JPH04167842A - Data transfer interrupt control system - Google Patents

Abstract

PURPOSE:To reduce number of times of interrupt to a CPU in the case of data transfer by providing a CPU, a memory section and a transfer control section in a processing element and providing an arrangement data section and a header section on the memory section. CONSTITUTION:A processing element (PE) 1 having a CPU 10 and a memory section 11 is provided with a transfer control section 12. The control section 12 is provided with an address latch means 12-4, a data number latch means 12-5 and a count means 12-6 counting a data number. Moreover, the control section 12 is provided with a comparator means 12-0 comparing values of the latch means 12-5 and the count means 12-6 and with an interrupt control information latch means 12-l, in which an interrupt signal 1 or a noninterrupt signal 0 is described as interrupt control information. Based on the output of the comparator means 12-0, either the interrupt control information 1 or 0 is sent to the CPU 10. Thus, number of times of interrupt of the PE to the CPU is considerably decreased.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art (Figures 4 to 6) Problems to be Solved by the Invention Means for Solving the Problems (Figure 1) Working Examples (Figures 2 and 3) Effects of the invention [Summary] Regarding the data transfer interrupt control method, the purpose is to significantly reduce the number of interrupts to the CPU of the processing element in a distributed memory parallel computer system. In a distributed memory type parallel computer system in which a plurality of processing elements 1 to 1 having processors and memories are connected, a processing element is provided with a transfer control section, and this transfer control section is provided with an address holding means, a data number holding means, and the like. , a counting means for counting the number of data, a comparison means for comparing each of the data number holding means and the call-out means, and an interrupt control information holding means, and as the interrupt control information, either an interrupt signal or a non-interrupt signal is provided. This interrupt control information is sent to the processor based on the output of the comparing means.

[Industrial Application Field] The present invention relates to a data transfer interrupt control method, and in particular, when transmitting data by distributing one message into multiple packets, the number of interrupts to the CPU of the source (SOURCE) is controlled. The objective is to reduce the overhead by reducing the

[Conventional technology]

In order to process a large amount of data at high speed, a processing element (processing element) having a processor and memory is used.
There is a parallel connection computer processing method in which processors (PE) are connected via a network and data is sent and received between the processors. Scientific calculations such as weather simulations are performed using such parallel computer processing methods.

At this time, the model to be calculated is cut into grids, and calculations are performed under given conditions such as flow velocity, pressure, temperature, etc. at each grid point. For example, in the case of weather forecasting, if the grid points are made finer, it becomes possible to make accurate predictions closely related to the area. However, the larger the number of grid points, the larger the amount of data, and when all the data is stored in the common memory shown at 100 in FIG. 4, the common memory needs to have a huge capacity.

For this purpose, each PE01P E 1 -P E n is connected through a network 101, and each PE is provided with a CPU and a memory M, respectively. Each of these PEs performs calculations on each grid point. In the example of FIG. 4, PEO performs calculations based on data in memory area SO among the common memory areas, PEI performs calculations based on data in memory area S1, and PE2 (not shown) performs calculations based on data in memory area S2. PEn performs the calculation based on the data in the memory area Sn. The results of these calculations are then
It is held in the memory M of. Note that the common memory 100
It is assumed that the data array in is arranged in the horizontal direction as shown by the arrow.

By the way, in the case of scientific operations, for example, multiplication between matrices may be performed. In this case, the PE requires data arranged vertically in the common memory 100 in FIG. 4, as shown by the dashed line. Part of this vertical arrangement data is held in its own memory M, but the rest needs to be transferred from other PEs. For example, as shown in FIG. 5, when arranging data, PEO requires data in the range of Sx shown by the dashed line.
It is necessary for PEI to transfer data 46 to 49.56 to 59-, and PE2 (not shown) transfers data 86 to 8.
It is necessary to transfer data from 9.96 to 99-. Note that the numbers in FIG. 5 indicate addresses.

For this kind of data transfer, PEI first uses 46 to
49 data is read out sequentially to create a packet and PEO
Next, the data 56 to 59 are sequentially read out to form a packet and sent to the PEO, and this process continues until all the required data is sent out. Similarly, PE2 (not shown) also does the same thing. For this data transfer, each PE is provided with a transfer control section (not shown).

[Problem to be solved by the invention]

By the way, in such a distributed memory parallel computer system, each PE generates an interrupt to the sender's CPU every time this sending packet is transferred to notify the end of the transfer. Therefore, in the case shown in Figure 5, PEI has 46-49), (56-59),
An interrupt was made to the CPU for each data transfer (66-69) and (76-79). P.E.
Since I also transfers data to other PEs in the same way, for example, as shown in FIG.
This results in a very large number of interrupts for data transfer, which increases CPU overhead, reduces data processing capacity, and makes it impossible to perform high-speed data processing.

Therefore, an object of the present invention is to provide a data transfer interrupt control method that reduces the number of interrupts to the CPU during data transfer, in order to improve these problems.

[Means to solve the problem]

In order to achieve the above object, in the present invention, as shown in FIG. 1, the PE is provided with a CPU 10, a memory section 12-, and a transfer control section 12 as typically shown in the PEI, and array data is stored in the memory section 12-. Section 12--0 and header section 12--
-1 is provided. The array data section 12--0 stores data or elements of a distributed area of the huge common memory 100 shown in FIG. 4, for example, the memory area S1.

The transfer control unit 12 includes a comparator 12-0 and a register 12-0.
1 to 12-6, +1 adders 12-7, 12 to 8, etc. are provided. Ona 13 is a driver.

[Effect]

Now, as shown in Figure 5, the PEI sends the address 46~49.56~59.66~69.76~7 to the PEO.
The case where each element of 9 is sent will be explained.

The PEI CPU10 is the header part 12 of the memory part 12-
--1 in this case, create 4 headers, write PEO as the destination PE (DEST PE) in header 1, write 4 as the length (LENGTH), and write 46 as the source side continuous address (SRCADR). Enter the destination address (predetermined) in the destination array data section, that is, the destination address
) and enter “0” as the interrupt control information (SRUPT).
”. Header 2 is the source side successive address (SR
It is the same as header 1 except that 56 is entered as the header CADR) and a destination address (DEST ADR) different from header 1 is entered. Header 3 is also similar to headers I and 2 except for (SRCADR) and (DEST ADR). However, header 4 is similar to header 1.2.3 (SR(,
ADR) and (DEST ADR) are not only different, but also "1" is written as interrupt control information (SRUPT).

When the CPU10 notifies the transfer control unit 12 of the sending address and activates it, the transfer control unit 12 reads the header part 12--1 from the memory unit 12-1 according to the read address written in the register 12-4, and Set the source side continuation address (46) to -3 and register 12-5.
The length (4) is set in the register 12-1, interrupt control information "0" is set in the register 12-1, and the counter 12-6 is initialized to (0). Then, the value of the register 12-3, ie (46), is set in the register 12-2 by the selector SEL.

As a result, the element at address 46 of memory section 12- is read out. Next, the +1 adder 12-7 adds the counter 12-
6 is incremented by 1 to become (1), and (46) of register 12-3 is incremented by 1 to become (47) by adder 12-8, and the element at address (47) is read out. , these operations are repeated, and the elements at addresses (48) and (49) are read out in sequence. When the element at address (49) is read, the value of counter 12-6 becomes (4),
Since the value matches the value written to register 12-5, comparator 12-0 outputs a match signal and turns on gate G, but the interrupt control information written to register 12-1 is "0". Therefore, no interrupt control signal is sent to the CPU 10.

Based on the match signal output from the comparator 12-0, the transfer control unit 12 creates a packet shown in FIG. 1(B) whose body is the element read from addresses (46) to (49), It is sent to communication network C and the transfer is controlled to PEO. Then, the header section 12--1 is read again, the presence or absence of the next header is checked, and the same control is performed based on header 2, and the elements at addresses (56) to (59) are transferred to the PEO.

Similar control is performed for header 3, and address (6
Elements 6) to (69) are transferred to Pl-,0. Similar control is performed for header 4, and address (
Elements 76) to (79) are transferred to the PEO. However, in this header 4, as shown in FIG. 1(C), interrupt control information "1" is written in the register 12-1, so this is notified to CPUl0, and CPUl0
Interrupt control will be performed.

In this way, in the past, the CPU
According to the present invention, the number of interruptions can be significantly reduced.

〔Example〕

An embodiment of the present invention will be described based on FIGS. 2 and 3.

FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of its operation.

In FIG. 2, the same symbols as in FIG. 1 indicate the same parts.

The PEO is configured similarly to the PEI, and includes a CPU 10', a memory section 12-', a reception control section 14, and a receiver 15. In FIG. 2, other configurations are omitted to show the case where elements are transferred from PEI to PEO.
The PEO is provided with a transfer control section, a driver, etc., similar to what is shown in the PEI, and the PEI is also provided with a reception control section, a receiver, etc., similarly to the PEO.

The memory section 12-'' is provided with an array data section 12-0' and a header section 12-1'.

The reception control unit 14 includes a comparator 14-0 and a register 14-0.
1 to 14-6, 71 adders 14-7, 14-8, etc. are provided.

In order to transfer data, P
The CPU 10 of the EI creates, for example, a head as shown in FIG. 1(C). From PEI to PEO, the dot-dashed line portion (46 to 49.56) of the memory area S1 shown in FIG.
~59.66~69.76~79), create header 1~header 4 as described above in the header section 12-,
Set the interrupt control information of header 4 to "1" and set other headers 1 to 3.
Now set it to "0".

When there are other elements to be sent from PEI to PEO, or when there are elements to be sent from PEI to another PP, the corresponding header 5.6, for example.
-Create.

After creating the required header in this way, the CPU
0 notifies the read destination address of the memory section 12- and activates the transfer control section 12. As a result, the following operation as shown in FIG. 3 is performed.

(2) The transfer control unit 12 initializes the counter 12-6 to zero. Further, the read destination address set in register I2-4 is transferred to register 1 via selector SEL.
2-2, and based on this, the hander section 12--0 is read out. From this, the source side read address (SRCA
DR) in register 12-3, and transfer data number (
LENGTH) is set in register 12-5, and interrupt control information (SRUPT) is set in register 12-1. Then, each data in the header section 12--1 is sent to the network C, and the originating PE number (PEI) is also sent to the network C.
, other information such as distance between elements is also included in network C.
The header information shown in FIG. 1(B) is sent to create a packet header.

■ The transfer control unit 12 sets the source side read address (SRCADR) of the register 12-4 in the register 12-2, accesses the memory unit 12-, takes out the first element, and sends it to the network. , is an element of the body of the packet.

■ And register 12-3 by +1 adder 12-8
+1 to the source side read address of +1 adder 1
2-7 increases the counter 12-6 by 1.2゜The address incremented by 1 in this register 12-3 causes the memory section 12-6 to be increased by 1.
, extracts the second element of the body, sends this element to the network, and writes it into the body of the packet.

The value of counter 12-6 and register 12
This process is repeated when the number of transferred data marked -5 does not match.

■ For example, when four elements are read out, the comparator 12-0 detects that the values of the counter 12-6 and the register 12-5 match, the gate G is turned on, and the value of the register 12-1 is read out. Since the set interrupt control information is [OJ at this time, the interrupt control signal is not sent to the CPU10, and the transfer control unit 12 reads the next header since it exists.

Note that when a match signal is detected from the comparator 12-0, the body portion is completed by the elements read so far, so this packet is sent out and received by the PEO.

(2) After this is done for header 1.2.3, it is also done for header 4. and comparator 1
When a match signal is output from 2-0 and gate G is turned on, rlj is written in register 12-1, so transfer control unit 12 sends an interrupt signal to CPU10, and CPU10 Based on this, interrupt processing is performed.

Then, the transfer control unit 12, as shown in FIG. 1(C),
Further, if there is a header 5, the CPU executes the CPU based on this, but if there is no header, the transfer operation ends.

On the other hand, when the PEO receives the packet, its header is decoded and the header section 12-' of the memory 12-' is
1', the destination PE number (DBSPE), the number of transferred data (LENGTH), and the source side continuous address (SRCA).
DR), destination address (DBST ADR),
Fill in the interrupt control information (SRUPT), etc., and perform reception control 1.
Notify 4 of the successive addresses and activate it.

At this time, the successive address is set in the register 14-4, and is set in the register I4-2 via the selector SEL, so that the transfer control unit 12 can transfer the address to the header part 12.
--1' is read, the destination address (DEST ADR) is written to register 14-3, and register 14-3 is read.
5, the number of transferred data (LENGTH) is set in register 14-1, interrupt control information (SRUPT) is set in register 14-1, and counter 14-6 is initialized to "0". Then, the destination address (DES) set in register 14-3 via selector SEL is stored in register 14-2.
TADR).

The first element transferred by the first packet is written to this destination address (DEST ADR), and at the same time, the counter 14-6 is incremented by 1, and the counter 14-6 is incremented by 1, and the counter 14-6 is incremented by 1. Since the address of register 14-3 is incremented by 1, the second transferred element is written.

When the fourth element is stored in the memory section 12-' in this way (the destination address normally indicates the array data section 1f-0', it is written to the array data section 12--0'). , a match signal is output from the comparator 14-0, the gate G is turned on, and since the interrupt control information set in the register 14-1 is "0" at this time, the CPU 10
'Do not send interrupt control signals to '.

In this way, when the reception control unit I4 writes each element transferred by the first to third packets and writes each element of the fourth packet, this time the register I4-1 l Since this [1] is entered, C
An interrupt control signal is sent to PUl0', and the CPUI
O' will perform interrupt processing.

In the above description, as illustrated in FIG. 5, one group of data, one message, is transferred by four data transfers, and an interrupt occurs at the end of this one message.

Furthermore, in the above description, in order to facilitate understanding, an example of a two-dimensional memory having an address structure as shown in FIG. 5 has been described, but the present invention is of course not limited to this.

〔Effect of the invention〕

According to the present invention, the number of interrupts to the CPU can be significantly reduced, so that in a distributed memory parallel computer system, when the transfer of transfer packet 1- is completed, the source CPU
C
It is possible to reduce over-hand on the PU and improve data processing capacity.

[Brief explanation of drawings]

Figure 1 is a diagram of the principle of the present invention. Figure 2 is a configuration diagram of an embodiment of the present invention. FIG. 3 is an explanatory diagram of the operation of the present invention, Figure 4 is an explanatory diagram of a distributed memory parallel computer system. Figure 5 is an explanatory diagram of two-dimensional array memory. FIG. 6 is an explanatory diagram of the header state. 10-CP IJ 12--Memory section 12-Transfer control unit 13- Driver

Claims (1)

[Claims] In a distributed memory type parallel computer system in which a plurality of processing elements having processors and memories are connected, a transfer control unit (12) is provided in the processing element, and the transfer control unit (12) includes: address holding means (12-3); data number holding means (12-5); counting means (12-6) for counting the number of data; data number holding means (12-5) and counting means (12-5);
A comparison means (12-0) for comparing each value of 6) and an interrupt control information holding means (12-1) are provided, and either an interrupt signal or a non-interrupt signal is entered as this interrupt control information, and the comparison is performed. A data transfer interrupt control system characterized in that the interrupt control information is sent to a processor based on the output of the means (12-0).