CN102551709A - Data acquisition circuit for electroencephalogram detection - Google Patents
Data acquisition circuit for electroencephalogram detection Download PDFInfo
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- CN102551709A CN102551709A CN2012100338729A CN201210033872A CN102551709A CN 102551709 A CN102551709 A CN 102551709A CN 2012100338729 A CN2012100338729 A CN 2012100338729A CN 201210033872 A CN201210033872 A CN 201210033872A CN 102551709 A CN102551709 A CN 102551709A
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Abstract
The invention discloses a data acquisition circuit for electroencephalogram detection, which comprises a main clock, a sequential logic circuit, an acquisition bus, a latched/series shift register and a plurality of buffer gates. Each branch circuit respectively transmits sampled synchronous data to one buffer gate; on the basis of the main clock, according to the requirements of a frame structure, the sequential logic circuit sends gate control signals from different paths of gate control signal wires at different moments to control to open the corresponding buffer gates and sends the synchronous data of the branch circuits onto the acquisition bus; after the synchronous data on each branch circuit is sent to the acquisition bus, the sequential logic circuit sends a latch signal to the latched/series shift register to load the synchronous data into the latched/series shift register; and the latched/series shift register outputs the loaded data in a series form to form a high speed data stream under the control of a serial clock. According to the acquisition circuit disclosed by the invention, the requirement on working of an electroencephalogram detection device is met.
Description
Technical field
The present invention relates to a kind of data sink collector that is used for the brain electro-detection, the data flow of multipath high-speed according to a data format that defines (frame structure), is accumulated one tunnel more high speed data flow, so that transmission and convenient is connected with computer.
Background technology
Development along with the modern medical diagnosis technology; People's bioelectric (being event related potential) of beginning the human brain thinking activities is produced detected and studied in recent years; This just requires more and more wideer to the frequency band of gathering EEG signals; And EEG signals often require multichannel to gather simultaneously, and each bandwidth chahnel is up to 0-2000Hz, and this just requires the sample frequency of each passage will reach more than the 4KHz at least.
For faint EEG signals, be accompanied by much bigger interfering signal often and exist simultaneously, EEG signals are amplified also unavoidably interfering signal is amplified simultaneously.For the EEG signals of microvolt level, want in the sampling system below 16, to offer a clear explanation and just must amplify 1000-10000 at least doubly, and interfering signal can make amplifier saturated like this.This is difficult to solve in the amplifier of routine to contradiction.Effectively solution is exactly to reduce the precision that amplification improves the AD conversion simultaneously, adopts 24 conversion accuracy through calculating, and amplification is as long as 5-10 doubly just can meet the demands.Big interfering signal can the way through digital filtering remove after the AD conversion is come in sampling.But, improve sampling precision and bring new problem again; Existing high-precision AD sampling A mostly is ∑-⊿ types, and it is to realize high-precisionly through sacrifice sample rate with the way of over-sampling, so sample rate is not high.
Conventional digitized electroencephalograph is the multichannel EEG signals of being introduced by electrode wires to be simulated respectively earlier amplify and filtering; Switch through the timesharing of analog switch then; Form one tunnel analogue signal and carry out the AD conversion, be sent to the data after the conversion in the computer through various communication medias again and handle.For the sample rate of each passage 4K Hz, even calculate according to 16 passages, the sample rate of a slice AD converter also will reach 64KHz, and these ∑-⊿ type AD converters for 24 precision can't be accomplished.Key is that ∑-⊿ type AD converters are carrying out high accuracy when conversion, the analogue signal that requires input must be same road continuously, can not pass through the switching of switch.
Therefore existing conventional digitized electroencephalograph do not resolve simultaneously to the multichannel EEG signals carry out wide bandwidth (0-2000Hz), high accuracy (24), the problem that high sampling rate is sampled.
The inventor is in order to address the above problem; Invented a kind of novel EEG checking device; As shown in Figure 1, comprise that pre-amplification circuit, anti-aliasing filter circuit, AD converter and analysis use computer, pre-amplification circuit, anti-aliasing filter circuit and AD converter have several respectively; Wherein each pre-amplification circuit, anti-aliasing filter circuit and an AD converter are connected successively and constitute a sampling and analog to digital conversion circuit respectively; Some samplings and analog to digital conversion circuit are connected in parallel, and form the several data flow, carry out the altofrequency sampling earlier along separate routes and change with high-precision AD; Compile the circuit data flow that each shunt conversion is good through a high-speed data again and accumulate a high-speed data-flow, deliver to analysis through data transmission circuit and analyze and handle with computer according to certain frame structure.Adopt this technological EEG checking device to satisfy the multichannel EEG signals are carried out two-forty (the every passage of 10 KHz) simultaneously, the requirement of high accuracy (24bit) sampling.Thereby make this device have good stability, characteristics such as capacity of resisting disturbance is strong, and frequency band range is wide can be applied to the analysis field of event related potential.Because this brain electro-detection technology is that the multichannel EEG signals are carried out the conversion of high-speed sampling and high-precision AD respectively.Thereby can produce the data flow of multipath high-speed simultaneously.These a large amount of multichannel datas must just can be imported computer easily according to the data flow that certain data format forms one tunnel more speed and handle.
Summary of the invention
Goal of the invention: the objective of the invention is to EEG checking device, a kind of data sink collector that can let multichannel data accumulate a high-speed data-flow is provided to inventor's design.
Technical scheme: the data sink collector that is used for the brain electro-detection of the present invention comprises master clock, sequential logical circuit, compiles bus, latchs/serial shift register and several buffered gates; Every shunt is delivered to a buffered gate with the synchrodata of sampling respectively; Said sequential logical circuit is based on said master clock, according to the requirement of frame structure, sees gate-control signal off on the gate-control signal line of never going the same way in the different moment, and control corresponding buffered door is opened, and the synchrodata of this shunt is delivered to compiled on the bus; After synchrodata in every shunt is sent to and compiles bus; Said sequential logical circuit is all seen latch signal off to said latching/serial shift register and synchrodata is packed in said latching/serial shift register, and the data that said latching/serial shift register will be packed under the control of serial clock are exported the formation high-speed data-flow with the mode of serial.
In order to cooperate the use of EEG checking device, the present invention compiles and has 70 shunt in the circuit, every along separate routes the synchrodata precision of sampling be 24bit; The said bus of compiling is 24bit; Said master clock is 24MHz.
Beneficial effect: the present invention compiles the circuit data flow that each shunt conversion is good and accumulates one tunnel high speed bitstream according to certain frame structure; So that fiber-optic transfer is connected with computer with making things convenient for through USB interface, the EEG checking device requirements of one's work have been satisfied.
Description of drawings
Fig. 1 is the structural representation of EEG checking device.
Fig. 2 is used for the data sink collector structural representation of brain electro-detection for the present invention.
The specific embodiment
Be elaborated in the face of technical scheme of the present invention down, but protection scope of the present invention is not limited to said embodiment.
Embodiment:Data sink collector of the present invention is used for EEG checking device.
As shown in Figure 1; EEG checking device; Comprise that pre-amplification circuit, anti-aliasing filter circuit, AD converter and analysis use computer; Said pre-amplification circuit, anti-aliasing filter circuit and AD converter have 70 respectively, and wherein each pre-amplification circuit, anti-aliasing filter circuit and an AD converter are connected successively and constitute a sampling and analog to digital conversion circuit respectively, and 70 samplings and analog to digital conversion circuit are connected in parallel; Form 70 circuit-switched data stream, compile circuit through a high-speed data again and accumulate a high-speed data-flow and deliver to analysis through data transmission circuit and analyze and handle with computer.Said data transmission circuit adopts optical fiber to isolate and the mode connect into analysis of USB interface is used computer.
Pre-amplification circuit: EEG signals at first are incorporated into pre-amplification circuit through the electrode that is attached on the human body scalp, are accompanied by EEG signals and have a lot of interference and artefact, and these garbage signals are often than the big hundreds of of useful EEG signals even thousands of times.This just requires preamplifier can amplify EEG signals has the ability that suppresses interfering signal again.Therefore adopt the instrument amplifier AD620 of high cmrr and high input impedance.In order not allow interfering signal that amplifier is saturated, amplifier is under the low gain state to be used, and amplification is controlled at 5-10 doubly.Like this dynamic range of input signal is expanded to ± 300mV.
Anti-aliasing filter circuit: under 10 KHz sample rates, satisfy the condition of sampling theorem in order to make AD converter circuit working at the back, must limit the frequency range that is input to the AD converter circuit signal.Present embodiment has adopted a step low-pass active filter circuit, with frequency band limits to the 0～2000Hz of output signal.
AD converter: present embodiment adopts high-precision AD converter to satisfy the requirement of differentiating microvolt level signal, and every road adopts the ∑-⊿ type AD converter ADS1251 of a slice low-cost and high-precision to carry out analog digital conversion.Switch the fatal influence that brings to ∑-⊿ type AD converters with regard to the interchannel of having avoided analogue signal like this, so the sample rate on each road reaches 10 KHz.
High-speed data compiles circuit: adopt structure of the present invention, data sink integrated one tunnel high speed data flow as shown in Figure 2, that multipath conversion is good is inserted synchronizing information, simultaneously so that computer is received the differentiation of the laggard row of channels of data.Be sent to a buffered gate respectively from the 24bit data of each shunt AD converter sampling, this buffered gate can be delivered to 24bit with the 24bit data respectively and compile on the bus under the control of gate-control signal.Sequential logical circuit is according to the requirement of frame structure; Earlier seeing control signal off from gate-control signal 0 in the beginning of every frame opens buffered gate; Synchrodata delivered to compile bus; Then sequential logical circuit see off latch signal data are packed into latch/serial shift register in, latch/data that serial shift register will be packed under the control of serial clock export at a high speed with the mode of serial.After this; See gate-control signal off on the gate-control signal line of never going the same way in the different moment; Controlling the buffered gate on corresponding road opens; The sampled data on this road delivered to compiles on the bus, then sequential logical circuit see off latch signal data are packed into latch/serial shift register in, latch/data that serial shift register will be packed under the control of serial clock export at a high speed with the mode of serial.So just formed one tunnel high speed data flow.So that fiber-optic transfer is connected with computer with making things convenient for through USB interface.All control signals all are based on the master clock of a 24MHz.
Optical fiber interface: according to the requirement of country to the medical apparatus and instruments compulsory standard, and the isolation voltage between patient's electrodes in contact and the network source must reach more than 4500 volts.The present invention adopts the fiber-optic transfer data to make that isolation voltage can be much larger than request of national standard between amplifier and computer.
USB interface: present embodiment adopts high speed USB 2.0 interface circuits, realizes the reception of computer sampled data and issuing of control command.
As stated, although represented and explained the present invention that with reference to specific preferred embodiment it shall not be construed as the restriction to the present invention self.Under the spirit and scope of the present invention prerequisite that does not break away from the accompanying claims definition, can make various variations in form with on the details to it.
Claims (2)
1. a data sink collector that is used for the brain electro-detection is characterized in that comprising, master clock, sequential logical circuit, compiles bus, latchs/serial shift register and several buffered gates; Every shunt is delivered to a buffered gate with the synchrodata of sampling respectively; Said sequential logical circuit is based on said master clock, according to the requirement of frame structure, sees gate-control signal off on the gate-control signal line of never going the same way in the different moment, and control corresponding buffered door is opened, and the synchrodata of this shunt is delivered to compiled on the bus; After synchrodata in every shunt is sent to and compiles bus; Said sequential logical circuit is all seen latch signal off to said latching/serial shift register and synchrodata is packed in said latching/serial shift register, and the data that said latching/serial shift register will be packed under the control of serial clock are exported the formation high-speed data-flow with the mode of serial.
2. the data sink collector that is used for the brain electro-detection according to claim 1 is characterized in that, has 70 shunt, and every synchrodata precision of sampling along separate routes is 24bit; The said bus of compiling is 24bit; Said master clock is 24MHz.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107898457A (en) * | 2017-12-05 | 2018-04-13 | 江苏易格生物科技有限公司 | A kind of method of clock synchronization between wireless brain wave acquisition device of group |
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| CN2300136Y (en) * | 1995-09-19 | 1998-12-09 | 张震 | Multi-guide, full functional electroencephalogram data collector |
| CN1275737A (en) * | 1999-05-27 | 2000-12-06 | 上海大唐移动通信设备有限公司 | Structure for information transmission bus |
| CN1529249A (en) * | 2003-10-17 | 2004-09-15 | 清华大学 | USB-based multi-parameter data obtaining system |
| CN200983200Y (en) * | 2006-09-08 | 2007-11-28 | 哈尔滨草青木秀电子技术有限责任公司 | Large-capacity precise digital collector |
| US20080306398A1 (en) * | 2007-06-06 | 2008-12-11 | Fujitsu Component Limited | Brain wave detecting apparatus |
| US20090149718A1 (en) * | 2007-12-10 | 2009-06-11 | Electronics And Telecommunications Research Institute | System for measuring bio-signals and method of providing health care service using the same |
| CN102314402A (en) * | 2011-07-29 | 2012-01-11 | 中国地震灾害防御中心 | Digital strong motion seismograph and multipath data acquisition interface thereof |
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2012
- 2012-02-15 CN CN2012100338729A patent/CN102551709A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2300136Y (en) * | 1995-09-19 | 1998-12-09 | 张震 | Multi-guide, full functional electroencephalogram data collector |
| CN1275737A (en) * | 1999-05-27 | 2000-12-06 | 上海大唐移动通信设备有限公司 | Structure for information transmission bus |
| CN1529249A (en) * | 2003-10-17 | 2004-09-15 | 清华大学 | USB-based multi-parameter data obtaining system |
| CN200983200Y (en) * | 2006-09-08 | 2007-11-28 | 哈尔滨草青木秀电子技术有限责任公司 | Large-capacity precise digital collector |
| US20080306398A1 (en) * | 2007-06-06 | 2008-12-11 | Fujitsu Component Limited | Brain wave detecting apparatus |
| US20090149718A1 (en) * | 2007-12-10 | 2009-06-11 | Electronics And Telecommunications Research Institute | System for measuring bio-signals and method of providing health care service using the same |
| CN102314402A (en) * | 2011-07-29 | 2012-01-11 | 中国地震灾害防御中心 | Digital strong motion seismograph and multipath data acquisition interface thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107898457A (en) * | 2017-12-05 | 2018-04-13 | 江苏易格生物科技有限公司 | A kind of method of clock synchronization between wireless brain wave acquisition device of group |
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