JP2000010934A - Bus arbitration system in multi-cpu system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decentralize loads on the CPUs in the multi-CPU system by equalizing the rates of the respective CPUs by composing the system of an arbiter part which arbitrates the bus use rights of the CPUs and a means which changes the priority of the CPUs according to the bus use time of the CPUs. SOLUTION: The system consists of the arbiter part which arbitrates the bus use rights of the CPUs and the means which changes the priority of the CPUs according to the bus use time of the CPUs. When the arbiter part 3 requests a measured time value (process time value of task), the CPUs (1 to 4) 1 send measured time values to the arbiter part 3. The arbiter part 3 gathers the measuring time by a gathering part. The measured time of the respective four CPUs (1 to 4) 1 is compared and select signals X and Y are sent to conversion cell parts of respective panels so as to give the bus use right in order from the CPU having the shortest measured time. The conversion cell parts determine the priority according to the logic of the conversion cells.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bus arbitration system for a multi-CPU system, and more particularly, to a bus arbitration system for distributing a load of a CPU of a communication system.

2. Description of the Related Art With the recent increase in speed and capacity of communication systems, development of devices using multiple CPUs has been required. For this reason, a processor mechanism for operating a plurality of CPUs as efficiently as possible and realizing the apparatus at a lower cost is required.

[0003]

2. Description of the Related Art In a conventional bus arbitration method, in order to acquire a right to use a bus, a priority number such as a panel ID is assigned to each CPU, and the priority number is changed every time a bus is acquired. Is used.

FIG. 9 is a conceptual diagram of a conventional system. In the figure, 1 is a plurality of CPUs, 2 is a processor bus for interconnecting these CPUs, and 3 is an arbiter unit connected to each CPU and arbitrating the processor bus.
In the figure, N CPUs 1 to N are provided. These CPUs have different priorities for each time zone.

For example, in time zone 1, CPU 1
The priority is higher in the order of 2, and in the time zone 2, CPU2, C
The priority order is higher in the order of PU3.
Is the highest priority. That is, according to each time zone, the smaller the number described, the higher the priority.

In the time zone 1, the CPU 1 has acquired the priority. Thereafter, in the time period 2, the CPU 2 acquires the priority, and in the time period 3, the CPU 3 acquires the priority. The CPU that has acquired the priority can perform signal processing using a processor bus (hereinafter simply referred to as a bus) 2.

FIG. 10 is an explanatory diagram of the processing time of the CPU. In the figure, the CPU 1 has the longest signal processing time, and the CPU 2 has the longest signal processing time. Each such CP
In performing the signal processing of U, each signal processing time is divided into small steps, and time division processing is performed for each divided step.

[0008]

The above-mentioned bus arbitration method is a method of distributing bus acquisition in one interrupt processing unit.
Further, since the processing time of the CPU differs for each interrupt, there is a problem that the usage rate of the CPU is not guaranteed to be completely averaged.

The present invention has been made in view of such a problem, and has been made in consideration of the above problems.
It is an object of the present invention to provide a bus arbitration system of a multi-CPU system capable of distributing the load of the CPU by equalizing the usage rate of the CPU.

[0010]

According to the present invention, each CPU has a function of measuring the task processing time locally, and when a certain time or the arbiter requests a task processing time value, each CPU sends the task processing time to the arbiter. Send that information. After that, the arbiter assigns the highest priority number to the CPU with the shortest task processing time or the CPU with the least number of task processing times, and changes the priority number of the CPU accordingly.

FIG. 1 is a block diagram showing the principle of the present invention. The same components as those in FIG. 9 are denoted by the same reference numerals. In the figure, reference numeral 1 denotes a plurality of CPUs connected to a processor bus 2. In the figure, four CPUs from CPU1 to CPU4
Are connected. An arbiter unit 3 is connected to each CPU 1 via the ID bus 4 and arbitrates the bus. The arbiter unit 3 supplies a priority determination signal to each CPU 1 in two bits of X and Y.

(1) A first invention for solving the above-mentioned problem is an arbiter unit 3 for arbitrating the bus use right of the CPU 1 in a system in which a plurality of CPUs 1 are connected via a processor bus 2, And changing means for changing the prioritization of the CPU 1 in accordance with the bus usage time.

According to the configuration of the present invention, priorities are assigned in ascending order of bus use time of the CPU 1.
Each CPU 1 can be used uniformly, and the load can be distributed.

(2) According to a second aspect of the present invention, in a system in which a plurality of CPUs 1 are connected via a processor bus 2, an arbiter unit 3 for arbitrating the bus use right of the CPUs and a processing task It is characterized in that it comprises a numbering means for each, and changing means for changing the priority order of the CPU 1 according to its priority.

According to the configuration of the present invention, by assigning a priority to each processing task, the CPU 1 having a large task can reduce the number of times of processing by arbitration of the arbiter unit 3, so that each CPU 1 is used uniformly. And the load can be distributed.

(3) In this case, when each of the CPUs has a function of locally measuring the task processing ratio, and when the arbiter unit 3 requests a task processing time value, each CPU 1
The arbiter unit 3 sends the information to the arbiter unit 3, and thereafter, the arbiter unit 3 assigns the highest priority number to the CPU 1 with the shortest task processing time or the CPU 1 with the least number of task processing times, and changes the priority number of the CPU 1 accordingly. Features.

According to the configuration of the present invention, by assigning the highest priority number to the CPU 1 with the shortest task processing time or the CPU 1 with the least number of task processing times,
PU1 can be used uniformly, and the load can be distributed.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 2 shows the selection signal and C
FIG. 2 is a diagram showing the relationship between PUs and their priorities, and is directed to the principle block diagram of FIG. The CPUs 1 to 4 are controlled according to the values of the priority order determination signals XY output from the arbiter unit 3.
The priority order up to PU4 changes as shown in the figure. For example, when XY = 01, the CPU 4 has the highest priority, and is followed by CPU1, CPU2, and CPU3.

FIG. 3 is a block diagram showing one embodiment of the panel 10 including a CPU. In the figure, reference numeral 1 denotes the CPU, which is connected to a processor bus and a control bus. Reference numeral 5 denotes a timer / processing count measuring unit which is connected to the CPU 1 and measures the processing time of each CPU or measures the number of processing tasks. Reference numeral 6 is connected to an ID bus, and an ID section for storing the priority of the CPU. Reference numeral 7 is connected to the ID section 6.
A conversion cell unit receiving a select signal from an arbiter unit, 8
Is a BWBID unit connected to the conversion cell unit 7 and storing the priority in BWB units.

The BWB ID is a backboard ID,
Indicates the priority of the initial state. The conversion cell unit 7 performs logical conversion of the select signal transmitted from the arbiter 3. I
D indicates the current priority of the CPU (panel). The timer measures the time required for the CPU to perform signal processing. The task processing frequency measurement measures the number of task processing performed by the CPU. The present invention will be described below using the circuit configured as described above.

First, when the panel including the CPU is inserted into the backboard, the BWB ID unit 8 sets the initial priority I
D is defined, passed through the conversion cell unit 7 and stored in the ID unit 6. Here, when the arbiter unit 3 transmits a control signal to the CPU 1, the CPU 1 activates the timer / processing number measuring unit 5 and measures the signal processing time or the number of processing of the task. That is, the task processing ratio of each CPU is measured. After completing a series of signal processing, the CPU 1 transmits the measured timer value to the arbiter unit 3.

The arbiter unit 3 transmits a select signal XY for determining the priority ID to the conversion cell unit 7 of the panel 10 with reference to the timer value. FIG. 4 is a block diagram for realizing the present system using four panels shown in FIG. In the figure, four panels A to D are used,
The present invention is not limited to this, and may be any number of panels.

FIG. 5 is a block diagram showing an embodiment of the arbiter unit 3. Reference numeral 21 denotes a collection unit that collects the measurement time or the number of times of processing of the task, 22 denotes a determination unit that receives the output of the collection unit 21 and determines the priority, and 23 receives the output of the determination unit 22 and supplies a select signal to each panel. ID to output XY
It is a conversion control unit. An arbiter 20 is connected to the ID bus.

First, the four panels 10 are inserted into the backboard. Initial priority I in BWB ID section 8 of each panel
D is defined. The priority order ID of the BWB ID part is ID
Stored in the unit 6. Here, the ID value is different for each panel.

The arbiter section 3 has an ID section 6 for four panels.
To give the bus priority to the panel (CPU) with the highest priority. After the CPU 1 releases the processor bus, an interrupt signal is input from the arbiter 20 to the CPU 1, and the signal processing time is measured by the timer of the timer / processing number measuring unit 5 in the panel 10. This signal processing time is measured for all four CPUs. in this case,
The measuring time is the processing time of the actual task.

Thereafter, when the arbiter unit 3 requests a measurement time value, the CPU 1 transmits the measurement time value to the arbiter unit 3. The arbiter unit 3 collects the measurement time in the collection unit 21. Then, the CPUs compare the measurement times of the four CPUs and transmit select signals X and Y to the conversion cell unit 7 of each panel in order to give the bus priority in order from the CPU with the shortest measurement time. The conversion cell unit 7 determines the priority ID based on the logic of the conversion cell (see FIG. 4).

By repeatedly performing the above operation, the CPU 1 having a large task can reduce the processing time by arbitration of the arbiter 3, so that the four CPUs can be used uniformly.

According to this embodiment, the CPUs are given priority in order from the one with the smallest bus access right, so that each CPU can be used uniformly and the load can be distributed.

Next, another operation of the present invention will be described. First, when the panel 10 is inserted into the backboard,
An initial priority ID is defined by the WB ID, passes through the conversion cell unit 7, and is stored in the ID unit 6. Arbiter part 3
Sends a control signal to the CPU, the CPU 1 activates the collecting unit 21 and measures the number of signal processing times of the task.
An example of the processing measurement is shown in FIG.

FIG. 6 is an explanatory diagram of tasks and the number of processes.
The CPU 1 includes a task A, a task B, and a task C. The CPU 2 includes a task A, a task B, and a task C. The CPU 3 includes a task A and a task C. CPUN includes only task B. Task A is for system monitoring and is the number of times
Task B has a length of 1 and is used for signal processing.
The task C is for signal processing, and has a length of processing times × 3.

The CPU 1 executes a task based on a task table prepared by an OS (operating system). Since the task number of the task is known before the execution of the task, the CPU 1 passes the task number to the timer / processing count measuring unit 5. The timer / processing count measuring unit 5 recognizes the type of task from the task number,
Measure the number of tasks. Here, the number of tasks is CP
It is not the number of tasks processed in U. It is a unit determined by a predetermined rule.

In FIG. 6, task A is assigned for system monitoring, task B and task C are assigned for signal processing, task A is for the number of CPU processings, task B is twice the CPU processing number, task C is Calculates the number of tasks as three times the number of processings by the CPU. This is performed for all four CPUs. Thereafter, when the arbiter unit 3 requests a task count value, the CPU 1 transmits the task count value to the arbiter 3.

The arbiter unit 3 converts the select signals X and Y to each panel 10 by referring to the measurement count values of the four CPUs and giving the bus priority in order from the CPU having the smallest task measurement count value. It is transmitted to the cell unit 7. The conversion cell unit 7 determines the priority ID based on the logic of the conversion cell.

By repeating the above operation,
A CPU with a large task can reduce the number of processes by arbitration of the arbiter, so that the four CPUs can be used uniformly.

According to this embodiment, by setting the priority for each processing task, a CPU having a large task can reduce the number of times of processing by arbitration of the arbiter. And the load can be distributed.

In this case, each of the CPUs has a function of locally measuring the task processing ratio, and when a certain time or the arbiter unit 3 requests a task processing time value, the CPU 1 sends the information to the arbiter unit 3. After that, the arbiter unit 3 sends the CPU 1 with the shortest task processing time
Alternatively, the highest priority number can be assigned to the CPU 1 with the smallest number of task processes, and the priority number of the CPU 1 can be changed accordingly. Therefore, according to this embodiment,
By assigning the highest priority number to the CPU 1 with the shortest task processing time or the CPU 1 with the fewest task processing times, each CPU 1 can be used uniformly and the load can be distributed.

FIG. 7 is a flowchart showing the operation of the CPU. When the CPU issues a bus request (S1), it acquires a bus (processor bus) (S2) and transfers data via the bus (S3). Next, when the data transfer is completed, the CPU releases the bus (S4).

Here, when an interrupt response is received (S
5), start the task (S6). At the same time, measurement of the task processing time is started (S7). When the task ends (S8), the task processing time measurement ends (S9).
The CPU counts up the processing time (S10).
Next, when the arbiter unit issues a processing time collection request for each CPU (S11), it collects the task processing time of each CPU and returns a collection response (S12). After collecting the measurement time, the arbiter unit determines the priority in the determination unit, changes the ID select signals X and Y (S13), and changes the ID (S14). The above processing is repeated.

FIG. 8 is a flowchart showing the operation of the arbiter unit 3. When the arbiter receives the bus request (S
1) Perform bus arbitration (S2). Then, after several seconds or about 1000 bus acquisitions (S3),
Information transfer is received from all CPUs (S5). The processing time is re-analyzed by the determination unit (S6), and the
The select signals X and Y are changed and output (S7).

In the above embodiment, the case where four panels are connected to the processor bus has been described. However, the present invention is not limited to this, and the case where an arbitrary number of panels are connected is described. Can be similarly applied.

[0041]

As described above in detail, (1) According to the first invention, in a system in which a plurality of CPUs are connected via a processor bus,
Arbiter section for arbitrating the bus use right of the CPU 1 and changing means for changing the prioritization of the CPU according to the bus use time of the CPU. To attach
Each CPU 1 can be used uniformly, and the load can be distributed.

(2) According to the second invention, a plurality of CPUs
An arbiter unit for arbitrating the right to use the bus of the CPU in a system in which the CPU is connected via a processor bus;
A number is assigned to each processing task, and the CPU is assigned according to its priority.
And the changing means for changing the prioritization of the tasks, the priorities are assigned to the respective processing tasks, and the CPU with the larger task can reduce the number of processes by arbitration of the arbiter unit. It can be used uniformly, and the load can be distributed.

(3) In this case, each of the CPUs has a function of locally measuring a task processing ratio, and when the arbiter unit 3 requests a task processing time value, the CPU sends the information to the arbiter unit. After that, the arbiter unit assigns the highest priority number to the CPU 1 with the shortest task processing time or the CPU with the fewest task processing times, and changes the priority number of the CPU accordingly. By assigning the highest priority number to the CPU with the fewest processing times,
Each CPU can be used uniformly, and the load can be distributed.

As described above, according to the present invention, the multi-CP
By equalizing the usage rate of each CPU in the U system, it is possible to provide a bus arbitration system of a multi-CPU system capable of distributing the load of the CPU.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a diagram illustrating a relationship between a select signal and a CPU priority.

FIG. 3 is a block diagram showing one embodiment of a panel.

FIG. 4 is a block diagram illustrating a configuration example of an entire system of the present invention.

FIG. 5 is a block diagram showing an embodiment of an arbiter.

FIG. 6 is an explanatory diagram of a task and the number of processes.

FIG. 7 is a flowchart showing the operation of the CPU.

FIG. 8 is a flowchart showing the operation of the arbiter.

FIG. 9 is a conceptual diagram of a conventional system.

FIG. 10 is an explanatory diagram of a processing time of a CPU.

[Explanation of symbols]

 1 CPU 2 Processor bus 3 Arbiter 4 ID bus

Claims (3)

[Claims] 1. A system in which a plurality of CPUs are connected via a processor bus, an arbiter for arbitrating the right to use the CPU, and a change for changing a priority of the CPU according to a bus use time of the CPU. CPU constituted by means
System bus arbitration system. 2. A system in which a plurality of CPUs are connected via a processor bus, an arbiter unit for arbitrating the right to use the CPU, a number assigned to each processing task, and a CPU corresponding to the priority.
A bus arbitration system for a multi-CPU system, comprising: a changing means for changing the priority order of the buses. 3. Each of the CPUs has a function of locally measuring a task processing ratio. When the arbiter requests a task processing time value, the CPU sends the information to the arbiter. 3. The multi-CPU system according to claim 1, wherein a highest priority number is assigned to a CPU having the shortest task processing time or a CPU having the fewest task processing times, and the priority number of the CPU is changed accordingly. Bus arbitration system.