CN1052356C - Programmable formatting synchronizer for multi-satellite receiving by remote sensing - Google Patents

Programmable formatting synchronizer for multi-satellite receiving by remote sensing Download PDF

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CN1052356C
CN1052356C CN97100692A CN97100692A CN1052356C CN 1052356 C CN1052356 C CN 1052356C CN 97100692 A CN97100692 A CN 97100692A CN 97100692 A CN97100692 A CN 97100692A CN 1052356 C CN1052356 C CN 1052356C
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data
satellite
chip
frame
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CN1171671A (en
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葛成辉
史久浩
朱正中
陈金树
杨海
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Tsinghua University
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Tsinghua University
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Abstract

The present invention relates to a programmable formatting synchronizer for satellite remote sensing and multi-satellite receiving, which is composed of five very large scale ultra-high speed programmable chips, wherein one chip is used for the I/Q separation of satellite data, two chips are respectively used for searching the frame synchronization heads of two I/Q paths of satellite data and protecting the fault tolerance, one chip is used for managing addresses for buffers, and the remaining chip is used for managing data for the buffers. Due to the adoption of a very large scale integrated circuit, the formatting synchronizer designed in the present invention has the advantages of small size, low cost, reliable operation and high speed, world and can cover all remote sensing satellites launched by worldwide countries before the year 2002.

Description

Programmable formatting synchronizer for multi-satellite receiving by remote sensing
The present invention relates to a kind of programmable formatting synchronizer for multi-satellite receiving by remote sensing, belong to the radio communication technology field.
Satellite remote sensing generally is to utilize artificial satellite in the earth is advanced by the track of prior design the earth to be observed, then the result who is observed is sent to ground with microwave, after ground station receives with tracking antenna, to signal amplify, demodulation, be called as the equipment that formats synchronizer by one then and format Synchronous Processing, inject the remote sensing satellite picture that main frame is processed into required standard then.Because satellite flight height height, the earth-circling cycle is short, and satellite remote sensing has become the strong observation instruments of each side such as meteorology, agricultural, Di Kuang, ocean, mapping, military affairs.Entered since the nineties, in view of the major contribution of remote sensing technology to the national economic development, the whole world not only developed country's great amount of investment develops its remote sensing cause, and developing country also does all one can to catch up one after another.In the equipment of satellite remote sensing ground station, comprise equipment such as receiver, antenna, computer, wherein format synchronizer because technology is special, become the key of earth station equipment, it is used for that the satellite data that aerial receiver receives is formatd processing and (comprises that I/Q separates, fault-tolerant anti-interference synchronously, go to disturb many steps such as decompressions) injection (INGEST) main frame then.Through formaing synchronous satellite data owing to deposit regularly, and through above-mentioned various processing, main frame just can be easily to each scan line location, goes forward side by side one to go on foot and carry out various preliminary treatment computings.
The remote sensing satellite earth station technology past abroad embargos China as a dual-use high-tech always.When Deng Xiaoping visited America after Sino-U.S. established diplomatic relations, the U.S. was as the friendly symbol of Sino-U.S., and to the ground station that Chinese exports one cover Landsat LANDSAT uses, this station was built up in 1986, promptly present remote sensing satellite ground station of the Chinese Academy of Sciences with 2,000 ten thousand dollars high prices.Wherein format synchronizer and just be worth hundreds thousand of dollars, because the satellite data code check that receives is too high, be recorded on the high-density tape earlier, 8 to 16 times of playback of reduction of speed then, enter main frame through the format synchronizer, this format synchronizer that can only receive single satellite data form is bulky, can not real-time processing data.
Ground station of institute of appropriation millions of dollar centering section of country expanded transformation in 1994, except that receiving Landsat LANDSAT, can also receive the ERS-1 of European Space Agency and the JERS-1 satellite of Japan, format synchronizer wherein is the product of Canadian MDA company, be called modular multifunctional satellite data processor (Modular Multifunctional Satellite Processor is called for short MMSP), it utilizes a plurality of circuit module plates to adapt to different satellite data forms respectively, be present international typical products, the NEC of Japan, the SPACETEC of Norway, 503 designs that waited of the domestic Ministry of Aerospace Industry are all similar with it.Though it no longer needs each satellite to use a format synchronizer respectively, but still each satellite is formatd processing with a large-scale module respectively, what modules what satellites just need.Therefore still bulky, cost an arm and a leg, and still be unable to do without the failure rate height, expensive high-density tape machine is as the necessaries of data reduction of speed.In sum, technology in the past is on structure, also need through a plurality of modules of the present invention, but the hardware of each module has only a kind of form, can not conversion, therefore because the form (comprising frame length, code check, synchronous code form etc.) of the descending data flow of every satellite all is different, therefore every new satellite, format synchronizer just need the new format synchronizer of a cover (as the H501 Landsat format synchronizer of Hughes company of ground station of the Chinese Academy of Sciences etc.).
The objective of the invention is to design programmable formatting synchronizer for multi-satellite receiving by remote sensing, adopt extensive field programmable device, reduced volume improves the operational reliability and the speed of service, and realizes formaing processing to crossing big portion remote sensing satellite both at home and abroad.Difference of the present invention is that whole logical circuits are to use software loading, therefore at the form of different satellites as long as design in advance with software, when receiving different satellite, load different software logics then at different satellite forms, and needn't change hardware, make same format synchronizer applicable to receiving a plurality of satellites.
The programmable formatting synchronizer for multi-satellite receiving by remote sensing The general frame of the present invention's design is seen Fig. 1, and it is made up of five programming devices, and they are respectively:
(1) be used to receive base band satellite-signal and synchronizing signal, and satellite data carried out the chip U201 that I/Q separates and distinguishes, comprise in this chip from the receiver demodulator:
The I/Q split circuit of forming by seven d type flip flops;
By input buffer, with or the loaded circuit formed of door group, register, output buffer;
(2) be used for the frame synchronization head of I/Q two-way satellite data is tracked down and arrested identical chips U202 and U203 with fault-tolerant protection, two chip blocks comprise respectively:
Form by input buffer, two condition door, be used for internal data and external bus two-way changing, total
The line buffer circuit,
Fault-tolerant by the data frame synchronization that device, shift register, XOR gate, high speed long word adder form of reading back
Track down and arrest circuit; (3) be used for the chip U204 that buffer address is managed, this chip comprises:
Put register, data frame length and the interframe counting circuit that device, counter, comparator form that read back by giving,
By frame protection counter, comparator, register, α several preset device, data frame that device is formed that reads back
The protection counting circuit,
By register, arbitrated logic device, data frame protection and the arbitration circuit that device forms that read back,
The I/O management circuit of forming by decoder, bus buffer, register, decoder,
By 7 groups with or the alternative selector formed of door,
By 11 groups with or the alternative selector formed of door.(4) be used for the chip U205 of buffer data management, this chip comprises:
By 4 groups with or the sheet formed of door select decoder,
By register, with door or door, the read-write moderator formed of clock,
By 2 shift registers, 8 32 bit data transducers that 32/8 bit pads are formed.
Effect of the present invention is the design concept that breaks traditions, adopt the extensive Field Programmable Gate Array (Field Programmable Gate Array FPGA) that newly grew up in recent years to design and be used for the format synchronizer of many stars, its advantage is:
A) when receiving different satellite, do not need more exchange device or module, only need FPGA is reloaded, its replacing speed needs only several milliseconds.
B) owing to adopted very lagre scale integrated circuit (VLSIC), so volume compression is to the plate level, and component number reduces by 1~2 order of magnitude, has improved reliability greatly, and cost also reduces an order of magnitude.
C) owing to having adopted very lagre scale integrated circuit (VLSIC), on circuit design, allow to adopt complicated logic, improved performance greatly, for example work as signal and be subjected to the serious interference (error rate>10 -3, normally should be<10 -6) time, system is still working properly.
D) improved processing speed greatly, reached interior 105Mb/S at present in the laboratory, (external product general (30Mb/S) can format processing in real time to domestic and international most satellite like this, avoids adopting unreliable equipment such as high-density tape machine; Real-time 0 grade of generating or 1A level data can directly provide department's uses such as mapping.Preparation was brought up to 150Mb/S in one, two year, like this can topped 2002 before all remote sensing satellites of countries in the world emission.
Description of drawings: Fig. 1 is an internal structure explanation block diagram of the present invention.Fig. 2~Fig. 5 is a general system diagram of the present invention, wherein Fig. 2, Fig. 3, Fig. 4, Fig. 5 be respectively total figure upper left,
Upper right, lower-left, bottom right each several part.Fig. 6 is I/Q split circuit figure.Fig. 7 is loaded circuit figure.Fig. 8 is the bus buffer circuit diagram.Fig. 9, Figure 10 are the fault-tolerant arrest circuit diagram of frame synchronization.Figure 11 is the fault-tolerant arrest theory diagram of frame synchronization.Figure 12 is frame length counter and interframe counting circuitry.Figure 13 is frame protection counter circuit figure.Figure 14 is frame synchronization protection and arbitration circuit figure.Figure 15 is the synchronous state machine schematic diagram.Figure 16 is inputoutput data management circuit figure.Figure 17 is alternative selector circuit figure.Figure 18 is alternative selector circuit figure.Figure 19 translates decoding circuit figure selectively for sheet.Figure 20 is read-write arbitration circuit figure.Figure 21 is 32 bit data change-over circuit figure devices.
Below in conjunction with accompanying drawing, introduce content of the present invention in detail.
The core of native system mainly is made of five ultra-large ultrahigh speed programming devices (FPGA), and general system diagram is seen Fig. 2~Fig. 5, and that adopt at present is the XC3164 and the XC3190 of Xilinx company, and each FPGA constitutes circuit U a 201~U205, wherein:
1)U201(XC3164)
Be mainly used in base band satellite data and the synchronizing signal of reception, and satellite data is carried out the I/Q separation and distinguished (because of most of remote sensing satellites adopt the QPSK modulation) from demodulator.Comprise following circuit in this chip:
A) the I/Q split circuit is seen Fig. 6.Because input traffic generally is to occur with the form that the I/Q position intersects, and signal processing must be carried out respectively I and Q, being input as of this circuit from next data ' DATA IN ' and clock ' the CLK IN ' of demodulator, have seven d type flip flop: D1~D7 among the figure, when clock is next interim one by one, data are advanced the according to the form below beat, ' Data1 ', ' Data2 ' is intermediate object program, triplex row below such three outputs just will become in the table can be seen ' CLKDIV2 ' clock after being two divided-frequency, ' has only ' I ' signal on the DATA I ', ' have only ' Q ' signal on the DATA Q ', so just finished the I/Q separation.The IxQ signal is used to make the IQ exchange among the figure, sees below relevant " synchronous state machine " joint and introduces.
DATAIN I1 Q1 I2 Q2 I3 Q3 I4 Q4 I5 Q5 I6
Data 1 - I1 Q1 I2 Q2 T3 Q3 I4 Q4 I5 Q5
Data 2 - - I1 Q1 I2 Q2 I3 Q3 I4 Q4 I5
CLKDIV2 1 0 1 0 1 0 1 0 1 0 1
DATAQ - - - Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4
DATAI - - - I1 I1 I2 I2 I3 I3 I4 I4
B) U202, U203, U204, the loaded circuit (see figure 7) of U205.Because every FPGA circuit all needs to load, if all directly carried out by main frame, then interface will be too loaded down with trivial details, so adopt the Indirect Loaded way among the design, promptly load U201 earlier, form this circuit, load for other circuit by this circuit again.This circuit is made up of input buffer, register, NAND gate group, output register.The major function of this circuit is fairly simple, and it is a decoding circuit.Provide chip selection signal AO by main frame, CS, D0~D3 chooses a slice in U202~U205, and IOR, IOW determine read-write, provide answer signal by downloading answering circuit then, and answer signal is transported to U202~U205.2) U202, U203 (2 XC3190)
Function and the structure of U202 and U203 are identical, are mainly used in respectively the frame synchronization head of I/Q two-way satellite data is tracked down and arrested and fault-tolerant protection, also are the main contents of format Synchronous Processing.As long as continuously in the signal frame synchronization is being tracked down and arrested, continuously signal just can be divided into many independently frames, and the rule of data arrangement can obtain, and also just might further carry out hardware or software processes.
The method that the frame synchronization head is tracked down and arrested mainly adopts matching method, because frame swynchronization code is in advance known, therefore needs only to give earlier in circuit and packs into, and code stream comes then to compare by turn, if both are in full accord, just can think that frame synchronization is caught in.This point is as long as the people that digital circuit is familiar with is easy to realization.Problem is to contain noise in the satellite data inevitably, does not just recognize if there is error frame to track down and arrest circuit synchronously in the frame swynchronization code slightly.Format will be extremely unreliable synchronously like this.Therefore the fault-tolerant safeguard measure of essential adding can steady operation.This is the key of format synchronization dependability.
Therefore in this part, added fault-tolerant and the frame synchronization safeguard measure, guaranteed under the very high mal-condition of the error rate, still can reliably the frame synchronization head be captured.
Comprise following parallel circuit in this chip: a) bus buffer (see figure 8).
Be mainly used in the two-way exchange of internal data and external bus, have 8 tunnel identical circuit, every road circuit is by defeated
Going into buffer and triple gate forms.External data 000~007 through IBUF and TBUF can enter inner I00~
I07, internal data can be gone out to 000~007 of outside through OBUFZ by I00~I07; DE and DIO are logical
Whether cross NAND201 and NAND202 control path passes through and reaches direction.
B) the fault-tolerant arrest circuit of frame synchronization (seeing Fig. 9 and Figure 10).
For the principle of the fault-tolerant arrest circuit of frame synchronization is described, can be with reference to Figure 11.
The input satellite data enters shift register and compares (theoretical and actual proof generally get 32 enough) with ' give and put synchronous code ' of having packed in advance by turn, comparative result such as identical, XOR gate output is " 1 ", otherwise be " 0 ", in high speed long word adder, carry out additional calculation, as there is not a noise jamming, adder output should be 32, exist if any error code, then adder output will be less than 32, as give and put fault-tolerant thresholding and be made as 29, then in the high speed serialization comparator if error code less than 32-29=3, just can make to detect to be output as " 1 ", promptly confirm catching of synchronous code.
Corresponding with above-mentioned functional-block diagram, have 15 row in Fig. 9 and Figure 10 circuit from left to right: first row: totally 5 data circuit HX244 that reads back is used for giving the reading back so that check of the value of putting with above-mentioned; Secondary series: (5 * RD8), first RD8 is used to deposit ' give and put fault-tolerant thresholding ' to totally 5 eight bit registers;
The 2nd~5 RD8 is used to deposit give and puts synchronous code; The 3rd row: 4 eight bit register RD8 constitute 32 bit shift register, and the satellite data of reception is moved therein by turn
The position; The 4th row: be 32 XOR gate, be used for satellite data and give the value of putting comparing; 4 register RD8 of the 5th row are used for 32 bit comparison results are latched.The 6th row~the ten five row: equal high speed long word adders for constituting by CADD32, calculate the satellite data synchronous code and
Give the number that the value of putting conforms to after relatively mutually, and first row's high speed serialization comparator with give the fault-tolerant thresholding of putting
Relatively, as long as produce more than or equal to fault-tolerant thresholding, just export " FIND " signal, the expression synchronous code
Find.3)U204(XC3190)
Be mainly used in the address administration of buffer, because the satellite data in the buffer should write, read by interface by main frame again, the address administration of buffer also must be arbitrated.
Comprise following parallel circuit in this chip:
A) frame length and interframe counting circuit (seeing Figure 12).The purpose of frame length counter is to get back to the frame head position automatically after the every frame of satellite data is over, and repeats original work.After satellite was determined, its frame length also determined, the frame length counter has been arranged after, even if do not detect synchronizing signal for the second time, system can continue to keep operate as normal.
On the frame length counter principle with general digital circuit in counter do not have differently, the characteristics of this circuit are that counter length is long, and rate request is high, counter is easy to take place the carry mistake and makes counting loss at fast state.
The frame length value is given in advance and being put at two RD8 of register (16), the interframe count value is given in advance putting in RD4 of register (4) and (is seen the parallel circuit figure upper left corner), six RD8RD counters are exported in 8 comparator EQ4 and are given the value of putting and compare, when the consistent counting that reaches when giving the value of putting, 8 EQ4 are consistent to export ' 1 ', through what with export CLR0 behind the door, also export CLR1 as counter O reset simultaneously.Three HX244 in upper right side are used for just giving the data of the putting register usefulness that conducts a survey of reading back.
B) frame protection counting circuit (seeing Figure 13).
In order to make frame synchronization reliable; except that fault-tolerant, also should add " frame protection ", promptly when the error rate is very big, may still track down and arrest after fault-tolerant less than synchronizing signal; then should allow in α time to lean on the frame length counter and continue to keep system works, thing that frame protection counter will do that Here it is.The optimum value of α value should be come as required to select by the user.
The circuit theory long counter at same frame of frame protection counter, just figure place has only 8, and is therefore simple relatively.The α value is given and being put in a RD8, then with 2 frames protection counter YFMO4 in value in 4 comparator EQ4 relatively, when count value≤α, the LOCK=1 of output, system lock enters the protection attitude.When count value>α, output LOCK=0, at this moment no longer protection.
C) frame synchronization protection and arbitration circuit (seeing Figure 14).
Above each several part will constitute complete " a frame synchronization state machine " also needs to add " frame synchronization protection and arbitration ", and Figure 15 is " frame synchronization state machine " complete theory diagram.
The principle of this unit is as follows:
1) when frame synchronization just often, per frame period finishes, promptly the frame length counting is returned; In the time of zero, just in time can detect frame synchronization, at this moment, frame synchronization is in the normal state or goes into to lock attitude;
2) when the frame synchronization step-out, in the finish time in frame period, can't detect normal frame synchronizing signal, this will start frame synchronization protection counter, make system enter frame protection attitude, utilize the count status of frame length counter simultaneously, keep original frame regularly;
3) give when deciding the protection number of times when the protection counter surpasses, system enters the losing lock attitude, at this moment protects counter no longer to increase, and rests on maximum;
4) when the frame synchronization arbitration unit is in the normal state or protects attitude,, be considered to puppet and ignored synchronously at the frame alignment detection signal that frame synchronization occurs midway;
5) when the frame synchronization arbitration unit is in the losing lock attitude, all will think real synchronizing signal at the frame synchronization detection and localization signal that the frame period any place occurs, at this moment protect counter O reset, normality is got back to by system;
When 6) not having frame alignment to detect in continuous α the frame time of losing lock attitude, an IxQ signal will be sent in this unit, so that the IQ split circuit is adjusted phase place, and examination again;
7) because the IQ split circuit needs this unit to carry out phase modulation proofreaies and correct, so when essential I, Q frame alignment signal occurred simultaneously when judging I/Q two-way frame alignment detection signal, ability acknowledgement frame detection and localization was effective, otherwise invalid.LOCK=1 represents that system goes into the lock state among Figure 15, and CLRI=1 represents that the frame period is in done state, at this moment should export CLRO and make the frame length counter O reset, and make the interframe counter increase 1, with the address of change vertical sync circuit to the buffering visit.CAPI and CAPO represent that the frame synchronization of importing I and Q detects, and CAPT represents that effective frame synchronization detects, and LOSS represents that system loses frame synchronization one time, and this signal is used to drive frame protection counter to be counted.
Above-mentioned frame synchronization arbitration can reduce following truth table with the protection process:
!LOCK CLRI CAPI CAPQ CLRO CAPT LOSS
Go into to lock attitude In cycle 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Go into to lock attitude The cycle tail 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 1 1 0 1 1 0 1 1 1 0
The losing lock attitude In cycle 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0
The losing lock attitude The cycle tail 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 0 0 1 0 0 1 0 0 1 1 0
Each signal is all consistent with Figure 15 with logic in the circuit diagram, therefore explain no longer that wherein 8 FD are register, arbitration circuit is formed with door AND and 4 or an OR2 by 7, circuit state conforms to above-mentioned truth table, and right-hand HX244 is used for each state value is read back so that check.D) inputoutput data management (seeing Figure 16).
Purpose is different static random access memory SRAM (U301~U308, down together) port is sent read-write
Order.The decoding circuit that constitutes by eight NAND gate NAND and two NOR gate NOR form ITOO,
OT01, RR and WW drive bus buffer YBUSBUF2, through register RD4 and 2 decoders
YD3 respectively to each address port of sram cache (Y0~Y7, A0~A7) select, to (R0~
R7) send to sram cache and read or write order, composition data flows to the configuration management of each address of buffer memory.E) alternative selector (seeing Figure 17).
This selector by 7 with or the door GMUX form.Input Cx, Ax, CNB, output Yx, (x=0~5).
Cx Ax CNB Yx
0 X 0 0
1 X 0 1
X 0 1 0
X 1 1 1
F) alternative selector (seeing Figure 18).
This selector by 11 with or the door GMUX form.Input Ax, Bx, AB, output Yx, (x=0~10)
Ax Bx AB Yx
0 X 0 0
1 X 0 1
X 0 1 0
X 1 1 1
More than two selectors constitute management and switching together to the sram cache address bus, purpose is distinguished reading and writing of SRAM data, because both addresses are different, need between to carry out alternative and switches.Selector circuit is simple gate circuit, does not need to explain.
4)U2055(XC3190)
Be mainly used in the data management of buffer, guarantee that satellite data is correctly become the parallel buffer that also writes frame by frame by serial.Comprise following parallel circuit in this chip:
A) sheet selects decoder circuit (seeing Figure 19).
This circuit by 4 groups with or the door PMCS form.Be used for according to read-write arbitration circuit ruling as a result CNB determine that sheet selects MCS should assign to the Na Yilu of MCS0~MCS3.Be input as address A0, A1, ruling is CNB as a result, and sheet selects MCS, is output as MCS0~MCS3, and its rule is:
When CNB=1, MCSx=MCS, (x=0~3) no matter and A0, A1 is how.At this moment, system carries out the visit of 32 parallel-by-bits to buffer memory, is unit with 32.
When CNB=0, MCSx=X, X=[A1, A0].At this moment, system carries out 8 visits by host computer control, is unit with the byte.
B) read-write arbitration circuit (seeing Figure 20)
Host access application (R/W) is deposited in FDRD, and the visit application of frame synchronization system is deposited in FDCRD, constitutes the arbitration combinational logic with door AND2B2 and OR3 or door, BR=Bus Read wherein, BW=Bus Write, CW=hardware Write.
This circuit below forms the SRAM timing source by three FD and combinational logic, and this timing source drives memory and reads and writes in a periodic manner.
C) data converter circuits (seeing Figure 21).
It is by 2 shift register YS2P16, and 8 32/8 bit pad YD328 constitute.YS2P16 is used for string and conversion, is universal circuit.The YD328 purpose is for to transfer 32 bit data to 8.Because frame synchronization system is with 32 work, SRAM writes by 8, changes when needing, and each circuit is general circuit.
Except that above main circuit, also have a small amount of auxiliary circuit in the synchronizer of the present invention, see total figure:
1) U102, U103, U105 are G20V8 gate array (GAL) circuit, are mainly used in to carry common bus interface address.U101, U104 are that 74ALS245 is a three-state transceiver, are used for bus and connect with the data between each main circuit are ternary.U106 is a quartz crystal.
2) U301, U302, U304, U305, U306, U307, U308 are static random access memory (HM628128), are used for the buffer-stored that satellite data enters host process.
3) U401, U402 are respectively MC10116 and MC10125, are used for the level conversion between ECL and the TTL.U403 is 7905 type pressurizers, and purpose provides required negative voltage for giving U401 and U402.
Can see that in conjunction with above-mentioned schematic diagram native system can finish the repertoire as remote sensing satellite ground station format synchronizer.
Because main logical circuit is all at U201~U205 in the native system, it all is the on-the-spot time journey of taking charge of, that is to say that its hardware just can be changed in several milliseconds, concerning different remote sensing satellites, its main data differences is form and code check, concerning different satellite orbits, main difference is the error rate of signal.Utilize programmable system just can adapt to different forms, comprise the sign indicating number type of synchronous code, the code length of data, the arrangement of major-minor frame, the error rate not equal can change by the logic that changes main circuit and adapted to, and needn't use other hardware logic electric circuit.
More than all chips be installed on the plug-in card, simple in structure, number of elements is few, not only brings the convenience in the production, and has improved reliability and maintainability greatly.

Claims (1)

1, a kind of programmable formatting synchronizer for multi-satellite receiving by remote sensing is characterized in that this synchronizer can by five
The programming device is formed, and they are respectively: (1) is used to receive base band satellite-signal and the synchronizing signal from the receiver demodulator, and satellite data is advanced
The chip (U201) that row I/Q separates and distinguishes comprises in this chip:
The I/Q split circuit of forming by seven d type flip flops,
By input buffer, with or the loaded circuit formed of door group, register, output buffer; (2) be used for the frame synchronization head of I/Q two-way satellite data is tracked down and arrested identical chips (U202 with fault-tolerant protection
And U203), two chip blocks comprise respectively:
Form by input buffer, triple gate, be used for internal data and external bus two-way exchange, total
The line buffer circuit,
Fault-tolerant by the data frame synchronization that device, shift register, XOR gate, high speed long word adder form of reading back
Track down and arrest circuit; (3) be used for the chip (U204) that buffer address is managed, this chip comprises:
Put register, data frame length and the interframe counting circuit that device, counter, comparator form that read back by giving,
By frame protection counter, comparator, register, α several preset device, data frame that device is formed that reads back
The protection counting circuit,
By register, arbitrated logic device, data frame protection and the arbitration circuit that device forms that read back,
The I/O management circuit of forming by decoder, bus buffer, register, decoder,
By 7 groups with or the alternative selector formed of door,
By 11 groups with or the alternative selector formed of door; (4) be used for the chip (U205) of buffer data management, this chip comprises:
By 4 groups with or the sheet formed of door select decoder,
By register, with door or door, the read-write moderator formed of clock,
By 2 shift registers, 8 32 bit data transducers that 32/8 bit pads are formed.
The connecting relation of above-mentioned each chip is: (U201) receive behind receiver next I/Q and CLK signal, treated the I/Q two-way is sent (U202) after separately respectively and (U203) carries out the fault-tolerant search processing of frame synchronization, and then be sent to (U204) and (U205) carry out data and address administration, deliver to the RAM buffer memory again, enter main frame by pci bus interface again.
CN97100692A 1997-03-14 1997-03-14 Programmable formatting synchronizer for multi-satellite receiving by remote sensing Expired - Fee Related CN1052356C (en)

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CN101419278B (en) * 2008-12-05 2011-08-17 航天恒星科技有限公司 Multichannel high speed remote sensing data acquiring and processing device
CN107888320A (en) * 2017-12-11 2018-04-06 国网浙江省电力有限公司 A kind of frame synchronization detection method based on OTN
CN110875867B (en) * 2020-01-20 2020-05-01 南京凌鸥创芯电子有限公司 Bus access arbitration device and method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4435826A (en) * 1980-09-05 1984-03-06 Hitachi, Ltd. Frame synchronizer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4435826A (en) * 1980-09-05 1984-03-06 Hitachi, Ltd. Frame synchronizer

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