CN101067972A - Memory error-detecting and error-correcting coding circuit and method for reading and writing data utilizing the same - Google Patents
Memory error-detecting and error-correcting coding circuit and method for reading and writing data utilizing the same Download PDFInfo
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Abstract
This invention relates to an error-check and error-correction code circuit for storages and a method for reading and writing data by it taking matrix G as a logic core including: a decoding process and a coding process and a method for writing in data by this method. Apart from a decoding process and an error correction process, it also includes a coding process, and finally puts forward an error check and correction and coding circuit for realizing said two methods including a decoder, an error-correction circuit, a coding circuit, an interface circuit and related data transmission circuit so as to simplify layout of bottom circuit and speed up operation speed of circuits.
Description
Technical field
What the present invention relates to is the implementation method of ECC in a kind of memory device, what be particularly related to is the method for read data EDC error detection and correction from storer, and the disposal route of utilizing the write memory data of said method realization, be to realize above-mentioned two kinds of pairing circuit structures of method at last.
Background technology
Along with development of integrated circuits, storage unit will occupy the chip area of the overwhelming majority.Memory property is very big to the performance impact of chip, therefore needs to guarantee the hundred-percent accuracy of storage data.But any storer all faces the challenge of reliability and yield rate, reduces along with the increase of integration density such as signal to noise ratio (S/N ratio); The soft error that cosmic rays causes storage unit; The deviation of technology and the defective of material cause the storer yield rate to reduce or the like.Therefore need a kind of effective method to address these problems.
ECC (Error Checking and Correcting) is the implication of bug check and correction.When data mistake of storage unit generation, this mistake will be found and locate to the ECC circuit, carries out corresponding error correction then.It not only simply is used for correcting the hard error that produces in the soft failure that caused by ray and the manufacture process, also is used for correcting the mistake of other form.Such as: ecological deterioration (voltage fluctuation, temperature raises) causes error in data; The technology disturbance causes that parameter changes, and causes the read-write failure; Some other random error etc.
Existing ECC method great majority are not done optimization to the G matrix, redundant data is not done to simplify and handle, when process more and more hour, this pretreated ECC circuit produces without the upper strata " spinoff " just highlights---the circuit complexity is huge, and the line area occupied is too big; Redundant bit takies too much memory span, thereby causes circuit delay big, influences speed.
The integrated level of chip is more and more higher, the area of memory module is increasing, and ECC is faced with and how improves encoding rate and make check bit take memory span less, how to simplify peripheral logical circuit when device size reaches deep-submicron, accelerate challenges such as circuit speed.
For solving the defective of above-mentioned existence, creator of the present invention is through long term studies and test the technical scheme disclosed in this invention that obtains finally.
Summary of the invention
The objective of the invention is to, a kind of memory error-detecting and error-correcting coding circuit is provided and utilizes its method that reads and writes data, thus the placement-and-routing that realizes simplifying the bottom circuit, and travelling speed, the coding circuit simplification degree that adds fast-circuit is obvious, encoding rate improves greatly.
For achieving the above object, the technical solution used in the present invention is, a kind of bug check and error correction method from the memory read data at first is provided, and it step that comprises is:
Step a1: decode procedure, the step that wherein said decode procedure comprises is:
Step a11: from storage unit, take out data bit and check bit, calculate syndrome according to the H matrix, described H matrix is that G matrix and unit matrix are formed, the figure place of described data bit is corresponding with G matrix column number, the figure place of check bit is corresponding with the columns of unit matrix, wherein the G matrix is divided into two parts up and down, and one of them part is every four correlative characters that repeat row, and phase ortho position correlative character is different; Per four the phase ortho positions of another part are one group, have identical correlative character, but correlative character difference between every group, and syndrome has a correlativity for each data bit and check bit in the H matrix data are carried out the value of XOR;
Step a12: the data bit of taking-up and check bit be according to G matrix correlation feature, by the control of address information, takes out 1 bit data that needs error correction from per four row, and these data and check bit and described syndrome are entered into error correction procedure together;
Step a2: error correction procedure, it step that comprises is:
Step a21: find out the data that extract in the data bit of from storer, reading and the error bit in the check bit according to syndrome, and correct the logical value of this error bit, obtain correct check bit sum data bit;
Step a22: output correct data position and check bit;
Next provides a kind of and writes the method for data to storer, and it has utilized above-mentioned bug check and error correction method from the memory read data to realize that it step that comprises is:
Step b1: decode procedure, the step that wherein said decode procedure comprises is:
Step b11: from storage unit, take out data bit and check bit, calculate syndrome according to the H matrix, described H matrix is that G matrix and unit matrix are formed, the figure place of described data bit is corresponding with G matrix column number, the figure place of check bit is corresponding with the figure place of unit matrix, wherein the G matrix is divided into two parts up and down, and one of them part is every four correlative characters that repeat row, and phase ortho position correlative character is different; Per four the phase ortho positions of another part are one group, have identical correlative character, but correlative character difference between every group;
Step b12: the data bit and the check bit of taking-up are given interface circuit, by the control of address information, take out corresponding 1 bit data from every four figures certificate, and these data and check bit are entered into error correction procedure together;
Step b2: error correction procedure, it step that comprises is:
Step b21: find out the data that extract in the data bit of from storer, reading and the error bit in the check bit according to syndrome, and correct the value of this error bit, the check bit sum data bit after obtaining to proofread and correct;
Step b22: the check bit sum data bit behind the output calibration;
Step b3: cataloged procedure, the step that wherein said decode procedure comprises is:
Step b31: carry out XOR with the data of input and the data bit behind the above-mentioned steps b22 output calibration, obtain the logical value of new data; Again according to correlative character in the G matrix, the control by address information produces new check bit to logical value and former check bit XOR with data of correlativity, exports and gives storer;
Step b32: according to address information, the former data bit corresponding positions that reads is replaced to the data bit of input from storer, produce new data and deposit in the storer;
A kind of memory error inspection and error correcting code circuitry are provided at last, and it comprises:
One demoder, the data and the check bit that have correlativity in its unit matrix with data matrix and check bit of being connected with storer are picked out, and again they are carried out XOR, obtain syndrome;
One error correction circuit is located the error bit of taking out data from storer according to syndrome, and its logical value of overturning, correct data after the acquisition error correction;
One scrambler, it links to each other with described storer and error correction circuit is connected, and takes out and passes through the data of error correction the data of input with from storer and carry out XOR, obtains the logical value of new data; Again according to correlative character in the described G matrix, the control by address information produces new check bit to logical value and former check bit XOR with data of correlativity, exports and gives storer;
One interface circuit, it links to each other with described storer and error correction circuit is connected, have a plurality of MUX, acquisition is data bit stored in storer, and determine that according to address information extraction the figure place data give error correction circuit by definite figure place, obtain the check bit of in memory device, taking out simultaneously and pass to error correction circuit; Also comprise a plurality of transmission gates and be transfused to data and replace, and deposit storer in according to one in the former definite figure place of address Information Selection;
Preferable, described demoder comprises: set and the XOR contrast circuit by the XOR that XOR gate is formed, the result who sets generation through XOR inputs to the XOR contrast circuit respectively with the check bit that is associated and carries out XOR, exports described syndrome from the XOR contrast circuit.
Preferable, it comprises a MUX, a plurality of splicing circuit described error correction circuit, and with the correction module of described splicing circuit equivalent, the output terminal of described MUX links to each other with a plurality of splicing circuit respectively, and described each splicing circuit links to each other with a correction module respectively;
Preferable, it comprises a plurality of XOR circuit and a plurality of selection control circuit described scrambler, wherein the output terminal of an XOR circuit selects control circuit to link to each other with each respectively, and described selection control circuit links to each other with one 1 XOR circuit respectively;
Preferable, the extraction circuit that extracts the error correction data position in the described interface circuit comprises a plurality of MUX, and the input end of each MUX obtains the data bit and the address bit signal of taking-up respectively, output be the data that extract;
Preferable, the circuit of putting back to of replacing the input data bit in the described interface circuit comprises a plurality of transmission circuits, each transmission circuit obtains the data bit of taking-up, the data bit and the address bit signal of input respectively, is output as the new data through replacing;
Preferable, described selection control circuit is two classes, and first kind of described selection control circuit of at least two groups is to be formed by connecting by an XOR circuit and a MUX, and described MUX selects circuit to link to each other with an address signal; Another kind of described selection control circuit is to be formed by connecting by an XOR circuit and an AND.
Description of drawings
Fig. 1 is that the present invention is from the bug check of memory read data and the flow chart of steps of error correction method;
Fig. 2 is the structural representation of the present invention with the H matrix of 4 input data instances;
Fig. 3 writes the flow chart of steps of the method for data to storer for the present invention;
Fig. 4 checks the structural representation of error correcting code circuitry for memory error of the present invention;
Fig. 5 checks decoding circuit structural representation in the error correcting code circuitry for memory error of the present invention;
Fig. 6 checks error correction circuit structural representation in the error correcting code circuitry for memory error of the present invention;
Fig. 7 checks coder structure synoptic diagram in the error correcting code circuitry for memory error of the present invention;
Fig. 8 A, Fig. 8 B are the structural representation of first kind of selection control circuit of the present invention;
Fig. 9 A to 9C is the structural representation of second kind of selection control circuit of the present invention;
Figure 10 is for extracting the illustrative view of functional configuration of error correction data position in the interface circuit of the present invention;
Figure 11 is for replacing the illustrative view of functional configuration of input data bit in the interface circuit of the present invention.
Embodiment
Below in conjunction with accompanying drawing, be described in more detail with other technical characterictic and advantage the present invention is above-mentioned.
Concrete disclosed method of the specific embodiment of the present invention and circuit structure, the stored data bit number of pairing verification is 4;
See also shown in Figure 1ly, it for the present invention from the bug check of memory read data and it step that comprises of flow chart of steps of error correction method is:
Step a1: decode procedure, the step that wherein said decode procedure comprises is:
Step a11: from storage unit, take out data bit and check bit, calculate syndrome according to the H matrix;
Step a12: the data bit of taking-up and check bit be according to G matrix correlation feature, by the control of address information, takes out 1 bit data that needs error correction from per four row, and these data and check bit and described syndrome are sent to error correction procedure together;
Step a2: error correction procedure, it step that comprises is:
Step a21: find out the data that extract in the data bit of from storer, reading and the error bit in the check bit according to syndrome, and correct the logical value of this error bit, obtain correct check bit sum data bit;
Step a22: output correct data position and check bit;
Wherein, described H matrix is that G matrix and unit matrix are formed, and sees also shown in Figure 2ly, and it is the structural representation of the present invention with the H matrix of 4 input data instances, and the characteristics of described H matrix are, and: d15～d0 is 16 bit data positions, and c4～c0 is 5 bit check positions.The G matrix is divided into two parts up and down, the first half characteristics: every four correlative characters that repeat row, phase ortho position correlative character is different; The latter half characteristics: per four phase ortho positions are one group, have identical correlative character, but correlative character difference between every group; Syndrome has a correlativity for each data bit and check bit in the H matrix data are carried out the value of XOR, and promptly formula is: Syndrome=d1^d2^......^d15^c0^c1^......^c4; Above-mentioned steps is taken out data bit and check bit common (16+5) position from storage unit like this, and the correct check bit sum data bit that error correction procedure obtains is respectively 5 and 4; The rule of " 1 " of expression correlativity has determined the area, time-delay, placement-and-routing of bottom circuit etc. in the G matrix, especially when storer inputoutput data position is more, big many of the optimization degree that the design of upper strata thought produces circuit than the design of bottom hardware.
See also shown in Figure 3ly, its present invention writes the flow chart of steps of the method for data to storer; In fact it also adds cataloged procedure except the process of the inspection error correction that comprised above-mentioned reading of data, and it complete step that comprises is:
Step b1: decode procedure, the step that wherein said decode procedure comprises is:
Step b11: from storage unit, take out data bit and check bit, calculate syndrome according to the H matrix, described H matrix is that G matrix and unit matrix are formed, the figure place of described data bit is corresponding with G matrix column number, the figure place of check bit is corresponding with the figure place of unit matrix, wherein the G matrix is divided into two parts up and down, and one of them part is every four correlative characters that repeat row, and phase ortho position correlative character is different; Per four the phase ortho positions of another part are one group, have identical correlative character, but correlative character difference between every group;
Step b12: the data bit and the check bit of taking-up are given interface circuit, by the control of address information, take out corresponding 1 bit data from every four figures certificate, and these data and check bit are sent to error correction procedure together;
Step b2: error correction procedure, it step that comprises is:
Step b21: find out the data that extract in the data bit of from storer, reading and the error bit in the check bit according to syndrome, and correct the value of this error bit, the check bit sum data bit after obtaining to proofread and correct;
Step b22: the check bit sum data bit behind the output calibration;
Step b3: cataloged procedure, comprising step be:
Step b31: carry out XOR with the data of input and the data bit behind the above-mentioned steps b22 output calibration, obtain the logical value of new data; Again according to correlative character in the G matrix, the control by address information produces new check bit to logical value and former check bit XOR with data of correlativity, exports and gives storer;
Step b32: according to address information, the former data corresponding positions that reads is replaced to the data of input from storer, produce new data and deposit in the storer;
For realizing above-mentioned two kinds of methods, creator of the present invention provides a kind of memory error inspection and error correcting code circuitry, see also shown in Figure 4ly, it comprises: a demoder 1, an error correction circuit 2, a scrambler 3, an interface circuit 4 and corresponding data transmission link; Wherein, described demoder 1 is connected with storer, and the data and the check bit that have correlativity in the unit matrix with data matrix and check bit are picked out, and again they are carried out XOR, obtain syndrome;
Described error correction circuit 2 is located the error bit of taking out data from storer according to syndrome, and its logical value of overturning, correct data after the acquisition error correction;
Described scrambler 3 links to each other with described storer and error correction circuit 2 is connected, and takes out and passes through the data of error correction the data of input with from storer and carry out XOR, obtains the logical value of new data; Again according to correlative character in the described G matrix, the control by address information produces new check bit to logical value and former check bit XOR with data of correlativity, exports and gives storer;
Described interface circuit 4 links to each other with described storer and error correction circuit 2 is connected, have four MUX, acquisition is data bit stored in storer, and, obtain the check bit of in memory device, taking out simultaneously and pass to error correction circuit 2 by determining that figure place determines that according to address information extraction the data of figure place give error correction circuit 2; Also comprise four transmission gates and be transfused to data and replace, and deposit storer in according to one in the former definite figure place of address Information Selection;
See also shown in Figure 5, it is a decoding circuit structural representation of the present invention, XOR tree 12 and XOR contrast circuit 11 that it is made up of XOR gate, the results that set 12 generations through XOR input to XOR contrast circuit 11 respectively with the check bit that is associated and carry out XOR, from the described syndrome of XOR contrast circuit 11 outputs; The process that realizes is that the unit matrix of data matrix and check bit is picked out data and check bit with correlativity, again they is carried out XOR, obtains syndrome.
See also shown in Figure 6, it is an error correction circuit structural representation of the present invention, it comprises a MUX 21, four splicing circuit 221,222,223,224, and with the correction module 231,232,233,234 of described splicing circuit equivalent, the output terminal of described MUX 21 links to each other with four splicing circuit 221,222,223,224 respectively, and described each splicing circuit links to each other with a correction module respectively; It is the design rule according to the G matrix, error correction circuit 2 can obtain simplifying and be divided into syndrome the first half circuit and the latter half circuit like this, thereby 4 data of taking out from storer are carried out error correction, and correction module 231,232,233,234 is according to its logical value of misdata bit flipping of syndrome location.
See also shown in Figure 7, it is the structural representation of coding circuit, it comprises six XOR circuit 31 and five selection control circuits 32, wherein the output terminal of an XOR circuit 310 selects control circuit 32 to link to each other with each respectively, and described selection control circuit 321,322,323,324,325 links to each other with one 1 XOR circuit 311,312,313,314,315 respectively; By appropriate design to coding circuit 3, the method of extracted data raising reliability can not have influence on the speed of integrated circuit, the access of its suitable multi-bit certificate, and the many more advantages that embody more of data bits---coding circuit simplification degree is obvious more, encoding rate improves greatly.Its course of work is as follows:
At first, 4 bit data of input and every good of 4 bit data of correction are carried out the logical value that XOR obtains 4 new bit data, the data bit that changes is logical value 1 certainly;
Secondly, these as a result which be used for and proofread and correct after check bit carry out XOR to obtain new check bit, depend on correlative character corresponding in the G matrix, and control by the address and to realize.The new data and the former check bit XOR that possess correlativity obtain adapting to the new 5 bit check positions of importing 4 bit data, principle is: the data bit that changes has become logical value 1 through first step, if it is relevant in this row, then enter the XOR with former check bit, thereby determine the logical value of new check bit.In conjunction with Fig. 2, select control circuit according to the corresponding data that extracted in G matrix first row, by the control of address information the data with correlativity are taken out; Addr[1:0 for example]=11, then address selection control circuit 0 is first taking-up that " 1 " is arranged in the corresponding G matrix in four groups, flow to XOR gate and proofread and correct after C0 carry out XOR, obtain new C0.
Consult Fig. 8 A to Fig. 9 C, it is respectively in the scrambler two kinds of different structure circuit diagrams in five selection control circuits, and they all are that correlativity according to the G matrix of Fig. 2 designs, and finish the XOR of the correlation data of corresponding C0 to C5.Wherein Fig. 8 A and Fig. 8 B are respectively first kind of described selection control circuit, and it is to be formed by connecting by an XOR circuit and a MUX, and described MUX selects circuit to link to each other with an address signal; First type selection control circuit 321 of Fig. 8 A correspondence, it finishes the XOR of the correlation data of corresponding C0 through XOR circuit 3211; Addr[1] position of expression data is if first or second, and is relevant between the data; Then the XOR result of data sends by MUX 3212; Corresponding another first type the selection control circuit 322 of Fig. 8 B, it finishes the XOR of the correlation data of corresponding C1 by XOR circuit 3221; Addr[0] position of expression data is if first or the 3rd, and is relevant between the data; Then the XOR result of data sends by MUX 3222.
See also shown in Fig. 9 A to Fig. 9 C, it is the structural representation of second kind of described selection control circuit, and it is to be formed by connecting by an XOR circuit and an AND; The selection control circuit 323 of Fig. 9 A correspondence is finished the XOR of the correlation data of corresponding C2, data dependence according to the correspondence of C2 shown in Figure 2 is fixed, do not need address selection, with AND 3231 incoherent data mask is fallen, all the other related datas are carried out XOR by XOR circuit 3232, and the result directly sends; The selection control circuit 324 of Fig. 9 B correspondence is finished the XOR of the correlation data of corresponding C3, data dependence according to the correspondence of C3 shown in Figure 2 is fixed, do not need address selection, with AND 3241 incoherent data mask is fallen, all the other related datas are carried out XOR by XOR circuit 3242, and the result directly sends; The selection control circuit 325 of Fig. 9 C correspondence is finished the XOR of the correlation data of corresponding C4, data dependence according to the correspondence of C4 shown in Figure 2 is fixed, do not need address selection, with AND 3251 incoherent data mask is fallen, same all the other related datas are carried out XOR by XOR circuit 3252, and the result directly sends.
The present invention adopts the design of extracted data position mainly in order to improve encoding rate and improve coding circuit speed when to improve the error correction probability, because ECC can only entangle 1 bit-errors, in order to prevent that the device extent of damage from causing several adjacent situations about all making a mistake greatly, original data are carried out error correction in the present invention adopts this " extraction " storer, the probability that the data of following two extractions of then above-mentioned situation make a mistake simultaneously is very little, so correct the reliability that 1 bit-errors just can greatly improve the storage data.See also shown in Figure 10, it is for extracting the illustrative view of functional configuration of error correction data position in the interface circuit of the present invention, it comprises four 4 and selects 1 MUX 41, the input end of each MUX 411,412,413,414 obtains the data bit and the address bit signal of taking-up respectively, output be the data that extract; It is finished from per four data according to corresponding 1 bit data of address Information Selection to be directed to present embodiment, and as the correction data that is replaced data/output, the data of this 4 bit extraction and 5 bit check positions will be delivered to error correction circuit 2 and proofread and correct.
See also shown in Figure 11, it is for replacing the illustrative view of functional configuration of input data bit in the interface circuit of the present invention, it comprises four transmission circuits 42, each transmission circuit 421,422,423,424 obtains the data bit of taking-up, the data bit and the address bit signal of input respectively, is output as the new data through replacing; It replaces to the input data bit according to 1 in the former four figures certificate of address Information Selection to be directed to present embodiment; All the other positions still keep former data, and this has just finished data " insertion ", and output data is as in the 16 new bit data write stories.
In sum, of the present invention three big characteristics:
1 pair of multidata coding can improve code check, reduces the ratio that the ECC technology increases chip area, reduces cost;
The problem that 2 increase code checks bring is exactly caused coding and error correction circuit huge, and for head it off, the present invention has simplified coding circuit in another innovation place exactly, does not promptly carry out the coding of total data, only utilizes insertion data and check bit to finish;
3 have simplified error correction circuit, each read-write operation process to storage unit, only needing that those data of being chosen in the multidata are carried out error correction gets final product, because coding circuit is used check bit, we also need the multidata corresponding check bit is carried out error correction, to guarantee that the check bit of using in the coding circuit is correct data.
The above only is preferred embodiment of the present invention, only is illustrative for the purpose of the present invention, and nonrestrictive.Those skilled in the art is understood, and can carry out many changes to it in the spirit and scope that claim of the present invention limited, revise, even equivalence, but all will fall within the scope of protection of the present invention.
Claims (9)
1, a kind of bug check and error correction method from the memory read data is characterized in that, it step that comprises is:
Step a1: decode procedure, the step that wherein said decode procedure comprises is:
Step a11: from storage unit, take out data bit and check bit, calculate syndrome according to the H matrix, described H matrix is that G matrix and unit matrix are formed, the figure place of described data bit is corresponding with G matrix column number, the figure place of check bit is corresponding with the columns of unit matrix, wherein the G matrix is divided into two parts up and down, and one of them part is every four correlative characters that repeat row, and phase ortho position correlative character is different; Per four the phase ortho positions of another part are one group, have identical correlative character, but correlative character difference between every group, and syndrome has a correlativity for each data bit and check bit in the H matrix data are carried out the value of XOR;
Step a12: the data bit of taking-up and check bit be according to G matrix correlation feature, by the control of address information, takes out 1 bit data that needs error correction from per four row, and these data and check bit and described syndrome are entered into error correction procedure together;
Step a2: error correction procedure, it step that comprises is:
Step a21: find out the data that from data bit, extract of from storer, reading and the error bit in the check bit according to syndrome, and the logical value of this error bit of error correction, obtain correct check bit sum data bit;
Step a22: output correct data position and check bit.
2, a kind ofly write the method for data to storer, it has utilized above-mentioned bug check and error correction method from the memory read data to realize, it is characterized in that it step that comprises is:
Step b1: decode procedure, the step that wherein said decode procedure comprises is:
Step b11: from storage unit, take out data bit and check bit, calculate syndrome according to the H matrix, described H matrix is that G matrix and unit matrix are formed, the figure place of described data bit is corresponding with G matrix column number, the figure place of check bit is corresponding with the figure place of unit matrix, wherein the G matrix is divided into two parts up and down, and one of them part is every four correlative characters that repeat row, and phase ortho position correlative character is different; Per four the phase ortho positions of another part are one group, have identical correlative character, but correlative character difference between every group;
Step b12: the data bit and the check bit of taking-up are given interface circuit, by the control of address information, take out corresponding 1 bit data from every four figures certificate, and these data and check bit are entered into error correction procedure together;
Step b2: error correction procedure, it step that comprises is:
Step b21: find out the data that extract in the data bit of from storer, reading and the error bit in the check bit according to syndrome, and the value of this error bit of error correction, the check bit sum data bit after obtaining to proofread and correct;
Step b22: the check bit sum data bit behind the output calibration;
Step b3: cataloged procedure, the step that wherein said decode procedure comprises is:
Step b31: carry out XOR with the data of input and the data bit behind the above-mentioned steps b22 output calibration, obtain the logical value of new data; Again according to correlative character in the G matrix, the control by address information produces new check bit to logical value and former check bit XOR with data of correlativity, exports and gives storer;
Step b32: according to address information, the former data bit corresponding positions that reads is replaced to the data bit of input from storer, produce new data and deposit in the storer.
3, a kind of memory error inspection and error correcting code circuitry is characterized in that it comprises:
One demoder, the data and the check bit that have correlativity in its unit matrix with data matrix and check bit of being connected with storer are picked out, and again they are carried out XOR, obtain syndrome;
One error correction circuit is located the error bit of taking out data from storer according to syndrome, and its logical value of overturning, correct data after the acquisition error correction;
One scrambler, it links to each other with described storer and error correction circuit is connected, and takes out and passes through the data of error correction the data of input with from storer and carry out XOR, obtains the logical value of new data; Again according to correlative character in the described G matrix, the control by address information produces new check bit to logical value and former check bit XOR with data of correlativity, exports and gives storer;
One interface circuit, it links to each other with described storer and error correction circuit is connected, have a plurality of MUX, acquisition is data bit stored in storer, and determine that according to address information extraction the figure place data give error correction circuit by definite figure place, obtain the check bit of in memory device, taking out simultaneously and pass to error correction circuit; Also comprise a plurality of transmission gates and be transfused to data and replace, and deposit storer in according to one in the former definite figure place of address Information Selection.
4, memory error inspection according to claim 3 and error correcting code circuitry, it is characterized in that, described demoder comprises: set and the XOR contrast circuit by the XOR that XOR gate is formed, the result who sets generation through XOR inputs to the XOR contrast circuit respectively with the check bit that is associated and carries out XOR, exports described syndrome from the XOR contrast circuit.
5, memory error inspection according to claim 3 and error correcting code circuitry, it is characterized in that, it comprises a MUX, a plurality of splicing circuit described error correction circuit, and with the correction module of described splicing circuit equivalent, the output terminal of described MUX links to each other with a plurality of splicing circuit respectively, and described each splicing circuit links to each other with a correction module respectively.
6, memory error inspection according to claim 3 and error correcting code circuitry, it is characterized in that, it comprises a plurality of XOR circuit and a plurality of selection control circuit described scrambler, wherein the output terminal of an XOR circuit selects control circuit to link to each other with each respectively, and described selection control circuit links to each other with one 1 XOR circuit respectively.
7, memory error inspection according to claim 3 and error correcting code circuitry, it is characterized in that, the extraction circuit that extracts the error correction data position in the described interface circuit comprises a plurality of MUX, the input end of each MUX obtains the data bit and the address bit signal of taking-up respectively, output be the data that extract.
8, memory error inspection according to claim 3 and error correcting code circuitry, it is characterized in that, the circuit of putting back to of replacing the input data bit in the described interface circuit comprises a plurality of transmission circuits, each transmission circuit obtains the data bit of taking-up, the data bit and the address bit signal of input respectively, is output as the new data through replacing.
9, memory error inspection according to claim 6 and error correcting code circuitry, it is characterized in that, described selection control circuit is two classes, first kind of described selection control circuit of at least two groups is to be formed by connecting by an XOR circuit and a MUX, and described MUX selects circuit to link to each other with an address signal; Another kind of described selection control circuit is to be formed by connecting by an XOR circuit and an AND.
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| CN2007100986025A CN101067972B (en) | 2007-04-23 | 2007-04-23 | Memory error-detecting and error-correcting coding circuit and method for reading and writing data utilizing the same |
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| CN2007100986025A Active CN101067972B (en) | 2007-04-23 | 2007-04-23 | Memory error-detecting and error-correcting coding circuit and method for reading and writing data utilizing the same |
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Address after: 100084 Room 301, building B, research building, Tsinghua Science and Technology Park, Beijing Applicant after: GIGADEVICE SEMICONDUCTOR Inc. Address before: 100084 Room 301, building B, research building, Tsinghua Science and Technology Park, Beijing Applicant before: GigaDevice Semiconductor Inc. |
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| COR | Change of bibliographic data |
Free format text: CORRECT: APPLICANT; FROM: BEIJING XINJI JIAYI, MICROELECTRONIC SCIENCE + TECH. CO., LTD. TO: GIGADEVICE SEMICONDUCTOR INC. |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: BEIJING GIGADEVICE SEMICONDUCTOR CO., LTD. Free format text: FORMER NAME: BEIJING GIGADEVICE SEMICONDUCTOR INC. |
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| CP03 | Change of name, title or address |
Address after: 100084 Beijing City, Haidian District Xueyuan Road No. 30, large industrial building A block 12 layer Patentee after: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. Address before: 100084 Room 301, building B, research building, Tsinghua Science and Technology Park, Beijing Patentee before: GigaDevice Semiconductor Inc. |
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| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 12 / F, block a, Tiangong building, No.30 Xueyuan Road, Haidian District, Beijing 100084 Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |