CN103456355A - EEPROM interface circuit - Google Patents

Abstract

The invention discloses an EEPROM interface circuit including an even parity generation circuit and a selecting replacement circuit. When data is stored, an EEPROM is automatically allowed to additionally store one bit; and when reading, the additionally stored bit is used for replacing an error bit, so that work can be continued when a chip generates a bit of wrong in the EEPROM.

Description

The EEPROM interface circuit

Technical field

The present invention relates to a kind of improved EEPROM interface circuit.

Background technology

The EEPROM of simulation often owing to producing the reason of technique cause cisco unity malfunction, what type of error was maximum is that in same EEPROM, the data on a certain bit line are all wrong.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of EEPROM interface circuit, when a bit-errors appears in EEPROM, chip can also be worked on.

For solving the problems of the technologies described above, EEPROM interface circuit of the present invention comprises:

One even parity check produces circuit, and its input is designated as a, and output is designated as b; Input a is the data that need to write EEPROM, is data bus signal, is designated as a[0] to a[N-1], wherein N is positive integer, is data-bus width; Output b is a data signal, b=a[0]+a[1]+... + a[N-1], wherein add as binary add; Output b inputs the EEPROM storage together with input a; This EEPROM has N+1 position storage space to each address; B, a[N-1] to a[0] successively in storage space from a high position to the lower memory; For generation of a backup, export b; As a[0] to a[N-1] in any one occur can going to replace error bit with output b when wrong, obtain correct a[0] to a[N-1];

One selects replacement circuit, and an one input is the output b and the combination of inputting a be stored in EEPROM, is designated as c; Another input is to select signal e; By the e position in the combination of output b and input a, with output, b replaces, and then the sense data using the low N position of result as EEPROM is exported, and output is designated as d; While finding the e position appearance mistake of EEPROM after test, with output, b replaces this error bit.

The present invention, by improving the EEPROM interface circuit, when the storage data, allows EEPROM deposit one automatically, the position that a replacement of depositing with this when reading makes mistakes more, thus make chip when a bit-errors appears in EEPROM, can also work on.Detect the EEPROM error bit, can carry out in automatic manufacturing test (ATE test).

The accompanying drawing explanation

Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:

Accompanying drawing is improved EEPROM interface circuit schematic diagram.

Embodiment

Shown in accompanying drawing, described EEPROM interface circuit comprises:

One even parity check produces circuit, and its input is the data that system need to write EEPROM, is designated as a.A is data bus signal, is designated as a[0] to a[N-1]; Wherein N is positive integer, is data-bus width.Its output is the even parity check result, is designated as b, and b is a data signal, b=a[0]+a[1]+... + a[N-1].Adding wherein is binary add, and binary add is exactly xor operation.Output b delivers in EEPROM and stores together with input a.Described EEPROM has N+1 position storage space to each address.B, a[N-1] to a[0] successively in storage space from a high position to the lower memory.The effect that described even parity check produces circuit is to produce a backup, exports exactly b.Produce output b by the even parity check mode and just can make other a[0] to a[N-1] in any one mistake appears, can go to replace error bit with the b position, obtain correct a[0] arrive a[N-1].

One selects replacement circuit, and an one input is the output b and the combination of inputting a be stored in EEPROM, is designated as c.C is data bus signal, b, a[N-1] to a[0] the big-endian arrangement successively in c of these positions.Another input is to select signal e.The operation that described selection replacement circuit is carried out is the e position in the combination of output b and input a, with this position replacement of output b; Then the output of the sense data using the low N position of result as EEPROM, output is designated as d; D be this interface circuit to the system other parts data bus as the EEPROM sense data.The effect of described selection replacement circuit is exactly that mistake appears in the e position of finding EEPROM after test, just can select replacement circuit by this, with this position of output b, replaces this error bit.

The work of described EEPROM interface circuit divides two stages, first stage is automatic manufacturing test (ATE test) stage, at this moment selects signal e to be made as N, exports b and replaces with b with the N position of the combination c of input a, because the N position itself is exactly b, so select the output d of replacement circuit, be exactly a.Whether system is identical with the value write by the value of relatively reading, and judges whether the EEPROM storage is correct.If find that the situation that all readouts and the value of writing are not inconsistent is all to make mistakes in the k position, just establish e in subordinate phase (normal work stage) so and equal k, this sample interface circuit just can replace the k position with b, thereby makes system can read correct event memory.

Abovely by embodiment, the present invention is had been described in detail, but these not are construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims (1)

1. an EEPROM interface circuit, is characterized in that, comprising:

One even parity check produces circuit, and its input is designated as a, and output is designated as b; Input a is the data that need to write EEPROM, is data bus signal, is designated as a[0] to a[N-1], wherein N is positive integer, is data-bus width; Output b is a data signal, b=a[0]+a[1]+... + a[N-1], wherein add as binary add; Output b inputs the EEPROM storage together with input a; This EEPROM has N+1 position storage space to each address; B, a[N-1] to a[0] successively in storage space from a high position to the lower memory; For generation of a backup, export b; As a[0] to a[N-1] in any one occur can going to replace error bit with output b when wrong, obtain correct a[0] to a[N-1];

One selects replacement circuit, and an one input is the output b and the combination of inputting a be stored in EEPROM, is designated as c; Another input is to select signal e; By the e position in the combination of output b and input a, with output, b replaces, and then the sense data using the low N position of result as EEPROM is exported, and output is designated as d; While finding the e position appearance mistake of EEPROM after test, with output, b replaces this error bit.

Images