CN108242973A - A data error correction method and device - Google Patents

Abstract

An embodiment of the present invention provides a kind of data error-correcting method and devices, and applied to the device for including sending module and receiving module, method includes：For the sending module of the device, netted logic coding is carried out for N data to be transmitted, obtains coded data；The coded data is sent to the receiving module of the device；For the receiving module of the device, the coded data received is split according to the rule of combination, obtains each data of the N data and described every group at least corresponding check bit data of two bits；According to the N data and every group of at least corresponding check bit data of two bits, using logical operation, determine that the data of mistake occur in the coded data；When the data that mistake occurs include at least a data in transmitted N positions data, error correction is carried out at least a data in the N data.Using the embodiment of the present invention, the reliability of device is improved.

Description

A data error correction method and device

technical field

The invention relates to the field of communication technology, in particular to a data error correction method and device.

Background technique

In the development process of the entire aerospace and nuclear power fields, based on SRAM (Static Random Access Memory, Static Random Access Memory) FPGA (Field Programmable Gate Array, Field Programmable Gate Array) has high functional integration, rich resources, and flexible design. advantages, but there are also certain risks. For example, in the field of aerospace, in the harsh radiation environment of outer space, it is susceptible to the influence of high-level charged particles, and will be subjected to radiation from various complex environments in space, resulting in the occurrence of phenomena such as single-particle flipping and multi-particle flipping, thus The functional error of the communication data will cause the FPGA device to occur, so it is necessary to carry out corresponding communication data reinforcement for the above phenomenon. Among them, the single event flipping mainly refers to the 0/1 flipping of one bit in the communication data, and the multi-event flipping mainly refers to the 0/1 flipping of two or more bits in the communication data. The probability of bit and above data flip errors is very low.

At present, in the FPGA of aerospace or nuclear power plants, the redundancy technologies commonly used for data reinforcement are TMR (Triple Modular Redundancy, triple-mode redundancy), partial TMR, duplication and comparison (DWC, Duplication With Compare), and reduced redundancy precision (RPR, reduced precision redundancy) and so on. Among them, TMR technology directly copies the input original data into two copies, combines the two copied data with the original data to obtain encoded data, and selects three copies of the encoded data through a majority voter at the output port, such as the original data is 000, the encoded data is 000000000, a single bit flip occurs during transmission, the encoded data becomes 000000100, and the output port passes through the majority voter, and 000 in the encoded data will be output as the decoded data. However, when a multi-bit error occurs during transmission, for example, the coded data error becomes 010010000, and the wrong decoded data 010 will be output at the output port. It can be seen that TMR cannot solve double-bit and above data flip errors. It can only perform data reinforcement for single-event flip errors on the FPGA, but cannot deal with multi-bit flip errors, resulting in low reliability of FPGA devices.

Contents of the invention

The purpose of the embodiments of the present invention is to provide a data error correction method and device, so as to achieve the purpose of improving device reliability.

In order to achieve the above purpose, an embodiment of the present invention provides a data error correction method, which is applied to a device including a sending module and a receiving module. The method includes:

For the transmit block of the device in question, do the following:

Perform network logic coding on the N-bit data to be transmitted to obtain coded data;

Wherein, the step of performing network logic coding includes: for the M-bit data in the N-bit data to be transmitted, performing logical operations on each group of at least two bits of data in the M-bit data to obtain Set check digit data corresponding to at least two bits of data; according to a preset combination rule, combine the N-bit data and the check digit data to obtain encoded data, wherein M is less than or equal to N, and N is not less than 4, The logical operation is exclusive OR operation, exclusive OR operation, AND operation, OR operation, NOT operation, AND NOT operation, OR NOT operation, or AND OR NOT operation;

sending the coded data to a receiving module of the device;

For the receiver block of the device in question, do the following:

Splitting the received coded data according to the combination rule to obtain parity data corresponding to each bit of the N-bit data and each group of at least two bits of data;

According to the N-bit data and the parity bit data corresponding to each group of at least two bits of data, using logical operations, determine the data in which errors occur in the encoded data;

When the erroneous data includes at least one bit of the transmitted N-bit data, error correction is performed on at least one bit of the N-bit data.

Preferably, according to the N-bit data and the parity bit data corresponding to each group of at least two-bit data, using logic operations to determine the erroneous data in the encoded data includes:

Carry out logical operations on each group of at least two bits of data in the N-bit data and corresponding check digit data to obtain an operation result; according to the number K of logic operations whose operation result is a specified value, and the operation result is a specified The number of common data bits contained in the K logical operations of the value determines the data in which errors occur in the encoded data, wherein the common data bits are contained in at least two logical operations in the K logical operations For the same data bits, K is less than or equal to the number of logic operations corresponding to all operation results.

Preferably, the error correction of at least one bit of the N-bit data includes:

When the determined erroneous data includes 1 erroneous data of the N bits of data, inverting the determined 1 bit of data.

Preferably, the error correction of at least one bit of the N-bit data includes:

When the determined erroneous data includes at least two erroneous data of the N-bit data, respectively inverting at least two bits of the determined N-bit data.

Preferably, the device including the sending module and the receiving module is: a field programmable logic gate array device or a device including FIFO, DDR, DRAM or ram-based.

In order to achieve the above purpose, an embodiment of the present invention provides a data error correction device, which includes:

The network logic coding unit is used for the sending module of the device, and performs network logic coding on the N-bit data to be transmitted to obtain encoded data; wherein, the process of performing network logic coding includes: for the N-bit data to be transmitted For the M-bit data in the bit data, logical operations are respectively performed on each group of at least two bits of data in the M-bit data to obtain check digit data corresponding to each group of at least two bits of data; according to the preset combination rules, the The N-bit data is combined with the parity bit data to obtain coded data, wherein, M is less than or equal to N, and N is not less than 4, and the logic operation is an exclusive OR operation, an exclusive OR operation, an AND operation, or an OR operation, NOT operation, AND NOT operation, OR NOT operation, or AND OR NOT operation;

a sending unit, configured to send the encoded data to a receiving module of the device;

The splitting unit is used for the receiving module of the device, splits the received encoded data according to the combination rule, and obtains each bit of the N-bit data corresponding to each group of at least two bits of data parity data;

An arithmetic unit, configured to determine the data in which errors occur in the coded data by logical operation according to the N-bit data and the check digit data corresponding to each group of at least two-bit data;

The error correction unit is configured to correct at least one bit of the N-bit data when the erroneous data includes at least one bit of the transmitted N-bit data.

Preferably, the computing unit specifically includes:

A logic operation subunit is used to perform logic operations on each set of at least two bits of data in the N-bit data and corresponding check digit data to obtain an operation result;

The error bit search subunit is used to determine that an error occurs in the encoded data according to the number K of logical operations whose operation result is a specified value, and the number of common data bits included in the K logical operations whose operation result is a specified value data, wherein the common data bit is the same data bit included in at least two logical operations among the K logical operations, and K is less than or equal to the number of logical operations corresponding to all the operation results.

Preferably, the error correction unit specifically includes:

The first inversion subunit is used to invert the determined one-bit data when the determined error data contains one-bit data in the N-bit data.

Preferably, the error correction unit further specifically includes:

The second inversion subunit is configured to respectively invert at least two bits of the determined N-bit data when the determined erroneous data includes at least two bits of the N-bit data.

Preferably, the device is: a field programmable logic gate array device or a device including FIFO, DDR, DRAM or ram-based.

The data error correction method and device provided by the embodiments of the present invention can use network logic coding to encode the N-bit data to be transmitted to obtain encoded data, and the receiving module can use the check bit data and the N bit in the transmitted encoded data N-bit data, error detection and error correction are performed on N-bit data using logic operations. Not only for single-event flipping, but also for multi-event flipping, the purpose of error detection and error correction can be realized, so as to better strengthen the communication data in the device and improve the stability and reliability of the device. Furthermore, the embodiments of the present invention can also be applied to devices including FIFO, DDR, DRAM or ram-based, to perform data error detection and error correction inside the device. Of course, implementing any product or method of the present invention does not necessarily need to achieve all the above-mentioned advantages at the same time.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic flow chart of a data error correction method provided by an embodiment of the present invention;

Fig. 2 is a schematic diagram of the relationship between the 5-bit data to be transmitted and the check digit data provided by the embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a data error correction device provided by an embodiment of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

A data error correction method provided by an embodiment of the present invention will firstly be described in detail below.

It should be noted that the embodiment of the present invention is preferably applicable to a device including a sending module and a receiving module. Concrete, in practical application, this device can be: field programmable logic gate array device or comprise FIFO (First Input First Output, first in first out), DDR (Double Data Rate, double rate synchronous dynamic random access memory), DRAM ( Dynamic Random Access Memory, dynamic random access memory) or ram-based devices, such as FPGA devices in aerospace systems or nuclear power plants, etc.

Referring to FIG. 1, FIG. 1 is a schematic flowchart of a data error correction method provided by an embodiment of the present invention, which may include the following steps:

For the transmit block of the device in question, do the following:

S101, performing network logic coding on the N-bit data to be transmitted to obtain coded data;

Specifically, the step of performing network logic coding includes: for the M-bit data in the N-bit data to be transmitted, respectively performing logical operations on each group of at least two bits of data in the M-bit data to obtain Check bit data corresponding to at least two bits of data in each group; according to a preset combination rule, combine the N-bit data and the check bit data to obtain encoded data, wherein M is less than or equal to N, and N is not less than 4 , the logical operation is exclusive OR operation, exclusive OR operation, AND operation, OR operation, NOT operation, AND NOT operation, OR NOT operation, or AND OR NOT operation;

Exemplarily, a data error correction method provided by an embodiment of the present invention will be described in detail below by taking the logic operation as an exclusive OR operation as an example.

Exemplarily, the preset combination rule may be: the original data bit is in the low position, and the parity bit is in the high position. When N is equal to 5 and M is equal to 5, for the 5-bit original data b ₁ , b ₂ , b ₃ , b ₄ , and b ₅ to be transmitted, perform an exclusive OR operation on each group of 2-bit data in the original data, The XOR operation process can be shown in Table 1.

Table 1

It can be seen from Table 1 that after XOR operation, the check digits eq ₁₂ , eq _{13 ,} eq ₁₄ , eq 15 , eq ₂₃ , eq ₂₄ , eq ₂₅ , eq ₃₄ , eq corresponding to each group of 2-bit data can be obtained ₃₅ and eq ₄₅ , wherein, the relationship between the 5-bit original data and the resulting check digit is shown in Figure 2; according to the preset combination rule that the original data bit is in the low bit and the check bit is in the high bit, the 5-bit The original data is combined with the check digit to obtain encoded data eq ₁₂ eq ₁₃ eq ₁₄ eq ₁₅ eq ₂₃ eq ₂₄ eq ₂₅ eq ₃₄ eq ₃₅ eq ₄₅ b ₁ b ₂ b ₃ b ₄ b ₅ (such as 000000000011111).

Exemplarily, in practical applications, when M is less than 5, network logic coding can also be performed for some data bits of 5-bit original data (such as 4-bit data bits b ₁ , b ₂ , b ₃ , b ₄ ). , so that the design complexity of net logic coding can be reduced. Among them, in the encoding process, not only the XOR operation can be performed between two data bits, but also the XOR operation can be performed between 3 bits, 4 bits or 5 bits, such as the XOR operation between b ₁ , b ₂ , and b ₃ check digit Exclusive OR operation between b ₁ , b ₂ , b ₃ , and b ₄ to get the parity bit Exclusive OR operation between b ₁ , b ₂ , b ₃ , b ₄ , and b ₅ to get the check digit Thus, more check digit data are obtained.

S102. Send the encoded data to a receiving module of the device;

For sending encoded data to the receiving module, one possible situation is to perform real data transmission, and another possible situation is to simulate a data transmission environment and actually perform data transmission.

In the data transmission of aerospace systems, FIFO, DDR, DRAM or other storage devices are generally selected to store encoded data, and then the stored encoded data is sent to the receiving module of the device. In this embodiment, the transmission environment of data is simulated, and data transmission is actually carried out. FIFO can be selected as a storage device, one end of which is connected to the encoded data output of the sending module, and the other end is connected to the data input of the receiving module.

For the receiver block of the device in question, do the following:

S103, split the received coded data according to the combination rule, and obtain check digit data corresponding to each bit of the N-bit data and each group of at least two bits of data;

Specifically, in practical applications, the bit width at both ends can be assumed to be the same during data transmission (that is, bit width = data bit width + parity bit width), and the receiving module parses it according to the bit width agreed with the sending module in advance. Yes, for example, for 5 original data bits 11111 and 10 check digits 0000000000, according to the aforementioned combination rule that the original data bits are in the low bits and the check bits are in the high bits, for the combination to obtain the coded data 000000000011111, a bit width of 15 bits can be used The data bus for transmission, the receiving module only needs to use the lower 5 bits 11111 of the received encoded data as data bits, and the upper 10 bits 0000000000 as check bits. Among them, when the number of bits of encoded data is large, the number of bits of data to be transmitted each time can be agreed before the sending module and the receiving module transmit the data, and the sending module sends the encoded data in batches according to a fixed frame length, and the receiving module Just do the merge. For example, if the number of encoded data is 50 bits, you can set the fixed frame length to 10 bits, send 5 times, and the receiving module will perform a merge operation when receiving 5 times, and then obtain the data bits and corresponding data from the merged complete encoded data. check digit data.

S104, according to the N-bit data and the parity bit data corresponding to each group of at least two bits of data, using logic operations to determine the data in which errors occur in the encoded data;

Specifically, logical operations can be performed on each group of at least two bits of data in the N-bit data and the corresponding check digit data to obtain an operation result; the number K of logical operations is a specified value according to the operation result, and The operation result is the number of common data bits contained in the K logical operations of the specified value, and the data in which the error occurs in the encoded data is determined, wherein the common data bits are at least two of the K logical operations. For the same data bits included in the operation, K is less than or equal to the number of logic operations corresponding to all operation results. Wherein, the logical operation may also be referred to as an error detection check formula. When the logical operation is an XOR operation, the specified value can be 1, indicating that an error occurs in the XOR operation due to data errors at this time.

Exemplarily, the number of required XOR operations may be determined according to the actual number of data bits in which errors occur in the application scenario of the embodiment of the present invention.

Still referring to the embodiment shown in Figure 2, combined with the XOR operation in Table 1, for each group of 2-bit data b ₁ b ₂ , b ₁ b ₃ , b ₁ b ₄ , b ₁ b ₅ , b ₂ of 5-bit original data b ₃ , b ₂ b ₄ , b ₂ b ₅ , b ₃ b ₄ , b ₃ b ₅ , b 4 b ₅ and their corresponding check digits eq ₁₂ , eq _{13 , eq 14 ,} eq ₁₅ , eq ₂₃ , _{eq 24} , eq ₂₅ , eq ₃₄ , eq ₃₅ , eq ₄₅ , perform XOR operation, the following operation result will be obtained:

The basis for error detection in the embodiment shown in FIG. 2 is that the operation results of the 10 error detection check formulas are all 0 when no error occurs, that is, the operation result is 1 only when a data error occurs. In aerospace systems, when data errors occur in devices, 99.9999% of the errors are 1-bit data errors or 2-bit data errors. In this case, only 1-bit or 2-bit data errors can be considered for network logic coding. The number of subsequent error detection checksums required.

Assume that for each group of 2-bit data b ₁ b ₂ , b ₁ b ₃ , b ₁ b 4 , b 1 b ₅ , b ₂ b ₃ , b ₂ b ₄ , b _{2 b 5 ,} b ₃ b for 5-bit original data ₄ , b ₃ b ₅ , b ₄ b ₅ and _their corresponding parity bits eq ₁₂ , eq ₁₃ , eq ₁₄ , eq ₁₅ , eq _{23 , eq 24} , eq ₂₅ , eq ₃₄ , eq ₃₅ , eq ₄₅ are XORed The operation results are as follows:

According to the above error checking basis, the 6 XOR operations whose operation result is 1 represent 6 error detection check formulas with errors, and the 6 error check check formulas include 3 common data bits b ₁ and 3 b ₂ , 2 b ₃ , 2 b ₄ , and 2 b ₅ , since b ₁ and b ₂ appear most frequently, it is determined that the data bits where errors occur are b ₁ and b ₂ .

In the above-mentioned embodiment, the error of 3 or more bits of data is not considered, and the number of error detection check formulas can be increased to meet the error detection and error correction requirements of specific application scenarios when it needs to be considered. In practical applications, when it is necessary to consider 3-bit and more bit flips, it is possible to perform 3-bit original data, 4-bit Exclusive OR operation between original data or 5-bit original data to get more check digits. For example, for the above-mentioned 5-bit original data, after obtaining 10 check digits of each group of 2 data, continue to check between 3-bit data Perform XOR operation to get eq ₁₂₃ , eq ₁₂₄ , eq ₁₂₅ , eq ₁₃₄ , eq ₁₃₅ , eq ₁₄₅ , eq ₂₃₄ , eq ₂₃₅ , eq ₂₄₅ , eq ₃₄₅ , perform XOR operation between 5-bit data to get eq ₁₂₃₄₅ , and then in In the process of determining the erroneous data that has been reversed, the number of error detection check formulas that can be obtained is 10+10+1=21, and the number K of the operation results of these error check check formulas is 1, and K error check formulas The number of public data bits contained in the check formula is used to determine which original data bits or check bits have errors. Wherein, when the operation result is the specified value 1, it means that the error check check formula has an error, and this When K is not greater than 21.

S105. Perform error correction on at least one bit of the N-bit data.

Specifically, when the erroneous data includes at least one bit of the transmitted N-bit data, error correction is performed on at least one bit of the N-bit data. In practical applications, when the error data is the check bit data, since the error of the check bit data will not affect the transmitted original N-bit data, there is no need to correct the error of the check bit data.

Specifically, when the determined erroneous data includes 1 bit of erroneous data in the N bits of data, the determined 1 bit of data is reversed.

Specifically, when the determined erroneous data includes at least two bits of erroneous data in the N-bit data, at least two bits of the determined N-bit data are respectively inverted.

Exemplarily, for each group of 2-bit data b ₁ b ₂ , b ₁ b ₃ , b ₁ b ₄ , b ₁ b ₅ , b ₂ b ₃ , b ₂ b ₄ , b ₂ b ₅ , b ₃ b ₄ , b ₃ b ₅ , b ₄ b ₅ and their _{corresponding} check digits eq ₁₂ , eq ₁₃ , eq ₁₄ , eq 15 , eq ₂₃ , eq ₂₄ , eq ₂₅ , eq ₃₄ , eq ₃₅ , eq ₄₅ , perform XOR operation to obtain the operation result, among them, Among a ₁ , a ₂ , a ₃ , a ₄ , a ₅ , a ₆ , a ₇ , a ₈ , a ₉ , and a ₁₀ , when one of the operation results is 1, a 1-digit check can be located Bit data error, if only a ₁ is 1, it means that eq ₁₂ has an error, and no error correction is required at this time; when 4 of the operation results are 1, one bit of the original data error can be located, such as a ₁ and a ₂ , a ₃ , a ₄ are 1, and the others are 0, indicating that the same data bit b ₁ included in the 4 error detection and error checking formulas has an error, and the error correction of b ₁ is reversed; when two of the operation results are 1 , you can locate the 2-bit check digit data error, such as a ₁ and a ₂ are 1, and the others are 0, indicating that there is no error in the original data bit, so there is an error in the check digit eq ₁₂ and eq ₁₃ , and there is no need to correct it at this time Wrong; when 3 of the operation results are 1, you can locate the 1-bit original data and the 1-bit check bit data related to the original data. For example, a ₁ , a ₂ , and a ₃ are 1, and others are 0 , according to the same data bit b ₁ contained in the three error detection check formulas, it is located that an error occurred in b ₁ , and because the operation result a ₄ of the error detection check formula related to b ₁ is 0, the check is located When an error occurs in bit eq ₁₅ , it is only necessary to invert and correct b ₁ ; when five of the operation results are 1, one bit of original data and one bit of check bit data irrelevant to the original data can be located An error occurs, such as a ₁ , a ₂ , a ₃ , a ₄ , and a ₅ are 1, and the others are 0. According to the same data bit b ₁ contained in the 4 error detection formulas, locate the error in b ₁ , And because an error occurs in a ₅ , an error cannot occur in b ₂ or b ₃ , which means that an error occurs in eq _23. At this time, it is only necessary to invert and correct b ₁ ; when 6 of the calculation results are 1, you can locate 2 An error occurs in the bit original data, such as a ₂ , a ₃ , a ₄ , a ₅ , a ₆ , and a ₇ are 1, and others are 0, and the 3 error detection formulas contain common data bits b ₁ 3, b ₂ 3 pieces, ₂ pieces of b3, 2 pieces of _b4 , and 2 pieces of _b5 indicate that errors occur in the 2-bit data _b1 and _b2 , and it is sufficient to invert _b1 and _b2 respectively for error correction. In addition, in practical applications, when it is required to perform error detection and error correction on 3-bit or more-bit data according to actual needs, more error detection check formulas can be added as described in the previous steps, specifically as follows: Realize the detection of multi-bit data errors and correct them.

The method shown in Figure 1 can be applied to FPGA devices, and can also be applied to devices containing FIFO, DDR, DRAM or ram-based.

It can be seen that by using network logic coding to encode the N-bit data to be transmitted to obtain encoded data, the receiving module can use logic operations to perform error detection and summing on the N-bit data according to the check digit data and N-bit data in the transmitted encoded data. Error correction. Not only for single-event flipping, but also for multi-event flipping, the purpose of error detection and error correction can be realized, so as to better strengthen the communication data in the device and improve the stability and reliability of the device. Furthermore, the embodiments of the present invention can also be applied to devices including FIFO, DDR, DRAM or ram-based, to perform data error detection and error correction inside the device.

Referring to FIG. 3, FIG. 3 is a schematic structural diagram of a data error correction device according to an embodiment of the present invention, corresponding to the process shown in FIG. , a splitting unit 303 , an arithmetic unit 304 , and an error correction unit 305 .

The network logic encoding unit 301 is used for the sending module of the device, and performs network logic encoding on the N-bit data to be transmitted to obtain encoded data; wherein, the process of performing network logic encoding includes: for the N-bit data to be transmitted For the M-bit data in the N-bit data, logical operations are respectively performed on each group of at least two bits of data in the M-bit data to obtain check digit data corresponding to each group of at least two bits of data; according to a preset combination rule, Combining the N-bit data with the parity bit data to obtain coded data, wherein M is less than or equal to N, and N is not less than 4, and the logic operation is an exclusive OR operation, an exclusive OR operation, an AND operation, or an OR operation , NOT operation, AND NOT operation, OR NOT operation, or AND OR NOT operation;

a sending unit 302, configured to send the encoded data to a receiving module of the device;

The splitting unit 303 is used for the receiving module of the device, splits the received encoded data according to the combination rule, and obtains that each bit of the N-bit data corresponds to each group of at least two bits of data check digit data;

An arithmetic unit 304, configured to determine the data in which errors occur in the encoded data by logical operation according to the N-bit data and the parity bit data corresponding to each group of at least two-bit data;

The error correction unit 305 is configured to, when the erroneous data includes at least one bit of the transmitted N-bit data, perform error correction on at least one bit of the N-bit data.

Specifically, the operation unit may specifically include: a logic operation subunit, an error bit search subunit (not shown in the figure);

A logic operation subunit is used to perform a logic operation on each set of at least two bits of data in the N-bit data and the corresponding check digit data to obtain an operation result;

The error bit search subunit is used to determine that an error occurs in the encoded data according to the number K of logical operations whose operation result is a specified value, and the number of common data bits included in the K logical operations whose operation result is a specified value data, wherein the common data bit is the same data bit included in at least two logical operations among the K logical operations, and K is less than or equal to the number of logical operations corresponding to all the operation results.

Specifically, the error correction unit may specifically include:

The first inversion subunit is used to invert the determined one-bit data when the determined error data contains one-bit data in the N-bit data.

Specifically, the error correction unit may further include:

The second inversion subunit is configured to respectively invert at least two bits of the determined N-bit data when the determined erroneous data includes at least two bits of the N-bit data.

Specifically, the device may be: a field programmable logic gate array device or a device including FIFO, DDR, DRAM or ram-based.

It can be seen that by using network logic coding to encode the N-bit data to be transmitted to obtain encoded data, the receiving module can use logic operations to perform error detection and summing on the N-bit data according to the check digit data and N-bit data in the transmitted encoded data. Error correction. Not only for single-event flipping, but also for multi-event flipping, the purpose of error detection and error correction can be realized, so as to better strengthen the communication data in the device and improve the stability and reliability of the device. Furthermore, the embodiments of the present invention can also be applied to devices including FIFO, DDR, DRAM or ram-based, to perform data error detection and error correction inside the device.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or order between them. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

Each embodiment in this specification is described in a related manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for relevant parts, refer to part of the description of the method embodiment.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present invention are included in the protection scope of the present invention.

Claims (10)

1. a kind of data error-correcting method, applied to the device for including sending module and receiving module, which is characterized in that the method Including：

For the sending module of the device, following operate is performed：

Netted logic coding is carried out for N data to be transmitted, obtains coded data；

Wherein, the step of progress netted logic coding, including：For the M-bit data in N data to be transmitted, to institute Every group in M-bit data at least two bits are stated, carry out logical operation respectively, are obtained corresponding for every group of at least two bits Check bit data；According to default rule of combination, the N data and the check bit data are combined, obtain coded number According to, wherein, M is less than or equal to N, and N is not less than 4, the logical operation for XOR operation, with or operation, with operation or operation, non- Operation, NAND operation, or non-operation or and-or inverter operation；

The coded data is sent to the receiving module of the device；

For the receiving module of the device, following operate is performed：

The coded data received is split according to the rule of combination, obtain each data of the N data with Described every group at least corresponding check bit data of two bits；

According to the N data and every group of at least corresponding check bit data of two bits, using logical operation, institute is determined State the data that mistake occurs in coded data；

When occur mistake data include transmitted N positions data at least a data when, in the N data extremely Few a data carries out error correction.

It is 2. according to the method described in claim 1, it is characterized in that, described according to the N data and every group at least two described Data corresponding check bit data in position using logical operation, determine that the data of mistake occur in the coded data, including：

Respectively for every group in the N data at least two bits and corresponding check bit data, logic fortune is carried out It calculates, obtains operation result；According to the logical operation number K that operation result the is designated value and K that operation result is designated value The number of common data position that logical operation is included determines to occur in the coded data data of mistake, wherein, the public affairs The identical data position that data bit is included by least two logical operations in the K logical operation altogether, K are less than or equal to all fortune Calculate the corresponding logical operation number of result.

3. according to the method described in claim 2, it is characterized in that, at least a data in the N data into Row error correction, including：

When determining wrong data include a bit error number in the N data according to when, identified a data is negated.

4. according to the method described in claim 2, it is characterized in that, at least a data in the N data into Row error correction, including：

When the wrong data determined include the N data at least two bit error numbers according to when, respectively to identified institute At least two bits stated in N data negate.

5. according to the method described in claim 1, it is characterized in that, the device comprising sending module and receiving module is： Field programmable gate array device or the device comprising FIFO, DDR, DRAM or ram-based.

6. a kind of data error correction apparatus, which is characterized in that described device includes：

For the sending module of the device, netted logic volume is carried out for N data to be transmitted for netted logic coding unit Code obtains coded data；Wherein, the process for carrying out netted logic coding includes：For the M in N data to be transmitted Position data, at least two bits of every group in the M-bit data, carry out logical operation respectively, obtain for every group at least two The corresponding check bit data of position data；According to default rule of combination, the N data and the check bit data are subjected to group It closes, obtains coded data, wherein, M is less than or equal to N, and N is not less than 4, and the logical operation is XOR operation, same or operation, with transporting Calculation or operation, inverse, NAND operation, or non-operation or and-or inverter operation；

Transmitting element, for the coded data to be sent to the receiving module of the device；

Split cells for the receiving module of the device, is torn the coded data received open according to the rule of combination Point, obtain each data of the N data and described every group at least corresponding check bit data of two bits；

Arithmetic element, for according to the N data and every group of at least corresponding check bit data of two bits, using patrolling Operation is collected, determines that the data of mistake occur in the coded data；

Error correction unit, for when occur mistake data include transmitted N positions data at least a data when, to described At least a data in N data carries out error correction.

7. device according to claim 6, which is characterized in that the arithmetic element specifically includes：

Logical operation subelement, for respectively for every group in the N data at least two bits and corresponding school A data are tested, logical operation is carried out, obtains operation result；

Subelement is searched in error bit, for being to refer to according to the logical operation number K and operation result that operation result is designated value The number of common data position that K logical operation of definite value is included determines to occur in the coded data data of mistake, In, identical data position that the common data position is included by least two logical operations in the K logical operation, K is less than Logical operation number corresponding equal to all operation results.

8. device according to claim 7, which is characterized in that the error correction unit specifically includes：

First negates subelement, during for including a data in the N data when determining wrong data, to determining A data negate.

9. device according to claim 8, which is characterized in that the error correction unit also specifically includes：

Second negates subelement, for when the wrong data determined include the N data at least two bits when, divide The other at least two bits in the identified N data negate.

10. device according to claim 6, which is characterized in that described device is：Field programmable gate array device Or the device comprising FIFO, DDR, DRAM or ram-based.