CN108242973A - A kind of data error-correcting method and device - Google Patents
A kind of data error-correcting method and device Download PDFInfo
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- CN108242973A CN108242973A CN201611217683.1A CN201611217683A CN108242973A CN 108242973 A CN108242973 A CN 108242973A CN 201611217683 A CN201611217683 A CN 201611217683A CN 108242973 A CN108242973 A CN 108242973A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0041—Arrangements at the transmitter end
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
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Abstract
An embodiment of the present invention provides a kind of data error-correcting method and devices, and applied to the device for including sending module and receiving module, method includes：For the sending module of the device, netted logic coding is carried out for N data to be transmitted, obtains coded data；The coded data is sent to the receiving module of the device；For the receiving module of the device, the coded data received is split according to the rule of combination, obtains each data of the N data and described every group at least corresponding check bit data of two bits；According to the N data and every group of at least corresponding check bit data of two bits, using logical operation, determine that the data of mistake occur in the coded data；When the data that mistake occurs include at least a data in transmitted N positions data, error correction is carried out at least a data in the N data.Using the embodiment of the present invention, the reliability of device is improved.
Description
Technical field
The present invention relates to field of communication technology, more particularly to a kind of data error-correcting method and device.
Background technology
In the evolution in the fields such as entire space flight and nuclear power, based on SRAM (Static Random Access
Memory, static RAM) type FPGA (Field Programmable Gate Array, field-programmable gate array
Row) have the advantages that functional integration is high, resourceful, flexible design, but there is also certain risks.Such as in space industry
In, it is easily influenced by high-order charged particle under the severe radiation environment of the outer space, can by it is various too
The radiation of empty complex environment, the generation for phenomena such as causing single-particle inversion, multiparticle overturning, occurs logical so as to cause FPGA device
The functionality errors of letter data, it is therefore desirable to carry out corresponding communication data reinforcing for above-mentioned phenomenon.Wherein, single-particle inversion
Be primarily referred to as a bit in communication data and occur 0/1 overturning, multiparticle overturning be primarily referred to as two in communication data or
0/1 overturning occurs for multidigit bit, wherein, the probability that three bits and data above overturning mistake occur in space industry is very low.
At present, in the FPGA of space flight or nuclear power station, the redundancy for being usually used in data reinforcing is TMR (Triple
Modular Redundancy, triplication redundancy), part TMR, repeat compared with (DWC, Duplication With
Compare redundancy precision (RPR, reduced precision redundancy) etc.), is reduced.Wherein, TMR technologies will be defeated
The initial data entered directly replicates two parts, and two parts of replicate datas with initial data are combined, coded data is obtained, leads in delivery outlet
It crosses a majority voting device to select three parts of data in coded data, such as initial data is 000, coded data is
000000000, single bit upset occurs in transmission process, coded data becomes 000000100, passes through most tables in delivery outlet
Certainly device understands 000 in outputting encoded data, as decoding data.But when multi-bit errors occur in transmission process,
Such as coded data error becomes 010010000, at this time in the decoding data 010 of delivery outlet meeting output error.As it can be seen that TMR without
Method solve dibit and more than Data flipping mistake, single-particle inversion on FPGA can only be directed to and carry out data reinforcing,
And the situation of multiparticle overturning mistake cannot be handled, the reliability for leading to FPGA device is relatively low.
Invention content
The embodiment of the present invention is designed to provide a kind of data error-correcting method and device, to realize raising device reliability
Purpose.
In order to achieve the above objectives, an embodiment of the present invention provides a kind of data error-correcting method, applied to including sending module
With the device of receiving module, method includes：
For the sending module of the device, following operate is performed：
Netted logic coding is carried out for N data to be transmitted, obtains coded data；
Wherein, the step of progress netted logic coding, including：For the M-bit data in N data to be transmitted,
To at least two bits of every group in the M-bit data, logical operation is carried out respectively, obtains being directed to every group of at least two bits pair
The check bit data answered；According to default rule of combination, the N data and the check bit data are combined, are compiled
Code data, wherein, M be less than or equal to N, N be not less than 4, the logical operation for XOR operation, with or operation, with operation or fortune
Calculation, inverse, NAND operation, or non-operation or and-or inverter operation；
The coded data is sent to the receiving module of the device；
For the receiving module of the device, following operate is performed：
The coded data received is split according to the rule of combination, obtains each digit of the N data
According to described every group at least corresponding check bit data of two bits；
According to the N data and every group of at least corresponding check bit data of two bits, using logical operation, really
The data of mistake occur in the fixed coded data；
When the data that mistake occurs include at least a data in transmitted N positions data, in the N data
At least a data carry out error correction.
Preferably, it is described according to the N data and every group of at least corresponding check bit data of two bits, it utilizes
Logical operation determines to occur in the coded data data of mistake, including：
Respectively for every group in the N data at least two bits and corresponding check bit data, patrolled
Operation is collected, obtains operation result；It is designated value according to the logical operation number K and operation result that operation result is designated value
The number of common data position that is included of K logical operation, determine that the data of mistake occur in the coded data, wherein,
The identical data position that the common data position is included by least two logical operations in the K logical operation, K are less than or equal to
The corresponding logical operation number of all operation results.
Preferably, at least a data in the N data carries out error correction, including：
When determining wrong data include a bit error number in the N data according to when, to identified a data
It negates.
Preferably, at least a data in the N data carries out error correction, including：
When the wrong data determined include the N data at least two bit error numbers according to when, respectively to determining
The N data at least two bits negate.
Preferably, the device comprising sending module and receiving module is：Field programmable gate array device or
Device comprising FIFO, DDR, DRAM or ram-based.
In order to achieve the above objectives, an embodiment of the present invention provides a kind of data error correction apparatus, device includes：
For the sending module of the device, netted patrol is carried out for N data to be transmitted for netted logic coding unit
Coding is collected, obtains coded data；Wherein, the process for carrying out netted logic coding includes：For in N data to be transmitted
M-bit data, at least two bits of every group in the M-bit data, carry out logical operation respectively, obtain for every group at least
The corresponding check bit data of two bits；According to default rule of combination, the N data and the check bit data are subjected to group
It closes, obtains coded data, wherein, M is less than or equal to N, and N is not less than 4, and the logical operation is XOR operation, same or operation, with transporting
Calculation or operation, inverse, NAND operation, or non-operation or and-or inverter operation；
Transmitting element, for the coded data to be sent to the receiving module of the device；
Split cells, for the receiving module of the device, according to the rule of combination to the coded data that receives into
Row is split, and obtains each data of the N data and described every group at least corresponding check bit data of two bits；
Arithmetic element, for according to the N data and every group of at least corresponding check bit data of two bits, profit
With logical operation, determine that the data of mistake occur in the coded data；
Error correction unit, for when occur mistake data include transmitted N positions data at least a data when, it is right
At least a data in the N data carries out error correction.
Preferably, the arithmetic element specifically includes：
Logical operation subelement, for be directed to respectively in the N data every group at least two bits and corresponding
Check bit data, carry out logical operation, obtain operation result；
Subelement is searched in error bit, for according to the logical operation number K and operation result that operation result is designated value
The number of common data position included by K logical operation of designated value determines that the number of mistake occurs in the coded data
According to, wherein, the identical data position that the common data position is included by least two logical operations in the K logical operation, K
Logical operation number corresponding less than or equal to all operation results.
Preferably, the error correction unit specifically includes：
First negates subelement, during for including a data in the N data when determining wrong data, to institute
Determining a data negates.
Preferably, the error correction unit also specifically includes：
Second negates subelement, for including at least two bits in the N data when the wrong data determined
When, at least two bits in the identified N data are negated respectively.
Preferably, described device is：Field programmable gate array device includes FIFO, DDR, DRAM or ram-
The device of based.
A kind of data error-correcting method and device provided in an embodiment of the present invention can utilize netted logic coding to be transmitted
N positions data encoded to obtain coded data, receiving module can be according to the check bit data in the coded data transmitted
With N data, EDC error detection and correction is carried out to N data using logical operation.Single-particle inversion can be not only directed to, for more
Son overturning can also realize the purpose of error detection and error correction, so as to preferably be reinforced to communication data in device, improve device
The stability and reliability of part.Further, the embodiment of the present invention can also be applied to include FIFO, DDR, DRAM or ram-
The device of based carries out the data error detection and error correcting of device inside.Certainly, implement any of the products of the present invention or
Method must be not necessarily required to reach all the above advantage simultaneously.
Description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention, for those of ordinary skill in the art, without creative efforts, can be with
Other attached drawings are obtained according to these attached drawings.
Fig. 1 is a kind of flow diagram of data error-correcting method provided in an embodiment of the present invention；
Fig. 2 is the relation schematic diagram of 5 data to be transmitted provided in an embodiment of the present invention and check bit data；
Fig. 3 is a kind of structure diagram of data error correction apparatus provided in an embodiment of the present invention.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without making creative work
Embodiment shall fall within the protection scope of the present invention.
A kind of data error-correcting method provided in an embodiment of the present invention is described in detail first below.
It should be noted that the embodiment of the present invention is preferably applied to the device comprising sending module and receiving module.Specifically
, in practical applications, which can be：Field programmable gate array device includes FIFO (First Input
First Output, first in first out), DDR (Double Data Rate, Double Data Rate synchronous DRAM), DRAM
The device of (Dynamic Random Access Memory, dynamic random access memory) or ram-based, such as space flight system
FPGA device of system or nuclear power station etc..
Referring to Fig. 1, Fig. 1 is a kind of flow diagram of data error-correcting method provided in an embodiment of the present invention, can be included
Following steps：
For the sending module of the device, following operate is performed：
S101 carries out netted logic coding for N data to be transmitted, obtains coded data；
Specifically, the step of progress netted logic coding, including：For the M digits in N data to be transmitted
According to at least two bits of every group in the M-bit data, carrying out logical operation respectively, obtain for every group of at least double figures
According to corresponding check bit data；According to default rule of combination, the N data and the check bit data are combined, are obtained
To coded data, wherein, M be less than or equal to N, N be not less than 4, the logical operation for XOR operation, with or operation, with operation or
Operation, inverse, NAND operation, or non-operation or and-or inverter operation；
Illustratively, below by taking logical operation is XOR operation as an example, to a kind of data provided in an embodiment of the present invention
Error correction method is described in detail.
Illustratively, default rule of combination can be：Original data bits are in low level, and check bit is in a high position.It is equal to 5, M in N
During equal to 5, for 5 initial data b to be transmitted1、b2、b3、b4、b5, to every group of 2 data in initial data, respectively into
Row XOR operation, XOR operation process can be as shown in table 1.
Table 1
As can be seen from Table 1, it by XOR operation, can obtain being directed to the corresponding check bit eq of every group of 2 data12、
eq13、eq14、eq15、eq23、eq24、eq25、eq34、eq35And eq45, wherein, between 5 initial data and obtained check bit
Relationship it is as shown in Figure 2；According to preset original data bits in low level, check bit in high-order rule of combination, by 5 original numbers
It is combined according to check bit, obtains coded data eq12eq13eq14eq15eq23eq24eq25eq34eq35eq45b1b2b3b4b5(such as
000000000011111)。
Illustratively, in practical applications, when M is less than 5, the partial data position of 5 initial data can also be directed to (such as
4 data bit b1、b2、b3、b4), netted logic coding is carried out, so as to reduce the design complexities of netted logic coding.Its
In, in an encoding process, not only can XOR operation between data bit two-by-two, can be to carry out exclusive or between 3,4 or 5
Arithmetic operation, such as b1、b2、b3Between carry out XOR operation obtain check bitb1、b2、b3、b4Between carry out it is different
Or operation obtains check bit b1、b2、b3、b4、b5Between carry out XOR operation obtain check bit So as to obtain more check bit data.
The coded data is sent to the receiving module of the device by S102；
It is a kind of it might be that carry out true data transmission for coded data is sent to receiving module,
Alternatively possible situation is the transmission environment of analogue data, and is truly carried out data transmission.
In the data transmission of aerospace system, FIFO, DDR, DRAM or other storage devices are typically chosen to store coding
Data, and then the coded data of storage is sent to the receiving module of device.In the present embodiment, the transmission environment of analogue data,
And truly carry out data transmission, FIFO can be selected as storage device, one end receives and sends the coded data output of module,
The data input of one termination receiving module.
For the receiving module of the device, following operate is performed：
S103 splits the coded data received according to the rule of combination, obtains each of the N data
Position data and described every group at least corresponding check bit data of two bits；
Specifically, in practical applications, it is the same (i.e. bit wide=number that in data transmission, the bit wide at both ends, which assume that,
According to bit width+verification bit width), receiving module according to and the bit wide made an appointment in advance of sending module remove parsing, such as needle
To 5 11111 and 10 bit check positions 0000000000 of original data bits, according to aforementioned original data bits in low level, check bit
In high-order rule of combination, coded data 000000000011111 is obtained for combination, the data that bit wide is 15 can be used
Bus is transmitted, and receiving module only need to be using low 5 11111 of the coded data received as data bit, 10 high
0000000000 is used as check bit just.It wherein, can be in sending module and receiving module when the digit of coded data is more
The data bits transmitted every time is appointed before transmission data, and coded data by fixed frame length is sent, connect by sending module in batches
It receives module and merges operation when receiving.Such as the digit of coded data is 50, can set fixed frame length
It is 10 to spend, and is sent 5 times, receiving module just merges operation when being connected to 5 times, then complete coded data obtains after merging
Obtain data bit and corresponding check bit data.
S104 according to the N data and every group of at least corresponding check bit data of two bits, is transported using logic
It calculates, determines that the data of mistake occur in the coded data；
It specifically, can be respectively for every group in the N data at least two bits and corresponding check bit
Data carry out logical operation, obtain operation result；It is the logical operation number K of designated value and operation knot according to operation result
The number of common data position that fruit is included by K logical operation of designated value determines that mistake occurs in the coded data
Data, wherein, the identical data that the common data position is included by least two logical operations in the K logical operation
Position, K are less than or equal to the corresponding logical operation number of all operation results.Wherein, logical operation can also be referred to as error detection verification
Formula.When logical operation is XOR operation, designated value can be 1, represent at this time due to error in data, lead to XOR operation
Mistake.
Illustratively, the data bits of mistake is actually occurred in application scenarios that can be according to embodiments of the present invention, to determine
The number of XOR operation needed for fixed.
Referring also to embodiment illustrated in fig. 2, with reference to the XOR operation of table 1, for every group of 2 data of 5 initial data
b1b2、b1b3、b1b4、b1b5、b2b3、b2b4、b2b5、b3b4、b3b5、b4b5Corresponding check bit eq12、eq13、eq14、eq15、
eq23、eq24、eq25、eq34、eq35、eq45, XOR operation is carried out, following operation result can be obtained：
Error detection foundation for embodiment illustrated in fig. 2 is the operation of 10 error detections verification formulas when an error has occurred
As a result all 0, that is to say, that only occur that operation result can just be caused to be 1 during error in data.In aerospace system, device
When error in data occurs, 99.9999% mistake of generation is 1 error in data or 2 error in data, and such case can be with
1 or 2 error in data are only considered to carry out netted logic coding, determine follow-up required error detection verification formula number.
Assuming that every group of 2 data b for 5 initial data1b2、b1b3、b1b4、b1b5、b2b3、b2b4、b2b5、b3b4、
b3b5、b4b5Corresponding check bit eq12、eq13、eq14、eq15、eq23、eq24、eq25、eq34、eq35、eq45, carry out exclusive or fortune
It calculates, it is as follows to obtain operation result：
According to above-mentioned error checking foundation, 6 XOR operation that operation result is 1 represent 6 error detection schools for mistake occur
Formula is tested, common data position b is included in 6 error detection verification formulas13, b23, b32, b42, b52, due to b1、b2Occur
Number it is most, thus determine occur mistake data bit be b1、b2。
Not considering 3 or 3 data above in above-described embodiment, there is a situation where mistakes, can increase when needing and considering
Error detection verifies formula number, to meet the EDC error detection and correction demand of concrete application scene.In practical applications, it is needing to consider 3 ratios
In the case of special and more bit reversals, exclusive or fortune can be carried out between 2 initial data when carrying out netted logic coding
On the basis of calculation, the XOR operation between 3 initial data, 4 initial data or 5 initial data is carried out, obtains more schools
Test position, such as above-mentioned 5 initial data, after 10 check bit of every group of 2 data are obtained, continue between 3 data into
Row XOR operation obtains eq123、eq124、eq125、eq134、eq135、eq145、eq234、eq235、eq245、eq345, between 5 data into
Row XOR operation obtains eq12345, and then during the wrong data for determining to overturn, available error detection verification formula
Number is 10+10+1=21, and verifying formula using the number K that operation result in these error detection verification formulas is 1 and K error detection includes
Common data position number, to judge that mistake occurs for which specific original data bits or check bit, wherein, be in operation result
During designated value 1, represent that mistake occurs for this error detection verification formula, and K is not more than 21 at this time.
S105 carries out error correction at least a data in the N data.
Specifically, when the data that mistake occurs include at least a data in transmitted N positions data, to the N
At least a data in the data of position carries out error correction.In practical applications, when the data that mistake occurs are check bit data, by
Mistake occurs in check bit data to have an impact the original N-bit data transmitted, so without to check bit data mistake
Accidentally carry out error correction.
Specifically, when determining wrong data include a bit error number in the N data according to when, to identified one
Position data-conversion.
Specifically, when the wrong data determined include the N data at least two bit error numbers according to when, it is right respectively
At least two bits in the identified N data negate.
Illustratively, for every group of 2 data b of 5 initial data as described above1b2、b1b3、b1b4、b1b5、b2b3、
b2b4、b2b5、b3b4、b3b5、b4b5Corresponding check bit eq12、eq13、eq14、eq15、eq23、eq24、eq25、eq34、eq35、
eq45, XOR operation is carried out, obtains operation result, wherein, In a1、a2、a3、a4、a5、a6、a7、a8、a9、a10In, when wherein 1 fortune
When calculation result is 1,1 bit check position error in data can be navigated to, such as only a1It is 1, illustrates eq12Mistake occurs, does not need at this time
Error correction；When wherein 4 operation results are 1,1 initial data mistake, such as a can be navigated to1、a2、a3、a4It is 1, other are
0, illustrate the same data bit b that this 4 wrong error detection verification formulas include1Mistake occurs, to b1Negate error correction；When wherein 2 operations
When being as a result 1,2 bit check position error in data, such as a can be navigated to1、a2It is 1, other are 0, illustrate that original data bits are not sent out
Raw mistake, so check bit eq12、eq13Mistake occurs, does not need to error correction at this time；When wherein 3 operation results are 1,
It navigates to 1 initial data and mistake, such as a occurs for 1 bit trial position data relevant with the initial data1、a2、a3It is 1, other
It is 0, the same data bit b included according to this 3 wrong error detection verification formulas1, orient b1Mistake, and because and b occurs1It is related
Error detection verification formula operation result a4It is 0, orients check bit eq15Mistake occurs, only needs to b at this time1Negate error correction；When
When wherein 5 operation results are 1, can navigate to 1 initial data and with the incoherent 1 bit trial digit of this initial data
According to generation mistake, such as a1、a2、a3、a4、a5It is 1, other are 0, the same data included according to wherein 4 wrong error detection verification formulas
Position b1, orient b1Mistake, and because a occurs5Occur mistake and b2Or b3Mistake can not possibly occur, illustrate eq23Mistake occurs,
It only needs to b at this time1Negate error correction；When wherein 6 operation results are 1,2 initial data can be navigated to, mistake occurs,
Such as a2、a3、a4、a5、a6、a7It is 1, other are 0, wherein 3 error detection verification formulas include common data position b13, b23, b32,
b42, b52, illustrate 2 data b1、b2Mistake occurs, respectively to b1、b2Negate error correction.In addition, in practical applications,
According to actual needs, it is desirable that when carrying out EDC error detection and correction to 3 and more long numeric data, can the step of front described in,
Increase more error detection verification formulas, realization of being specifically subject to detects long numeric data mistake and carries out error correction.
Method can be applied to FPGA device shown in Fig. 1, can also be applied to include FIFO, DDR, DRAM or ram-
The device of based.
As it can be seen that being encoded to obtain coded data to N data to be transmitted using netted logic coding, receiving module can
With the check bit data in the coded data transmitted and N data, N data are carried out using logical operation error detections and
Error correction.Single-particle inversion can be not only directed to, the purpose of error detection and error correction can also be realized for multiparticle overturning, so as to device
Communication data is preferably reinforced in part, improves the stability and reliability of device.Further, the embodiment of the present invention is also
It can be applied to include the device of FIFO, DDR, DRAM or ram-based, carry out the data error detection and mistake of device inside
It corrects.
Referring to Fig. 3, Fig. 3 is a kind of structure diagram of data error correction apparatus for carrying of the embodiment of the present invention, and shown in FIG. 1
Flow is corresponding, which can include：Netted logic coding unit 301, transmitting element 302, split cells 303, fortune
Calculate unit 304, error correction unit 305.
For the sending module of the device, net is carried out for N data to be transmitted for netted logic coding unit 301
Shape logic coding obtains coded data；Wherein, the process for carrying out netted logic coding includes：For N digits to be transmitted
M-bit data in at least two bits of every group in the M-bit data, carries out logical operation respectively, obtains for every group
At least corresponding check bit data of two bits；According to default rule of combination, by the N data and the check bit data into
Row combination, obtain coded data, wherein, M be less than or equal to N, N be not less than 4, the logical operation for XOR operation, with or operation,
With operation or operation, inverse, NAND operation, or non-operation or and-or inverter operation；
Transmitting element 302, for the coded data to be sent to the receiving module of the device；
Split cells 303, for the receiving module of the device, according to the rule of combination to the coded data that receives
It is split, obtains each data of the N data and described every group at least corresponding check bit data of two bits；
Arithmetic element 304, for according to the N data and every group of at least corresponding verification digit of two bits
According to using logical operation, determining that the data of mistake occur in the coded data；
Error correction unit 305, for including at least a data in transmitted N positions data when the data that mistake occurs
When, error correction is carried out at least a data in the N data.
Specifically, the arithmetic element can specifically include：Logical operation subelement, error bit search subelement (in figure
It is not shown)；
Logical operation subelement, for be directed to respectively in the N data every group at least two bits and corresponding
Check bit data, carry out logical operation, obtain operation result；
Subelement is searched in error bit, for according to the logical operation number K and operation result that operation result is designated value
The number of common data position included by K logical operation of designated value determines that the number of mistake occurs in the coded data
According to, wherein, the identical data position that the common data position is included by least two logical operations in the K logical operation, K
Logical operation number corresponding less than or equal to all operation results.
Specifically, the error correction unit can specifically include：
First negates subelement, during for including a data in the N data when determining wrong data, to institute
Determining a data negates.
Specifically, the error correction unit can also specifically include：
Second negates subelement, for including at least two bits in the N data when the wrong data determined
When, at least two bits in the identified N data are negated respectively.
Specifically, described device can be：Field programmable gate array device or comprising FIFO, DDR, DRAM or
The device of ram-based.
As it can be seen that being encoded to obtain coded data to N data to be transmitted using netted logic coding, receiving module can
With the check bit data in the coded data transmitted and N data, N data are carried out using logical operation error detections and
Error correction.Single-particle inversion can be not only directed to, the purpose of error detection and error correction can also be realized for multiparticle overturning, so as to device
Communication data is preferably reinforced in part, improves the stability and reliability of device.Further, the embodiment of the present invention is also
It can be applied to include the device of FIFO, DDR, DRAM or ram-based, carry out the data error detection and mistake of device inside
It corrects.
It should be noted that herein, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any this practical relationship or sequence.Moreover, term " comprising ", "comprising" or its any other variant are intended to
Non-exclusive inclusion, so that process, method, article or equipment including a series of elements not only will including those
Element, but also including other elements that are not explicitly listed or further include as this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
Also there are other identical elements in process, method, article or equipment including the element.
Each embodiment in this specification is described using relevant mode, identical similar portion between each embodiment
Point just to refer each other, and the highlights of each of the examples are difference from other examples.Especially for system reality
For applying example, since it is substantially similar to embodiment of the method, so description is fairly simple, related part is referring to embodiment of the method
Part explanation.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the scope of the present invention.It is all
Any modification, equivalent replacement, improvement and so within the spirit and principles in the present invention, are all contained in protection scope of the present invention
It is interior.
Claims (10)
1. a kind of data error-correcting method, applied to the device for including sending module and receiving module, which is characterized in that the method
Including：
For the sending module of the device, following operate is performed：
Netted logic coding is carried out for N data to be transmitted, obtains coded data；
Wherein, the step of progress netted logic coding, including：For the M-bit data in N data to be transmitted, to institute
Every group in M-bit data at least two bits are stated, carry out logical operation respectively, are obtained corresponding for every group of at least two bits
Check bit data；According to default rule of combination, the N data and the check bit data are combined, obtain coded number
According to, wherein, M is less than or equal to N, and N is not less than 4, the logical operation for XOR operation, with or operation, with operation or operation, non-
Operation, NAND operation, or non-operation or and-or inverter operation；
The coded data is sent to the receiving module of the device；
For the receiving module of the device, following operate is performed：
The coded data received is split according to the rule of combination, obtain each data of the N data with
Described every group at least corresponding check bit data of two bits；
According to the N data and every group of at least corresponding check bit data of two bits, using logical operation, institute is determined
State the data that mistake occurs in coded data；
When occur mistake data include transmitted N positions data at least a data when, in the N data extremely
Few a data carries out error correction.
It is 2. according to the method described in claim 1, it is characterized in that, described according to the N data and every group at least two described
Data corresponding check bit data in position using logical operation, determine that the data of mistake occur in the coded data, including：
Respectively for every group in the N data at least two bits and corresponding check bit data, logic fortune is carried out
It calculates, obtains operation result；According to the logical operation number K that operation result the is designated value and K that operation result is designated value
The number of common data position that logical operation is included determines to occur in the coded data data of mistake, wherein, the public affairs
The identical data position that data bit is included by least two logical operations in the K logical operation altogether, K are less than or equal to all fortune
Calculate the corresponding logical operation number of result.
3. according to the method described in claim 2, it is characterized in that, at least a data in the N data into
Row error correction, including：
When determining wrong data include a bit error number in the N data according to when, identified a data is negated.
4. according to the method described in claim 2, it is characterized in that, at least a data in the N data into
Row error correction, including：
When the wrong data determined include the N data at least two bit error numbers according to when, respectively to identified institute
At least two bits stated in N data negate.
5. according to the method described in claim 1, it is characterized in that, the device comprising sending module and receiving module is：
Field programmable gate array device or the device comprising FIFO, DDR, DRAM or ram-based.
6. a kind of data error correction apparatus, which is characterized in that described device includes：
For the sending module of the device, netted logic volume is carried out for N data to be transmitted for netted logic coding unit
Code obtains coded data；Wherein, the process for carrying out netted logic coding includes：For the M in N data to be transmitted
Position data, at least two bits of every group in the M-bit data, carry out logical operation respectively, obtain for every group at least two
The corresponding check bit data of position data；According to default rule of combination, the N data and the check bit data are subjected to group
It closes, obtains coded data, wherein, M is less than or equal to N, and N is not less than 4, and the logical operation is XOR operation, same or operation, with transporting
Calculation or operation, inverse, NAND operation, or non-operation or and-or inverter operation；
Transmitting element, for the coded data to be sent to the receiving module of the device；
Split cells for the receiving module of the device, is torn the coded data received open according to the rule of combination
Point, obtain each data of the N data and described every group at least corresponding check bit data of two bits；
Arithmetic element, for according to the N data and every group of at least corresponding check bit data of two bits, using patrolling
Operation is collected, determines that the data of mistake occur in the coded data；
Error correction unit, for when occur mistake data include transmitted N positions data at least a data when, to described
At least a data in N data carries out error correction.
7. device according to claim 6, which is characterized in that the arithmetic element specifically includes：
Logical operation subelement, for respectively for every group in the N data at least two bits and corresponding school
A data are tested, logical operation is carried out, obtains operation result；
Subelement is searched in error bit, for being to refer to according to the logical operation number K and operation result that operation result is designated value
The number of common data position that K logical operation of definite value is included determines to occur in the coded data data of mistake,
In, identical data position that the common data position is included by least two logical operations in the K logical operation, K is less than
Logical operation number corresponding equal to all operation results.
8. device according to claim 7, which is characterized in that the error correction unit specifically includes：
First negates subelement, during for including a data in the N data when determining wrong data, to determining
A data negate.
9. device according to claim 8, which is characterized in that the error correction unit also specifically includes：
Second negates subelement, for when the wrong data determined include the N data at least two bits when, divide
The other at least two bits in the identified N data negate.
10. device according to claim 6, which is characterized in that described device is：Field programmable gate array device
Or the device comprising FIFO, DDR, DRAM or ram-based.
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