CN110489267B - Memory and method for reinforcing data to be stored - Google Patents
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Abstract
The invention relates to a memory and a method for reinforcing data to be stored, wherein the memory comprises: the data reinforcing module is used for reinforcing data to be stored and comprises: the error correction and detection unit is used for carrying out error correction and detection coding and decoding on the data to be stored; a check code obtaining unit connected to the error correction and detection unit for obtaining a check code used in the process of error correction and detection coding; the check code copying unit is connected to the check code acquiring unit and is used for copying the check code to ensure that the number of the check code is 3; the data splitting and recombining unit is used for splitting and recombining the data; and the data splicing unit is connected to the check code copying unit, connected to the data splitting and recombining unit and used for splicing the split and recombined data with the copied check code to acquire the reinforced data for storage.
Description
Technical Field
The present invention relates to the field of memories, and in particular, to a memory and a method for reinforcing data to be stored.
Background
With the high-speed development of integrated circuits, memories are more and more important, wherein static memories (SRAMs) have been widely used in various high-speed memories due to their high speed and low power consumption, and SRAMs have also been widely used in circuit systems of various aerospace devices. When an SEE mainly enters a device by high-energy particles in the universe, such as heavy nuclear particles and alpha particles, the charges deposited on the tracks of the SEE are collected by sensitive nodes to cause signal inversion of a memory. Therefore, the SRAM used in aerospace should have good single event effect resistance as well as its own characteristics.
For the memory consolidation, a duplication Redundancy method is often used in the prior art, in which hamming code encoding is performed on data first, and then Triple Modular Redundancy (TMR) is applied to the generated new data. However, in this way, on one hand, the original data and the check code are copied simultaneously during triple modular redundancy copy, which requires a large area of the memory, and on the other hand, due to the characteristics of the hamming code, only one bit of error can be corrected, which is relatively poor for the situation of continuous multi-bit inversion caused by high-energy particles.
Referring to fig. 1, the conventional TMR design mainly copies a standard D-flip flop (DFF) cell for reinforcement into 3 parts, and for convenience of description, the three D-flip flops are respectively named A, B, C. And then, carrying out 2-from-3 voting on the outputs of the 3D trigger units, wherein the method reduces the probability of soft errors when the standard D trigger is used for transmitting data in terms of probability, and the circuit structure of the voting circuit is shown in FIG. 2, and the one-bit signal inversion can be filtered by the 2-from-3 voting circuit. The output F of the voting circuit is equal to A, B, C majority (e.g., a equals 1, B equals 1, C equals 0, and then F equals 1), which increases reliability by making use of spatial redundancy.
Although the technical scheme in the prior art can achieve better performance, the technical scheme needs to occupy larger memory area.
Disclosure of Invention
The invention aims to provide a memory and a method for reinforcing data to be stored, which can meet the reinforcement requirement and reduce the occupied amount of the memory.
In order to solve the above technical problem, the present invention provides a memory, including: the data reinforcing module is used for reinforcing data to be stored and comprises: the error correction and detection unit is used for carrying out error correction and detection coding and decoding on the data to be stored; a check code obtaining unit connected to the error correction and detection unit for obtaining a check code used in the process of error correction and detection coding; the check code copying unit is connected to the check code acquiring unit and is used for copying the check code to ensure that the number of the check code is 3; the data splitting and recombining unit is connected to the error correcting and detecting unit and is used for splitting and recombining the data; and the data splicing unit is connected to the check code copying unit and the data splitting and recombining unit and is used for splicing the split and recombined data with the copied check code to acquire the reinforced data for storage.
Optionally, the check code copying unit includes: and the number of the standard D triggers is consistent with the number of copies to be copied by the check code copying unit, and each standard D trigger is connected to the check code acquiring unit and outputs a copied check code.
Optionally, the data splitting and recombining unit includes: the first splitting subunit is used for sequentially splitting the data to be stored from the highest bit to the lowest bit to obtain 32-bit first subdata; the second splitting subunit is connected to the first splitting subunit, connected to the error correction and detection unit, and configured to sequentially split the first sub data from a highest bit to a lowest bit, and obtain first to fourth second sub data of each 8-bit share; and the third splitting subunit is connected to the second splitting subunit and is used for sequentially splitting the second subdata from the highest bit to the lowest bit to obtain the first to fourth subdata of each 2-bit share.
Optionally, the data splitting and recombining unit further includes: a reassembly subunit, connected to the third splitting subunit, for performing reassembly on the first subdata, where the reassembly rule includes: integrating third subdata which belongs to the same first subdata and has the same sequence to form first to fourth recombined subdata, wherein the first to fourth recombined subdata respectively correspond to all combinations of the first to fourth third subdata of the first subdata; and in the recombined subdata, the third subdata with the same sequence number is arranged from the highest position to the lowest position according to the ascending order of the sequence number of the second subdata to which the third subdata is subordinate.
Optionally, the data splicing unit splices the data according to the following rules: and correspondingly adding the copying results of the check codes of the first to fourth groups of second subdata respectively after the lowest bits of the first to fourth groups of subdata, and finishing splicing.
Optionally, the error correction and detection unit is a hamming code error correction and detection unit, and is configured to perform hamming code error correction and detection coding and decoding on the second sub-data, and the number of check codes generated by each part of the second sub-data is five bits.
In order to solve the technical problem, the invention provides a method for reinforcing data to be stored, which comprises the following steps: carrying out error correction and error detection coding on data to be stored; acquiring a check code used in the error correction and detection coding process, and copying the check code into three parts; and splicing the copied three check codes with the data to be stored to form reinforced data.
Optionally, before performing error correction and error detection coding on the data to be stored, the method further includes the following steps: splitting the data to be stored from the highest bit to the lowest bit in sequence to obtain 32-bit first subdata; and splitting the first subdata from the highest bit to the lowest bit in sequence to obtain first subdata, second subdata and fourth subdata of each 8-bit part.
Optionally, when performing error correction and error detection coding and decoding on data to be stored, the method includes the following steps: and carrying out Hamming code error correction and detection coding on the second subdata, and generating a five-bit check code by each 8-bit second subdata.
Optionally, before splicing the copied three check codes with the data to be stored, the method includes the following steps: splitting the second subdata from the highest bit to the lowest bit in sequence to obtain first subdata, second subdata, third subdata and third subdata of each 2 bits; integrating third subdata which belongs to the same first subdata and has the same sequence to form first to fourth recombined subdata, wherein the first to fourth recombined subdata respectively correspond to all combinations of the first to fourth third subdata of the first subdata; arranging the third subdata with the same sequence number from the highest position to the lowest position according to the ascending order of the sequence number of the second subdata to which the third subdata is subordinate to form the recombined subdata; and correspondingly adding the copying results of the check codes of the first to fourth sub-data respectively after the lowest bits of the first to fourth sub-data to finish splicing.
The memory and the method for reinforcing the data to be stored firstly reinforce the data when writing the data, firstly carry out Hamming code coding on the data to be stored to generate a check code, and then only carry out copy redundancy on the check code, thereby balancing the radiation resistance and the memory area occupied by the coded data. And then, splicing the redundant check code with the data to be stored, so that the original data can still be recovered to a certain extent when the high-energy particles cause multi-bit inversion. Further, when reading the reinforced data stored in the memory, firstly, three check codes can be used for obtaining a check code through a voting circuit, then, the original data is restored according to the splicing rule, then, the obtained check code is spliced with the data to be processed for error correction and detection, if an error smaller than or equal to one bit occurs, correct data can be obtained after error correction and detection, and if an error larger than one bit occurs, an error flag bit is returned to inform a user that at least two bits of errors occur in the currently stored data.
Drawings
Fig. 1 is a schematic diagram of a copy redundancy structure in the prior art.
Fig. 2 is a schematic diagram of a voting circuit structure in the prior art.
Fig. 3 is a schematic flow chart of consolidating data to be stored in the prior art.
FIG. 4 is a diagram illustrating a memory structure according to an embodiment of the present invention.
FIG. 5 is a diagram illustrating steps of a method for consolidating data to be stored according to an embodiment of the present invention.
Detailed Description
The following describes a memory and a method for consolidating data to be stored according to the present invention in further detail with reference to the accompanying drawings and the detailed description.
Fig. 4 is a schematic structural diagram of a memory according to an embodiment of the invention.
In this particular embodiment, a memory is provided, comprising: the data reinforcing module is used for reinforcing data to be stored and comprises: an error correction and detection unit 401, configured to perform error correction and detection encoding and decoding on data to be stored; a check code obtaining unit 402, connected to the error correction and detection unit 401, for obtaining a check code used in the process of error correction and detection coding; a check code copying unit 403, connected to the check code obtaining unit 402, configured to copy the check code, so that the number of copies of the check code is 3; a data splitting and recombining unit 404, connected to the error correcting and detecting unit 401, for splitting and recombining data; and the data splicing unit 405 is connected to the check code copying unit 403 and the data splitting and recombining unit 404, and is configured to splice the split and recombined data with the copied check code, and obtain the reinforced data for storage.
In a specific embodiment, the check code copying unit 403 includes: the number of the standard D flip-flops is consistent with the number of copies to be copied by the check code copying unit 403, and each standard D flip-flop is connected to the check code obtaining unit 402 and outputs a copied check code.
In a specific embodiment, the data splitting and recombining unit 404 includes: the first splitting subunit is used for sequentially splitting the data to be stored from the highest bit to the lowest bit to obtain 32-bit first subdata; the second splitting subunit is connected to the first splitting subunit, connected to the error correction and detection unit, and configured to sequentially split the first sub data from a highest bit to a lowest bit, and obtain first to fourth second sub data of each 8-bit share; and the third splitting subunit is connected to the second splitting subunit and is used for sequentially splitting the second subdata from the highest bit to the lowest bit to obtain the first to fourth subdata of each 2-bit share.
The data splitting and recombining unit further comprises: a reassembly subunit, connected to the third splitting subunit, for performing reassembly on the first subdata, where the reassembly rule includes: integrating third subdata which belongs to the same first subdata and has the same sequence to form first to fourth recombined subdata, wherein the first to fourth recombined subdata respectively correspond to all combinations of the first to fourth third subdata of the first subdata; and in the recombined subdata, the third subdata with the same sequence number is arranged from the highest position to the lowest position according to the ascending order of the sequence number of the second subdata to which the third subdata is subordinate.
In a specific embodiment, the data splicing unit 405 splices the following rules: and correspondingly adding the copying results of the check codes of the first to fourth groups of second subdata respectively after the lowest bits of the first to fourth groups of subdata, and finishing splicing.
In a specific embodiment, the error correction and detection unit 401 is a hamming code error correction and detection unit, and is configured to hamming code encode and decode the second sub-data, and the number of check codes generated by each second sub-data is five bits, so that, in the decoding stage, a single-bit error in the read data can be corrected, and a condition of a two-bit error can be detected.
In a specific embodiment, the number of the check code used by the hamming code error correction and detection unit 401 is 5 bits, and after a five-bit check code is added to the second sub-data, the check code occupies the 0 th power to the 3 rd power of 2 of the data to which the check code is added, and the highest bit of the data to which the check code is added.
In this way, for a group of first subdata, the number of bits of formed reinforced data is 92 bits, the number of bits is less, and because a hamming code error correction and detection code is used, five check codes are correspondingly generated every 8 bits, so that in a decoding stage, one bit error in read data can be corrected, and the condition of two bit errors can be detected, and the method is simple and convenient.
In a specific embodiment, the memory further includes a voting circuit, connected to the check code copying unit 403, configured to perform voting carry on the copied check code, where the output check code is a majority of the copied check code, so that when a user decodes the reinforced data using the check code, the voted check code is used, and the error probability is smaller, which is beneficial to smooth decoding of the reinforced data.
In one embodiment, the voting circuit is a 2-out-of-3 voting circuit, which is directly related to the number of copies of the check code.
Fig. 5 is a schematic diagram illustrating steps of a method for consolidating data to be stored according to an embodiment of the present invention.
In this embodiment, there is also provided a method for consolidating data to be stored, including the steps of: s51, carrying out error correction and error detection coding on the data to be stored; s52, acquiring a check code used in the error correction and detection coding process, and copying the check code into three parts; and S53, splicing the copied three check codes and the data to form reinforced data.
In one embodiment, before performing error correction and error detection coding on data to be stored, the method further includes the following steps: splitting the data to be stored from the highest bit to the lowest bit in sequence to obtain 32-bit first subdata; and splitting the first subdata from the highest bit to the lowest bit in sequence to obtain first subdata, second subdata and fourth subdata of each 8-bit part.
In one embodiment, when encoding and decoding error correction and detection of data to be stored, the method comprises the following steps: and carrying out Hamming code error correction and detection coding on the second subdata, and generating a five-bit check code by each 8-bit second subdata.
In a specific embodiment, before splicing the copied three check codes with the data to be stored, the method includes the following steps: splitting the second subdata from the highest bit to the lowest bit in sequence to obtain first subdata, second subdata, third subdata and third subdata of each 2 bits; integrating third subdata which belongs to the same first subdata and has the same sequence to form first to fourth recombined subdata, wherein the first to fourth recombined subdata respectively correspond to all combinations of the first to fourth third subdata of the first subdata; and arranging the third subdata with the same sequence number from the highest position to the lowest position according to the ascending order of the sequence number of the second subdata to which the third subdata is subordinate, so as to form the recombined subdata. Third subdata to be stored is formed through splitting and recombining of data, so that when the high-energy particles cause multi-Bit inversion (MBU) of the reinforced data, the original data can still be recovered to a certain extent.
(ii) a And correspondingly adding the copying results of the check codes of the first to fourth sub-data respectively after the lowest bits of the first to fourth sub-data to finish splicing.
In the method for reinforcing data to be stored according to the specific embodiment, when data is written, the data is encoded by a hamming code to generate a check code, and then only the check code is subjected to triple modular redundancy replication. Thus, the balance between the radiation resistance and the memory area occupied by the encoded data is obtained.
In a specific implementation mode, when reinforced data is read, firstly, three redundant copied check codes pass through a two-out-of-three voting circuit, a majority of the copied check codes is output, then original data is recovered according to a splitting and recombining rule of the reinforced data, reverse operation is carried out on related splitting and recombining steps, then an obtained check code and the original data are spliced to carry out error correction and error detection, if errors smaller than or equal to one bit occur, correct data can be obtained after error correction and error detection, and if errors larger than one bit occur, an error flag bit is returned to inform a processor that the data have errors.
The first embodiment is as follows:
since the data length processed in a computer is generally an integral multiple of 32 or 32 bits, when the data length is not 32 bits, the original data can still be split into 32 bits, so that the following processing is performed on the original data assumed to be 32 bits:
(1) the original data is divided into four parts, each part is 8 bits, and the four parts are respectively recorded as a [7: 0), b [7: 0), c [7:0, d [7:0 ];
(2) and generating a check code for the split 8-bit data, generating a 5-bit check code for each 8 bits and a 5-bit check code for each 8 bits according to a Hamming code coding rule of 13_8, so that after the Hamming code is used for coding the original data, one bit of error in the data can be corrected, and two bit of error in the data can be detected. For the generated 5-bit check code, we respectively mark parity _ a [ 4: 0), parity _ b [ 4: 0), parity _ c [ 4: 0), parity _ d [ 4: 0 ];
(3) and copying each check code into three parts, recombining four parts of 8-bit data, and recording the recombined data as A [7: 0), B [7: 0), C [7: 0), D [7:0], rules of recombination include:
A[7：0]＝{a[7:6]、b[7:6]、c[7:6]、d[7:6]}；
B[7：0]＝{a[5:4]、b[5:4]、c[5:4]、d[5:4]}；
C[7：0]＝{a[3:2]、b[3:2]、c[3:2]、d[3:2]}；
D[7：0]＝{a[1:0]、b[1:0]、c[1:0]、d[1:0]}；
(4) and splicing the recombined DATA with a redundant check code, wherein the spliced DATA is DATA _ A, DATA _ B, DATA _ C, DATA _ D and is written into a memory. The rules for splicing include:
DATA_A＝{A[7:0]、parity_a[4：0]、parity_a[4：0]、parity_a[4：0]}；
DATA_B＝{B[7:0]、parity_b[4：0]、parity_b[4：0]、parity_b[4：0]}；
DATA_C＝{C[7:0]、parity_c[4：0]、parity_c[4：0]、parity_c[4：0]}；
DATA_D＝{D[7:0]、parity_d[4：0]、parity_d[4：0]、parity_d[4：0]}；
in this embodiment, the original 32-bit data, after being encoded, only needs 92 bits.
If the method in the prior art is used and the data is encoded according to the hamming code encoding rule of 13-8, after the original 32-bit data is processed and the reinforced data is formed, the data finally written into the memory module is as follows:
DATA_A＝{a[7:0]、parity_a[4：0]、a[7:0]、parity_a[4：0]、a[7:0]、parity_a[4：0]}；
DATA_B＝{b[7:0]、parity_b[4：0]、b[7:0]、parity_b[4：0]、b[7:0]、parity_b[4：0]}；
DATA_C＝{c[7:0]、parity_c[4：0]、c[7:0]、parity_c[4：0]、c[7:0]、parity_c[4：0]}；
DATA_D＝{d[7:0]、parity_d[4：0]、d[7:0]、parity_d[4：0]、d[7:0]、parity_d[4：0]}；
at this time, the 32-bit data is changed into 156 bits after the reinforcement coding, and the occupied memory is large.
Therefore, by adopting the method in the embodiment, compared with the traditional method combined with the Hamming code coding rule of 13-8, the bit number is saved by 41%, and the occupied area of the memory in the reinforcing process is greatly saved.
Assuming the memory is under the influence of energetic particles, A [ 6: and 5, errors of two continuous bits occur, if the data to be stored are not split and recombined, the Hamming code decoding module cannot correct the errors of the two continuous bits, so that the stored data have errors, and the processor can only be informed to rewrite correct data. However, if a new splitting and recombining method is adopted to split and recombine the data to be stored, A6 and A5 are a 6 and b 7 respectively and correspond to the original data blocks a and b, so that only one bit of data error occurs to the original data blocks respectively, and correct data can be restored by the Hamming code decoding module at the moment, and therefore, through the splitting and recombining processing of the data, the performance of the memory module for resisting multi-bit upset is improved on the premise of reducing the area of the memory.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (8)
1. A memory, comprising:
the data reinforcing module is used for reinforcing data to be stored and comprises:
the error correction and detection unit is used for carrying out error correction and detection coding and decoding on the data to be stored;
a check code obtaining unit connected to the error correction and detection unit for obtaining a check code used in the process of error correction and detection coding;
the check code copying unit is connected to the check code acquiring unit and is used for copying the check code to ensure that the number of the check code is 3;
the data splitting and recombining unit is connected to the error correcting and detecting unit and is used for splitting and recombining the data; the data splitting and recombining unit comprises:
the first splitting subunit is used for sequentially splitting the data to be stored from the highest bit to the lowest bit to obtain 32-bit first subdata;
the second splitting subunit is connected to the first splitting subunit, connected to the error correction and detection unit, and configured to sequentially split the first sub data from a highest bit to a lowest bit, and obtain first to fourth second sub data of each 8-bit share;
the third splitting subunit is connected to the second splitting subunit and is used for sequentially splitting the second subdata from the highest bit to the lowest bit to obtain first to fourth subdata of each 2-bit share;
and the data splicing unit is connected to the check code copying unit and the data splitting and recombining unit and is used for splicing the split and recombined data with the copied check code to acquire the reinforced data for storage.
2. The memory according to claim 1, wherein the check code copying unit comprises:
and the number of the standard D triggers is consistent with the number of copies to be copied by the check code copying unit, and each standard D trigger is connected to the check code acquiring unit and outputs a copied check code.
3. The memory according to claim 1, wherein the data splitting and reassembling unit further comprises:
a reassembly subunit, connected to the third splitting subunit, for performing reassembly on the first subdata, where the reassembly rule includes:
integrating third subdata which belongs to the same first subdata and has the same sequence to form first to fourth recombined subdata, wherein the first to fourth recombined subdata respectively correspond to all combinations of the first to fourth third subdata of the first subdata;
and in the recombined subdata, the third subdata with the same sequence number is arranged from the highest position to the lowest position according to the ascending order of the sequence number of the second subdata to which the third subdata is subordinate.
4. The memory according to claim 3, wherein the data splicing unit splices as follows:
and correspondingly adding the copying results of the check codes of the first to fourth groups of second subdata respectively after the lowest bits of the first to fourth groups of subdata, and finishing splicing.
5. The memory according to claim 1, wherein the error correction and detection unit is a hamming code error correction and detection unit for hamming code error correction and detection encoding and decoding the second sub-data, and the number of check codes generated for each sub-data is five bits.
6. A method of consolidating data to be stored, comprising the steps of:
carrying out error correction and error detection coding on data to be stored;
acquiring a check code used in the error correction and detection coding process, and copying the check code into three parts;
splicing the copied three check codes with the data to be stored to form reinforced data; wherein the content of the first and second substances,
before the data to be stored is subjected to error correction and error detection coding, the method also comprises the following steps:
splitting the data to be stored from the highest bit to the lowest bit in sequence to obtain 32-bit first subdata;
and splitting the first subdata from the highest bit to the lowest bit in sequence to obtain first subdata, second subdata and fourth subdata of each 8-bit part.
7. The method for consolidating data to be stored according to claim 6, wherein when encoding and decoding error correction and detection of the data to be stored, the method comprises the following steps:
and carrying out Hamming code error correction and detection coding on the second subdata, and generating a five-bit check code by each 8-bit second subdata.
8. The method for reinforcing data to be stored according to claim 7, wherein when the copied three check codes are spliced with the data to be stored, the method comprises the following steps:
splitting the second subdata from the highest bit to the lowest bit in sequence to obtain first subdata, second subdata, third subdata and third subdata of each 2 bits;
integrating third subdata which belongs to the same first subdata and has the same sequence to form first to fourth recombined subdata, wherein the first to fourth recombined subdata respectively correspond to all combinations of the first to fourth third subdata of the first subdata;
arranging the third subdata with the same sequence number from the highest position to the lowest position according to the ascending order of the sequence number of the second subdata to which the third subdata is subordinate to form the recombined subdata;
and correspondingly adding the copying results of the check codes of the first to fourth sub-data respectively after the lowest bits of the first to fourth sub-data to finish splicing.
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