CN114220474A - Data processing method, device and storage medium - Google Patents
Data processing method, device and storage medium Download PDFInfo
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- CN114220474A CN114220474A CN202111351149.0A CN202111351149A CN114220474A CN 114220474 A CN114220474 A CN 114220474A CN 202111351149 A CN202111351149 A CN 202111351149A CN 114220474 A CN114220474 A CN 114220474A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
Abstract
The application provides a data processing method, a device and a storage medium, wherein the method comprises the following steps: carrying out Error Correction Code (ECC) encoding on the original data to generate an original ECC check code; copying the original ECC check code to obtain an ECC check code group comprising three identical original ECC check codes; storing the original data and the ECC check code group in the NAND flash memory; when the original data is obtained from the NAND flash memory, the target ECC check code is determined based on the ECC check code group, and the original data stored in the NAND flash memory is checked based on the target ECC check code to obtain the target data. According to the method and the device, the reliability of the ECC check code is improved by copying the ECC check code, the probability of failure caused by the fact that the ECC check code is attacked is greatly reduced, the correctness of the ECC check code is greatly improved, and therefore the probability of consistency of target data verified based on the ECC check code and original data is improved.
Description
Technical Field
The present invention relates to the field of aerospace, and in particular, to a data processing method, device, and storage medium.
Background
Because the NAND flash memory (NAND FLASH memory) has the characteristics of high density and large capacity, it is widely used in various electronic systems. In the aerospace field, it is also common to store NAND FLASH the data in memory, and wait for the master controller to call up the data for data access. However, in the space radiation environment, there are solar cosmic rays, silver river cosmic rays and the like, these rays have extremely high energy, when high-energy particles hit NAND FLASH memory cells, abnormal phenomena such as single-bit flipping and multi-bit flipping can occur to the semiconductor device, especially multi-bit flipping, which can cause large-scale errors in data stored in NAND FLASH device, and if serious, cause the whole system to be abnormal.
Currently, to solve the problem of NAND FLASH data bit flipping, it is common to perform Error Correction Code (ECC) check on data, perform ECC encoding on the data when writing NAND FLASH memory, and store the original data and the check code together in NAND FLASH. When reading data, the original data and the check code are read together, ECC decoding is carried out, and the inverted error bit is corrected.
However, the ECC check code is also stored in the NAND FLASH memory, and since the check code stored in the NAND FLASH memory is also affected by cosmic rays, when high-energy particles hit the location of the ECC storage cell, the check code is inverted, and when the number of bits of the inverted check code is large, the subsequent original data cannot be corrected.
Disclosure of Invention
The application mainly aims to provide a data processing method, data processing equipment and a storage medium. And correcting the reversed bits of the ECC check code by adopting a system-level reinforcement method through performing triple modular redundancy on the check code, and performing subsequent ECC decoding and error correction.
In view of this, a first aspect of the embodiments of the present application provides a data processing method, where the data processing method includes: carrying out Error Correction Code (ECC) encoding on the original data to generate an original ECC check code; copying the original ECC check code to obtain an ECC check code group, wherein the ECC check code group comprises a plurality of original ECC check codes which are the same ECC check code; storing the original data and the ECC check code group in a NAND flash memory; when the original data is obtained from the NAND flash memory, a target ECC check code is determined based on the ECC check code group, and the original data stored in the NAND flash memory is checked based on the target ECC check code to obtain target data. According to the embodiment of the application, the reliability of the ECC check code is improved by copying the ECC check code, the probability of failure caused by the fact that the ECC check code is attacked is greatly reduced, the correctness of the ECC check code is greatly improved, and therefore the probability of consistency of target data verified based on the ECC check code and original data is improved.
In one possible embodiment, the ECC check code group includes 3 ECC check codes, and the determining the target ECC check code based on the ECC check code group includes: sequentially comparing whether corresponding bits among 3 ECC check codes are consistent or not, wherein the 3 ECC check codes respectively comprise m bits; for the kth bit of the target ECC check code, if the values of two ECC check codes in the kth bit are consistent in the 3 ECC check codes, determining the consistent value as the value of the kth bit of the target ECC check code.
In one possible embodiment, the ECC check code group includes 3 ECC check codes, and the determining the target ECC check code based on the ECC check code group includes: sequentially comparing whether corresponding bits among 3 ECC check codes are consistent or not, wherein the 3 ECC check codes respectively comprise m bits; and for the k bit of the target ECC check code, when the values of the 3 ECC check codes at the k bit are consistent, determining the consistent value as the value of the k bit of the target ECC check code.
In one possible implementation, the programs are stored in a programmable read-only memory PROM.
In one possible embodiment, the programs include an ECC check code triple modular redundancy program, an ECC encoding program, and an ECC decoding program.
A second aspect of the embodiments of the present application provides a data processing apparatus, including: the generating unit is used for carrying out Error Correction Code (ECC) coding on the original data to generate an original ECC check code; the copying unit is used for copying the original ECC check code to obtain an ECC check code group, wherein the ECC check code group comprises a plurality of original ECC check codes, and the plurality of original ECC check codes are the same ECC check code; the storage unit is used for storing the original data and the ECC check code group in the NAND flash memory; and the determining unit is used for determining a target ECC check code based on the ECC check code group when the original data is acquired from the NAND flash memory, and checking the original data stored in the NAND flash memory based on the target ECC check code to obtain target data. According to the embodiment of the application, the reliability of the ECC check code is improved by copying the ECC check code, the probability of failure caused by the fact that the ECC check code is attacked is greatly reduced, the correctness of the ECC check code is greatly improved, and therefore the probability of consistency of target data verified based on the ECC check code and original data is improved.
In a possible implementation manner, the ECC check code group includes 3 ECC check codes, and the determining unit is specifically configured to compare whether corresponding bits among the 3 ECC check codes are consistent in sequence, where the 3 ECC check codes include m bits respectively; for the kth bit of the target ECC check code, if the values of two ECC check codes in the kth bit are consistent in the 3 ECC check codes, determining the consistent value as the value of the kth bit of the target ECC check code.
In a possible implementation manner, the ECC check code group includes 3 ECC check codes, and the determining unit is specifically configured to compare whether corresponding bits among the 3 ECC check codes are consistent in sequence, where the 3 ECC check codes include m bits respectively; and for the k bit of the target ECC check code, when the values of the 3 ECC check codes at the k bit are consistent, determining the consistent value as the value of the k bit of the target ECC check code.
In a possible embodiment, the memory unit is also used to store programs in a programmable read-only memory PROM.
In one possible embodiment, the programs include an ECC check code redundancy program, an ECC encoding program, and an ECC decoding program. In one possible embodiment, the NAND flash memory includes a data area and a redundancy area; the storage unit is specifically configured to: and respectively storing the original data and the ECC check code group in the data area and the redundant area.
A third aspect of the present application provides a computer-readable storage medium having stored therein instructions, which, when run on a computer, cause the computer to perform the method of the above-described aspects.
A fourth aspect of the application provides a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to cause the computer device to perform the method provided by the above aspects.
According to the technical scheme, the embodiment of the application has the following advantages:
the application provides a data processing method, a device and a storage medium, wherein the method comprises the following steps: carrying out ECC encoding on the original data to generate an original ECC check code; copying the original ECC check code to obtain an ECC check code group, wherein the ECC check code group comprises a plurality of original ECC check codes which are the same ECC check code; storing the original data and the ECC check code group in a NAND flash memory; when the original data is obtained from the NAND flash memory, a target ECC check code is determined based on the ECC check code group, and the original data stored in the NAND flash memory is checked based on the target ECC check code to obtain target data. According to the embodiment of the application, the reliability of the ECC check code is improved by copying the ECC check code, the probability of failure caused by the fact that the ECC check code is attacked is greatly reduced, the correctness of the ECC check code is greatly improved, and therefore the probability of consistency of target data verified based on the ECC check code and original data is improved.
Drawings
FIG. 1 is a schematic flow chart illustrating a data processing method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a NAND flash memory according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of an embodiment of a data processing apparatus according to the present application;
FIG. 4 is a block diagram of an embodiment of a data processing system according to the present application;
fig. 5 is a schematic structural diagram of another embodiment of a data processing system according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The term "and/or" appearing in the present application may be an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" in this application generally indicates that the former and latter related objects are in an "or" relationship.
The terms "first," "second," and the like in the description and in the claims of the present application and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein. Moreover, the terms "comprises," "comprising," and any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or modules is not necessarily limited to those steps or modules explicitly listed, but may include other steps or modules not expressly listed or inherent to such process, method, article, or apparatus.
Because the NAND flash memory (NAND FLASH memory) has the characteristics of high density and large capacity, it is widely used in various electronic systems. In the aerospace field, it is also common to store NAND FLASH the data in memory, and wait for the master controller to call up the data for data access. However, in the space radiation environment, there are solar cosmic rays, silver river cosmic rays and the like, these rays have extremely high energy, when high-energy particles hit NAND FLASH memory cells, abnormal phenomena such as single-bit flipping and multi-bit flipping can occur to the semiconductor device, especially multi-bit flipping, which can cause large-scale errors in data stored in NAND FLASH device, and if serious, cause the whole system to be abnormal.
Currently, to solve the problem of NAND FLASH data bit flipping, it is common to perform Error Correction Code (ECC) check on data, perform ECC encoding on the data when writing NAND FLASH memory, and store the original data and the check code together in NAND FLASH. When reading data, the original data and the check code are read together, ECC decoding is carried out, and the inverted error bit is corrected.
However, the ECC check code is also stored in the NAND FLASH memory, and since the check code stored in the NAND FLASH memory is also affected by cosmic rays, when high-energy particles hit the location of the ECC storage cell, the check code is inverted, and when the number of bits of the inverted check code is large, the subsequent original data cannot be corrected.
The application mainly aims to provide a data processing method, data processing equipment and a storage medium. And correcting the reversed bits of the ECC check code by adopting a system level reinforcement method through carrying out multimode redundancy on the check code, and carrying out subsequent ECC decoding and error correction.
Referring to fig. 1, to solve the above problem, an embodiment of the present application provides a data processing method, where the data processing method includes:
101. carrying out ECC encoding on the original data to generate an original ECC check code;
ECC was developed on the basis of parity. As is known, in a digital circuit, the smallest data unit is called "bit", also called "data bit", and the "bit" is also the smallest unit in the memory, which represents the high and low level signals of data by "1" and "0". In the digital circuit, 8 continuous bits are a byte (byte), each byte in the memory without parity has only 8 bits, and if a bit of the byte stores an error, the corresponding data stored in the byte will be changed, which results in an error of the application program. In addition to each byte (8 bits), there is an additional bit in the memory with "parity" for error detection. For example, a byte stores a certain number (1, 0, 1), each bit is added up (1+0+1+0+1+ 5), 5 is an odd number, if an odd check is used (i.e., the sum of 9 bits of a byte (8 bits) plus the 1 bit of the error detection is an odd number), then the bit of the error detection should be 0(5+ 0-5 is an odd number), if an even check is used (i.e., the sum of 9 bits of a byte (8 bits) plus the 1 bit of the error detection is an even number), then the bit of the error detection should be 1(5+ 1-6 is an even number), when the CPU returns to read the stored data, it adds up the data stored in the previous 8 bits again, and the calculation result is consistent with the check bit. The CPU attempts to correct these errors when it finds that the two are different. But the deficiency of Parity is: when the memory finds that a certain data bit has an error, the data bit with the error cannot be accurately positioned, and the error cannot be corrected.
The Parity memory checks the correctness of 8 bits of data on the data bit by adding a check bit on the basis of the original data bit, but the check bit is multiplied along with the increase of the data bit, eight bits of data bit need one check bit, and sixteen bits of data bit need two check bits. ECC is also implemented by adding check bits to the original data bits. It is different from Parity in that if the data bit is 8 bits, 5 bits are needed to be added for ECC error checking and correction, and each time the data bit is doubled, the ECC is added with only one check bit, that is, when the data bit is 16 bits, the ECC bit is 6 bits, when the data bit is 32 bits, the ECC bit is 7 bits, when the data bit is 64 bits, the ECC bit is 8 bits, and so on, when the data bit is doubled, the ECC bit is added with only one bit. ECC has more check bits and stronger fault-tolerant capability.
102. Copying the original ECC check code to obtain an ECC check code group, wherein the ECC check code group comprises a plurality of original ECC check codes which are the same ECC check code;
generally, for the guarantee of the reliability of the ECC check code and the comprehensive consideration of the storage space and efficiency, the ECC check code may be copied into 3 copies, and 3 ECC check codes constitute an ECC check code group.
103. Storing the original data and the ECC check code group in a NAND flash memory;
referring to fig. 2, the NAND flash memory may include a data area and a redundant area, and storing the original data and the ECC check code group in the NAND flash memory includes: the original data and the ECC check code groups are stored in the data area and the redundant area, respectively.
104. And when the original data is acquired from the NAND flash memory, determining a target ECC check code based on the ECC check code group, and checking the original data stored in the NAND flash memory based on the target ECC check code to obtain the target data.
If the ECC check code group comprises 3 ECC check codes, and the 3 ECC check codes respectively comprise m bits, sequentially comparing whether corresponding bits among the 3 ECC check codes are consistent; m is a positive integer greater than or equal to 2; when the k bit values among the 3 ECC check codes are consistent, determining that the k bit value in the target ECC check code is the k bit value in the 3 ECC check codes, wherein k is any natural number from 1 to m.
When the values of the kth bit among the ECC check codes are not consistent, if the values of the kth bit of two ECC check codes in the 3 ECC check codes are consistent, determining that the consistent value is the value of the kth bit of the target ECC check code. For example, when the k-th bit of each ECC check code in the ECC check code group is 0, 0, and 1, respectively, the value of the k-th bit of the ECC check code is considered to be 0, and the number of k-th bits in 3 ECC check codes is 2 and the number of 1 is 1 in the above example, that is, it is considered that 1 appears as that the bit in the ECC check code group is affected by the cosmic ray to cause the flipping.
The invention provides a data processing method, which comprises the following steps: carrying out error correction ECC coding on the original data to generate an original ECC check code; copying the original ECC check code to obtain an ECC check code group, wherein the ECC check code group comprises a plurality of original ECC check codes which are the same ECC check code; storing the original data and the ECC check code group in the NAND flash memory; and when the original data is acquired from the NAND flash memory, determining a target ECC check code based on the ECC check code group, and checking the original data stored in the NAND flash memory based on the target ECC check code to obtain the target data. According to the embodiment of the application, the reliability of the ECC check code is improved by copying the ECC check code, the probability of failure caused by the fact that the ECC check code is attacked is greatly reduced, the correctness of the ECC check code is greatly improved, and therefore the probability of consistency of target data verified based on the ECC check code and original data is improved.
With reference to fig. 3, a schematic structural diagram of a data processing apparatus according to an embodiment of the present application is shown, where the data processing apparatus 300 includes:
a generating unit 301, configured to perform error correction ECC encoding on the original data to generate an original ECC check code.
A copying unit 302, configured to copy the original ECC check code to obtain an ECC check code group, where the ECC check code group includes multiple original ECC check codes, and the multiple original ECC check codes are all identical ECC check codes;
a storage unit 303, configured to store the original data and the ECC check code group in a NAND flash memory;
a determining unit 304, configured to determine a target ECC check code based on the ECC check code group when the original data is obtained from the NAND flash memory, and check the original data stored in the NAND flash memory based on the target ECC check code to obtain target data.
According to the embodiment of the application, the reliability of the ECC check code is improved by copying the ECC check code, the probability of failure caused by the fact that the ECC check code is attacked is greatly reduced, the correctness of the ECC check code is greatly improved, and therefore the probability of consistency of target data verified based on the ECC check code and original data is improved.
Optionally, on the basis of the embodiment corresponding to fig. 3, in another embodiment of the data processing apparatus 300 provided in this embodiment of the present application, the ECC check code group includes 3 ECC check codes, and the determining unit is specifically configured to compare whether corresponding bits among the 3 ECC check codes are consistent in sequence, where the 3 ECC check codes respectively include m bits; for the kth bit of the target ECC check code, if the values of two ECC check codes in the kth bit are consistent in the 3 ECC check codes, determining the consistent value as the value of the kth bit of the target ECC check code.
Optionally, on the basis of the embodiment corresponding to fig. 3, in another embodiment of the data processing apparatus 300 provided in this embodiment of the present application, the ECC check code group includes 3 ECC check codes, and the determining unit is specifically configured to compare whether corresponding bits among the 3 ECC check codes are consistent in sequence, where the 3 ECC check codes respectively include m bits; and for the k bit of the target ECC check code, when the values of the 3 ECC check codes at the k bit are consistent, determining the consistent value as the value of the k bit of the target ECC check code.
Optionally, on the basis of the embodiment corresponding to fig. 3, in another embodiment of the data processing apparatus 300 provided in the embodiment of the present application, the storage unit 303 is further configured to store the programs in a programmable read only memory PROM.
Optionally, on the basis of the embodiment corresponding to fig. 3, in another embodiment of the data processing apparatus 300 provided in the embodiment of the present application, the programs include an ECC check code redundancy program, an ECC encoding program, and an ECC decoding program.
Optionally, on the basis of the embodiment corresponding to fig. 3, in another embodiment of the data processing apparatus 300 provided in the embodiment of the present application, the NAND flash memory includes a data area and a redundant area; the storage unit 304 is specifically configured to: and respectively storing the original data and the ECC check code group in the data area and the redundant area.
The data processing method and the data processing apparatus in the present embodiment are introduced in detail above, and the data processing system 400 provided in the present embodiment is introduced below, and the data processing system in the embodiment of the present application is described below. Specifically, referring to fig. 4, fig. 4 is a schematic structural diagram of an embodiment of a data processing system in an embodiment of the present application, and as shown in fig. 4, the data processing system includes a processor 401, a programmable read-only memory (PROM) 402 coupled to the processor, and a NAND flash memory 403. In some implementations, they may be coupled together by a bus. The processor 401 may be a Central Processing Unit (CPU), a Network Processor (NP), or a combination of the CPU and the NP. The processor may also be an application-specific integrated circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof. The programmable read-only memory PROM402 stores therein a redundancy program, an ECC encoding program, and an ECC decoding program, and the NAND flash memory 403 is used to store original data and an ECC check code.
The PROM402 is a read-only memory, and after 1 programming, the PROM402 can only perform read operation, and the PROM402 has high radiation resistance, so that the PROM402 is adopted to store redundancy programs, ECC encoding programs and ECC decoding programs, and errors of the redundancy programs, the ECC encoding programs and the ECC decoding programs are prevented.
Referring to fig. 5, the redundancy program may be a triple modular redundancy program, which has the principle of selecting two from three, and by backing up one data into three, the original data can be restored as long as two or three data in the three data do not occur simultaneously and have the same error. In the NAND flash memory, three sets of ECC check data are respectively placed in the storage units, and because the three sets of data are independent, the probability that the same data in two or three sets of data is simultaneously copied by high-energy particles is very low, and therefore, even if one set of ECC data is copied to be wrong, the correct data can be restored.
In this patent, the flow of reading and writing data by the CPU is as follows:
1. programming: the CPU controller writes a triple modular redundancy program and an ECC encoding/decoding program into a PROM memory in a burning mode;
2. data ECC encoding: the CPU calls an ECC encoding program from the PROM, carries out ECC encoding on the original data, generates an ECC check code and copies the ECC check code into three parts;
3. writing data; writing original data and 3 parts of ECC check codes into a NAND FLASH storage unit together, wherein the original data is stored in a data area, and the 3 parts of ECC check codes are stored in a redundant area;
4. reading data: the CPU controller sends a command to read the original data and the ECC check code, then calls a triple modular redundancy program from the PROM, compares three ECC check codes and corrects an error bit in the ECC check code;
5. and (3) data ECC decoding: the CPU controller calls an ECC decoding program in the PROM, and the NAND FLASH data are corrected by the ECC check code.
According to the embodiment of the application, the reliability of the ECC check code is improved by copying the ECC check code, the probability of failure caused by the fact that the ECC check code is attacked is greatly reduced, the correctness of the ECC check code is greatly improved, and therefore the probability of consistency of target data verified based on the ECC check code and original data is improved.
Also provided in the embodiments of the present application is a computer-readable storage medium, which stores a computer program, and when the computer program runs on a computer, the computer program causes the computer to execute the steps performed by the server in the method described in the foregoing embodiment shown in fig. 1.
Also provided in an embodiment of the present application is a computer program product including a program, which when run on a computer causes the computer to perform the steps performed by the server in the method as described in the embodiment of fig. 1.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions in actual implementation, for example, at least two units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may also be distributed on at least two network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
In the examples provided herein, it should be understood that the disclosed methods may be implemented in other ways without exceeding the scope of the present application. The present embodiment is an exemplary example only, and should not be taken as limiting, and the specific disclosure should not be taken as limiting the purpose of the application. For example, some features may be omitted, or not performed.
The technical means disclosed in the present application is not limited to the technical means disclosed in the above embodiments, and includes technical means formed by any combination of the above technical features. It should be noted that, for those skilled in the art, without departing from the principle of the present application, several improvements and modifications can be made, and these improvements and modifications are also considered to be within the scope of the present application.
The pulse amplitude acquisition device and the pulse amplitude acquisition method provided by the embodiment of the present application are described in detail above, and a specific example is applied in the present application to explain the principle and the implementation of the present application, and the description of the above embodiment is only used to help understand the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application. Although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (10)
1. A data processing method, characterized in that the data processing method comprises:
carrying out Error Correction Code (ECC) encoding on the original data to generate an original ECC check code;
copying the original ECC check code to obtain an ECC check code group, wherein the ECC check code group comprises a plurality of original ECC check codes which are the same ECC check code;
storing the original data and the ECC check code group in a NAND flash memory;
when the original data is obtained from the NAND flash memory, a target ECC check code is determined based on the ECC check code group, and the original data stored in the NAND flash memory is checked based on the target ECC check code to obtain target data.
2. The data processing method of claim 1, wherein the ECC check code group includes 3 ECC check codes, and the determining the target ECC check code based on the ECC check code group includes:
sequentially comparing whether corresponding bits among 3 ECC check codes are consistent or not, wherein the 3 ECC check codes respectively comprise m bits;
for the kth bit of the target ECC check code, if the values of two ECC check codes in the kth bit are consistent in the 3 ECC check codes, determining the consistent value as the value of the kth bit of the target ECC check code.
3. The data processing method of claim 1, wherein the ECC check code group includes 3 ECC check codes, and the determining the target ECC check code based on the ECC check code group includes:
sequentially comparing whether corresponding bits among 3 ECC check codes are consistent or not, wherein the 3 ECC check codes respectively comprise m bits;
and for the k bit of the target ECC check code, when the values of the 3 ECC check codes at the k bit are consistent, determining the consistent value as the value of the k bit of the target ECC check code.
4. A data processing method as claimed in any one of claims 1 to 3, characterized in that the programs are stored in a programmable read-only memory PROM.
5. The data processing method of claim 4, wherein the programs include an ECC check code triple modular redundancy program, an ECC encoding program, and an ECC decoding program.
6. A data processing apparatus, characterized in that the data processing apparatus comprises:
the generating unit is used for carrying out Error Correction Code (ECC) coding on the original data to generate an original ECC check code;
the copying unit is used for copying the original ECC check code to obtain an ECC check code group, wherein the ECC check code group comprises a plurality of original ECC check codes, and the plurality of original ECC check codes are the same ECC check code;
the storage unit is used for storing the original data and the ECC check code group in the NAND flash memory;
and the determining unit is used for determining a target ECC check code based on the ECC check code group when the original data is acquired from the NAND flash memory, and checking the original data stored in the NAND flash memory based on the target ECC check code to obtain target data.
7. The data processing apparatus according to claim 6, wherein the ECC check code group includes 3 ECC check codes, and the determining unit is specifically configured to sequentially compare whether corresponding bits among the 3 ECC check codes are consistent, where the 3 ECC check codes respectively include m bits; for the kth bit of the target ECC check code, if the values of two ECC check codes in the kth bit are consistent in the 3 ECC check codes, determining the consistent value as the value of the kth bit of the target ECC check code.
8. The data processing apparatus according to claim 6, wherein the ECC check code group includes 3 ECC check codes, and the determining unit is specifically configured to sequentially compare whether corresponding bits among the 3 ECC check codes are consistent, where the 3 ECC check codes respectively include m bits; and for the k bit of the target ECC check code, when the values of the 3 ECC check codes at the k bit are consistent, determining the consistent value as the value of the k bit of the target ECC check code.
9. A computer device, comprising: programmable read only memory, transceiver, processor and bus system;
wherein, the programmable read only memory is used for storing programs;
the processor is configured to execute a program in the memory to implement the method of any one of claims 1 to 5;
the bus system is used for connecting the memory and the processor so as to enable the memory and the processor to communicate.
10. A computer-readable storage medium comprising instructions that, when executed on a computer, cause the computer to perform the method of any of claims 1 to 5.
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