CN108847849B - Basic coding and decoding unit and coder-decoder - Google Patents
Basic coding and decoding unit and coder-decoder Download PDFInfo
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- CN108847849B CN108847849B CN201810826940.4A CN201810826940A CN108847849B CN 108847849 B CN108847849 B CN 108847849B CN 201810826940 A CN201810826940 A CN 201810826940A CN 108847849 B CN108847849 B CN 108847849B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
Abstract
The application discloses a basic coding and decoding unit and a coder-decoder, wherein the basic coding and decoding unit comprises two same logic circuits which are used for coding and decoding respectively; the logic circuit includes the same number of input pins and output pins and a number of exclusive or gates. The basic coding and decoding unit in the coding circuit can enable coding and decoding to use the same circuit, and complexity and manufacturing cost of circuit design are reduced. During digital communication, if bit reversal occurs, parity of data can not be changed, so that a receiving party can directly carry out parity check on the coded data, and directly abandons the data when the check fails, thereby avoiding waste of computing resources caused by decoding invalid data with bit reversal.
Description
Technical Field
The present application relates to the field of coding and decoding technologies, and in particular, to a basic coding and decoding unit and a codec.
Background
Digital circuits are now widely used. It is often necessary to encode the original information for purposes of information hiding, error checking, etc. The coding algorithm may be implemented by a software program or may be implemented by a hardware circuit. Software implementation of coding algorithms is more flexible, but the required computation time and power consumption are usually much higher than for hardware coding circuits. In power consumption sensitive application occasions such as the internet of things, a hardware circuit is often used for coding. In the prior art, in the information hiding coding hardware implementation, different circuits are usually used for the coding function and the decoding function, which increases the complexity of circuit design and manufacturing cost. On the other hand, the encoded data usually cannot maintain the parity of the original data (i.e. when there are odd 1 s in the original data, there may be odd 1 s or even 1 s in the encoded data), and it is necessary to receive and decode all the data during transmission to determine whether bit flipping occurs through parity check, and if it is found that bit flipping occurs, the computing resource is wasted.
Disclosure of Invention
The present application aims to provide a codec unit and a codec, wherein encoding and decoding are implemented by using the same circuit, and encoded data can maintain parity, when the codec circuit is used for digital communication, a receiver can directly perform parity check on the encoded data, and directly discard the data when the check fails, thereby avoiding waste of computing resources due to decoding of invalid data with bit flipping.
A basic coding and decoding unit comprises two same logic circuits, wherein the two same logic circuits are used for coding and decoding respectively; the logic circuit includes the same number of input pins and output pins and a number of exclusive or gates.
As above, wherein the logic circuit comprises eight input pins and eight output pins, each input pin is associated with five output pins through an xor gate.
As above, wherein each input pin is connected to an input of a first xor gate, an output of the first xor gate being a first output pin, associating the input pin with the first output pin; and each input pin is connected with the input end of the second exclusive-or gate, the output end of the second exclusive-or gate is connected with the input end of the third exclusive-or gate, the output end of the third exclusive-or gate is connected with the input ends of the fourth exclusive-or gate, the fifth exclusive-or gate, the sixth exclusive-or gate and the seventh exclusive-or gate, and the output ends of the fourth exclusive-or gate, the fifth exclusive-or gate, the sixth exclusive-or gate and the seventh exclusive-or gate are respectively used as a second output pin, a third output pin, a fourth output pin and a fifth output pin, so that the input pins are respectively associated with the second output pin, the third output pin, the fourth output pin and the fifth output pin.
As above, the logic circuit includes fourteen exclusive or gates, which are defined as exclusive or gate 1, exclusive or gate 2, exclusive or gate 3, exclusive or gate 4, exclusive or gate 5, exclusive or gate 6, exclusive or gate a, exclusive or gate B, exclusive or gate C, exclusive or gate D, exclusive or gate E, exclusive or gate F, exclusive or gate G, and exclusive or gate H, and 8 input pins are defined as i1, i2, i3, i4, i5, i6, i7, i8, and 8 output pins are defined as o1, o2, o3, o4, o5, o6, o7, o8, wherein the input pin i1 is connected to an input terminal of the exclusive or gate F, and an output terminal of the exclusive or gate F is the output pin o 6; the input pin i1 is connected to the input terminal of the xor gate 1, the output terminal of the xor gate 1 is connected to the input terminal of the xor gate 6, the output terminal of the xor gate 6 is connected to the input terminal of the xor gate C, D, E, G, and the output terminals of the xor gate C, D, E, G are the output pins o3, o4, o5, and o7, respectively.
As above, the input pin i2 is connected to the input terminal of the xor gate H, and the output terminal of the xor gate H is the output pin o 1; the input pin i2 is connected with the input end of the exclusive or gate 1, the output end of the exclusive or gate 1 is connected with the input end of the exclusive or gate 6, the output end of the exclusive or gate 6 is connected with the input end of the exclusive or gate C, D, E, G, and the output ends of the exclusive or gate C, D, E, G are output pins o3, o4, o5 and o7 respectively; the input pin i3 is connected with the input end of the exclusive-or gate D, and the output end of the exclusive-or gate D is an output pin o 5; the input pin i3 is connected to the input terminal of the xor gate 2, the output terminal of the xor gate 2 is connected to the input terminal of the xor gate 5, the output terminal of the xor gate 5 is connected to the input terminals of the xor gate a, the xor gate B, the xor gate F and the xor gate H, and the output terminals of the xor gate a, the xor gate B, the xor gate F and the xor gate H are the output pins o1, o2, o6 and o8, respectively.
As above, the input terminal i4 of the xor gate C is connected, and the output terminal of the xor gate C is the output terminal o 3; the input pin i4 is connected with the input end of the exclusive-or gate 2, the output end of the exclusive-or gate 2 is connected with the input end of the exclusive-or gate 5, the output end of the exclusive-or gate 5 is connected with the input ends of the exclusive-or gate A, the exclusive-or gate B, the exclusive-or gate F and the exclusive-or gate H, and the output ends of the exclusive-or gate A, the exclusive-or gate B, the exclusive-or gate F and the exclusive-or gate H are respectively output pins o1, o2, o6 and o 8; the input pin i5 is connected with the input end of the exclusive-or gate G, and the output end of the exclusive-or gate G is an output pin o 3; the input pin i5 is connected to the input terminal of the xor gate 3, the output terminal of the xor gate 3 is connected to the input terminal of the xor gate 5, the output terminal of the xor gate 5 is connected to the input terminals of the xor gate a, the xor gate B, the xor gate F and the xor gate H, and the output terminals of the xor gate a, the xor gate B, the xor gate F and the xor gate H are the output pins o1, o2, o6 and o8, respectively.
As above, the input pin i6 is connected to the input terminal of the xor gate a, and the output terminal of the xor gate a is the output pin o 1; the input pin i6 is connected to the input terminal of the xor gate 4, the output terminal of the xor gate 4 is connected to the input terminal of the xor gate 6, the output terminal of the xor gate 6 is connected to the input terminals of the xor gate C, the xor gate D, the xor gate E, and the xor gate G, and the output terminals of the xor gate C, the xor gate D, the xor gate E, and the xor gate G are the output pins o3, o4, o5, and o7, respectively.
As above, the input pin i7 is connected to the input terminal of the xor gate E, and the output terminal of the xor gate E is the output pin o 5; the input pin i7 is connected to the input terminal of the xor gate 3, the output terminal of the xor gate 3 is connected to the input terminal of the xor gate 5, the output terminal of the xor gate 5 is connected to the input terminals of the xor gate a, the xor gate B, the xor gate F and the xor gate H, and the output terminals of the xor gate a, the xor gate B, the xor gate F and the xor gate H are the output pins o1, o2, o6 and o8, respectively.
As above, the input pin i8 is connected to the input terminal of the xor gate B, and the output terminal of the xor gate B is the output pin o 2; the input pin i8 is connected to the input terminal of the xor gate 4, the output terminal of the xor gate 4 is connected to the input terminal of the xor gate 6, the output terminal of the xor gate 6 is connected to the input terminals of the xor gate C, the xor gate D, the xor gate E, and the xor gate G, and the output terminals of the xor gate C, the xor gate D, the xor gate E, and the xor gate G are the output pins o3, o4, o5, and o7, respectively.
A codec comprising a number of basic codec units according to claims 1-9 and a number of flip-flops, the number of flip-flops being the same as the number of output pins of the basic codec units; each output pin is connected to the D terminal of a corresponding flip-flop.
The beneficial effect of this application is as follows:
(1) the basic coding and decoding unit and the basic coding and decoding unit in the coder and decoder can enable coding and decoding to use the same circuit, and complexity and manufacturing cost of circuit design are reduced.
(2) The basic coding and decoding unit and the coder and decoder provided by the application can not change the parity of data if bit reversal occurs during digital communication, so that a receiving party can directly carry out parity check on the coded data, and directly abandons the data when the check fails, thereby avoiding the waste of computing resources caused by decoding invalid data with bit reversal.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to the drawings.
Fig. 1 is a circuit diagram of an internal structure of a basic codec unit according to an embodiment of the present disclosure;
fig. 2 is a circuit connection structure diagram of a byte codec according to an embodiment of the present application;
fig. 3 is a connection structure diagram of two byte codecs according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The basic coding and decoding unit provided by the embodiment of the application comprises two independent and same logic circuits, and the two logic circuits are used for coding and decoding respectively.
Specifically, the same device may include two logic circuits, where the two logic circuits respectively form an encoder and a decoder, the encoder is configured to send encoded data to a decoder of another device, and the decoder is configured to receive encoded data sent by the other device and decode the encoded data. Wherein the internal structural connection of the encoder and decoder is described below.
As shown in fig. 1, the logic circuit includes a plurality of xor gates, 8 input pins, and 8 output pins.
Illustratively, the 8 input pins are labeled i1, i2, i3, i4, i5, i6, i7, i8, and the 8 output pins are labeled o1, o2, o3, o4, o5, o6, o7, o 8.
Specifically, each xor gate has two input pins and one output pin, and each input pin is connected to 5 output pins through a different xor gate, and the specific connection relationship is described below.
The input pins of each exclusive-or gate are defined as a first pin and a second pin from top to bottom respectively, four exclusive-or gates on the left in the figure are defined as an exclusive-or gate 1, an exclusive-or gate 2, an exclusive-or gate 3 and an exclusive-or gate 4, two exclusive-or gates in the middle are defined as an exclusive-or gate 5 and an exclusive-or gate 6, and 8 exclusive-or gates on the right are defined as an exclusive-or gate A, an exclusive-or gate B, an exclusive-or gate C, an exclusive-or gate D, an exclusive-or gate E, an exclusive-or gate F, an exclusive-or gate G and an exclusive-or gate H.
As shown in fig. 1, the input pin i1 is connected to the first input pin of the xor gate F and the first input pin of the xor gate 1, the output pin of the xor gate 1 is connected to the first input pin of the xor gate 6, the output pin of the xor gate 6 is connected to the second input pin of the xor gate C, D, G and the first input pin of the xor gate E, that is, the input pin i1 is associated with the output pins o6, o3, o4, o5 and o 7.
The input pin i2 is connected to the second output pin of the xor gate H and the second input pin of the xor gate 1, respectively, the output pin of the xor gate 1 is connected to the first input pin of the xor gate 6, the output pin of the xor gate 6 is connected to the second input pin of the xor gate C, D, G, respectively, and the first input pin of the xor gate E, that is, the input pin i1 is associated with the output pins o8, o3, o4, o5, and o 7.
The input pin i3 is connected to a first input pin of the xor gate D and a first input pin of the xor gate 2, respectively, the output pin of the xor gate 2 is connected to a first input pin of the xor gate 5, and the output pins of the xor gate 5 are connected to first output pins of the xor gate a, the xor gate B, and the xor gate H, respectively, and a second output pin of the xor gate F, that is, the input pin i3 is associated with the output pins o4, o1, o2, o6, and o 8.
The input pin i4 is connected to a first input pin of the xor gate C and a second input pin of the xor gate 2, respectively, the output pin of the xor gate 2 is connected to a first input pin of the xor gate 5, and the output pins of the xor gate 5 are connected to first output pins of the xor gate a, the xor gate B, and the xor gate H, respectively, and a second output pin of the xor gate F, that is, the input pin i4 is associated with the output pins o3, o1, o2, o6, and o 8.
The input pin i5 is connected to a first input pin of the xor gate G and a first input pin of the xor gate 3, respectively, the output pin of the xor gate 3 is connected to a second input pin of the xor gate 5, and the output pins of the xor gate 5 are connected to first output pins of the xor gate a, the xor gate B, and the xor gate H, respectively, and a second output pin of the xor gate F, that is, the input pin i5 is associated with the output pins o7, o1, o2, o6, and o 8.
The input pin i6 is connected to the second input pin of the xor gate a and the first input pin of the xor gate 4, respectively, the output pin of the xor gate 4 is connected to the second input pin of the xor gate 6, the output pin of the xor gate 6 is connected to the second input pin of the xor gate C, D, G, respectively, and the first input pin of the xor gate E, that is, the input pin i6 is associated with the output pins o1, o3, o4, o5, and o 7.
The input pin i7 is connected to a second input pin of the xor gate E and a second input pin of the xor gate 3, respectively, the output pin of the xor gate 3 is connected to a second input pin of the xor gate 5, and the output pins of the xor gate 5 are connected to first output pins of the xor gate a, the xor gate B, and the xor gate H, respectively, and a second output pin of the xor gate F, that is, the input pin i7 is associated with the output pins o5, o1, o2, o6, and o 8.
The input pin i8 is connected to the second input pin of the xor gate B and the second input pin of the xor gate 4, respectively, the output pin of the xor gate 4 is connected to the second input pin of the xor gate 6, the output pin of the xor gate 6 is connected to the second input pin of the xor gate C, D, G, respectively, and the first input pin of the xor gate E, that is, the input pin i8 is associated with the output pins o2, o3, o4, o5, and o 7.
In summary, in the circuit diagram of the internal structure of the basic codec unit provided in this embodiment, 8 input pins i1-i8 can be respectively associated with 5 xor gates in the xor gates a-H, so that each input pin is associated with 5 output pins through an xor gate, and when any input bit is inverted, 5 output bits are inverted, which is equivalent to amplifying the decoded erroneous data, so that the error is easier to detect during application, and on the other hand, the parity of the data is not changed. Similarly, each output pin is associated with five input pins. Specifically, o1 is associated with i6, i3, i4, i5 and i7, o2 is associated with i8, i3, i4, i5 and i7, o3 is associated with i4, i1, i2, i6 and i8, o4 is associated with i3, i1, i2, i6 and i8, o5 is associated with i7, i1, i2, i6 and i8, o6 is associated with i1, i3, i4, i5 and i7, o7 is associated with i1, i2, i5, i6 and i8, o8 is associated with i3, i2, i4, i5 and i 7.
During encoding, original data is input into the logic circuit from the input pins, encoded data is output from the output pins, and each output pin corresponds to a logic expression. Specifically, as can be seen from the above description, o1 ═ i6^ i3^ i4^ i5^ i 7; o2 ═ i7^ i3^ i4^ i5^ i 8; o3 ═ i2^ i1^ i4^ i6^ i 8; o4 ═ i1^ i2^ i3^ i6^ i 8; o5 ═ i1^ i2^ i8^ i6^ i 7; o6 ═ i3^ i4^ i5^ i7^ i 1; o7 ═ i1^ i2^ i5^ i6^ i 8; o8 ═ i3^ i2^ i4^ i5^ i 7.
For example, if the originally encoded data i1-i7 is 11110000, the encoded data is calculated to be 00110101 according to the above logical expression.
When decoding, the original data is input into the logic circuit from the input pin, and the decoded data is output from the output pin. Let the input pins during decoding be defined as o1-o7, and the output pins be defined as x1-x7, then the logic expression during decoding is: the power supply comprises a power supply, a power supply.
In the above example, when the original data is 00110101 in decoding, x1 is 1, and x2 is 1; x3 ═ 1; x4 ═ 1, x5 ═ 0; x6 ═ 0; x7 ═ 0; x8 ═ 0; therefore, the decoded data is 11110000, which is the same as the data before encoding. Therefore, the same circuit can be used for achieving the same effect of encoding and decoding.
Illustratively, if the original data is 11110000, and there are even numbers of "1" and even numbers of "0", the encoded data is 00110101 after passing through the basic codec unit.
If the first bit becomes "0" when flipped, the original data becomes 01110000, and since the first bit is connected to input pin i1 and i1 is associated with output pins o6, o3, o4, o5, and o7, the third, fourth, fifth, sixth, and seventh bits of the encoded data are all flipped, and thus the encoded data becomes 00001011.
In the above example, there are even numbers of 1's in both the original data before the inversion and the encoded data; after the inversion occurs, there are odd numbers of "1" in the original data, and the encoded data also has odd numbers of "1". Therefore, the logic circuit of the application does not change the parity of the data, and is beneficial to the parity check of the data; moreover, the inversion of one bit in the original data can cause the inversion of five bits in the encoded data, so that the receiver can more easily check the data error before decoding.
As shown in fig. 2, a circuit connection structure diagram of a byte codec provided in this embodiment is shown, wherein the 7 th to 0 th bits of Data to be encoded are respectively connected to the i1-i8 input pins of the basic codec unit, the o1-o8 output pins of the basic codec unit are respectively connected to the D terminals of 8D flip-flops, clock signals are respectively connected to the clock terminals of the 8D flip-flops, and the 0 th to 7 th bits of Data EncData after encoding can be obtained by outputting the Data at the Q terminals of the 8D flip-flops, thereby completing encoding.
As another embodiment, the 7-0 bits of the encoded Data may be connected to the i1-i8 input pins of the basic codec unit in a disorderly order, and the connection order may be adjusted according to the respective requirements of those skilled in the art.
Illustratively, if the encoded Data is input in the order of 0, 1, 2, 3, 5, 4, 7, 6, 8 bits, the encoded Data EncData is also output in the order of 0, 1, 2, 3, 5, 4, 7, 6, 8 bits.
Specifically, the encoding and decoding circuits of this embodiment are the same circuit, the encoded Data completed by the encoded Data end can be transmitted to the decoding Data end through wireless communication, the decoding Data end uses the same circuit to decode, that is, the 7 th to 0 th bits of the Data to be decoded are respectively connected to the i1-i8 input pins of the basic encoding and decoding unit, the o1-o8 output pins of the basic encoding and decoding unit are respectively connected to the D ends of 8D flip-flops, the clock signals are respectively connected to the clock ends of the 8D flip-flops, and the 0 th to 7 th bits of the Data EncData after decoding can be obtained and output by the Q ends of the 8D flip-flops, so as to complete decoding.
Specifically, each coding and decoding unit completes coding and decoding of 8-bit binary data, if the data to be coded and decoded is 16-bit binary data, 2 basic coding and decoding units are required to be spliced, and if the data to be coded and decoded is 32-bit binary data, 4 basic coding and decoding units are required to be spliced, and so on.
As shown in fig. 3, a schematic diagram of a connection structure of two byte encoders provided by the present application includes two basic codec units, where the two codec units exist independently and there is no circuit connection relationship between the two codec units.
In summary, the present application further provides a multi-byte encoding circuit, which includes a plurality of basic encoding and decoding units, and the number of the basic encoding and decoding units is set according to the actual situation.
The beneficial effects of the embodiment of the application are as follows:
(1) the basic coding and decoding unit and the basic coding and decoding unit in the coder and decoder can enable coding and decoding to use the same circuit, and complexity and manufacturing cost of circuit design are reduced.
(2) The basic coding and decoding unit and the coder and decoder provided by the application can not change the parity of data if bit reversal occurs during digital communication, so that a receiving party can directly carry out parity check on the coded data, and directly abandons the data when the check fails, thereby avoiding the waste of computing resources caused by decoding invalid data with bit reversal.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application. It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (2)
1. A basic coding and decoding unit is characterized by comprising two same logic circuits which are used for coding and decoding respectively; the logic circuit comprises input pins and output pins with the same quantity and a plurality of exclusive-OR gates;
wherein the logic circuit comprises eight input pins and eight output pins, each of the input pins being associated with five of the output pins through the exclusive-or gate;
the logic circuit comprises fourteen exclusive-or gates, fourteen exclusive-or gates are defined as an exclusive-or gate 1, an exclusive-or gate 2, an exclusive-or gate 3, an exclusive-or gate 4, an exclusive-or gate 5, an exclusive-or gate 6, an exclusive-or gate A, an exclusive-or gate B, an exclusive-or gate C, an exclusive-or gate D, an exclusive-or gate E, an exclusive-or gate F, an exclusive-or gate G and an exclusive-or gate H, 8 input pins are defined as i1, i2, i3, i4, i5, i6, i7 and i8, 8 output pins are defined as o1, o2, o3, o4, o5, o6, o7 and o8, wherein the input pin i1 is connected with an input end of the exclusive-or gate F, and an output end of the exclusive-or gate F is an output pin o 6; the input pin i1 is connected to an input terminal of an exclusive or gate 1, an output terminal of the exclusive or gate 1 is connected to an input terminal of an exclusive or gate 6, an output terminal of the exclusive or gate 6 is connected to an input terminal of an exclusive or gate C, D, E, G, and output terminals of the exclusive or gate C, D, E, G are output pins o3, o4, o5 and o7, respectively;
the input pin i2 is connected with the input end of an exclusive-or gate H, and the output end of the exclusive-or gate H is an output pin o 8;
the input pin i2 is connected with the input end of the exclusive-or gate 1;
the input pin i3 is connected with the input end of the exclusive-or gate D;
the input pin i3 is connected with an input end of an exclusive-or gate 2, an output end of the exclusive-or gate 2 is connected with an input end of an exclusive-or gate 5, an output end of the exclusive-or gate 5 is connected with input ends of an exclusive-or gate A, an exclusive-or gate B, an exclusive-or gate F and an exclusive-or gate H, and output ends of the exclusive-or gate A, the exclusive-or gate B, the exclusive-or gate F and the exclusive-or gate H are output pins o1, o2, o6 and o8 respectively;
the input end of the input pin i4 exclusive-or gate C is connected;
the input pin i4 is connected with the input end of the exclusive-or gate 2;
the input pin i5 is connected with the input end of the exclusive-or gate G;
the input pin i5 is connected with the input end of an exclusive-or gate 3, and the output end of the exclusive-or gate 3 is connected with the input end of an exclusive-or gate 5;
the input pin i6 is connected with the input end of the exclusive-or gate A;
the input pin i6 is connected with the input end of an exclusive-or gate 4, and the output end of the exclusive-or gate 4 is connected with the input end of an exclusive-or gate 6;
the input pin i7 is connected with the input end of the exclusive-or gate E;
the input pin i7 is connected with the input end of the exclusive-or gate 3;
the input pin i8 is connected with the input end of the exclusive-or gate B;
the input pin i8 is connected to the input of the xor gate 4.
2. A codec comprising a plurality of basic codec units according to claim 1 and a plurality of flip-flops, wherein the number of flip-flops is the same as the number of output pins of the basic codec units; each output pin is connected with the D end of the corresponding trigger.
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| CN104601179A (en) * | 2014-12-12 | 2015-05-06 | 北京麓柏科技有限公司 | Erasure code coding circuit and decoding circuit and coding and encoding circuit of storage system |
| US9501590B1 (en) * | 2015-03-04 | 2016-11-22 | Cadence Design Systems, Inc. | Systems and methods for testing integrated circuit designs |
| CN108964670B (en) * | 2018-07-25 | 2020-07-24 | 北京翼鸥教育科技有限公司 | Basic coding and decoding unit and coder-decoder |
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