CN1255952C - Manchester coder and decoder - Google Patents
Manchester coder and decoder Download PDFInfo
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- CN1255952C CN1255952C CN 03132569 CN03132569A CN1255952C CN 1255952 C CN1255952 C CN 1255952C CN 03132569 CN03132569 CN 03132569 CN 03132569 A CN03132569 A CN 03132569A CN 1255952 C CN1255952 C CN 1255952C
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Abstract
The present invention discloses a Manchester encoder and a decoder which can be used for devices, such as an industrial control bus, a computer interface, etc. The present invention is composed of an encoder (1) and a decoder (2), wherein data signals and clock signals are integrated to output data signals of a single Manchester encoding form by the encoder (1); the output data signals are input into the decoder (2) by a data line (3), and then, the clock signals for synchronizing the receiving end and the sending end of a data transmission system are decomposed. The present invention is only composed of a simple circuit and does not need a phase-locked loop. The present invention has the advantages of simple and reliable structure, low cost and easy realization and use.
Description
Technical field: the present invention relates to a kind of Manchester encoder, it can be used for devices such as industrial-controlled general line, computer interface.
Background technology: the communication task of industrial-controlled general line, computer network system is to transmit the information of data or datumization.These data are represented with discrete Binary Zero, the mode of 1 sequence usually.Code element be transmit the base unit of data.What transmitted in bus and network service mostly is dual code greatly, and it each can only be got one in 1 or 0 two state.Manchester (being Manchester) coding is a kind of baseband signal commonly used coding.It has inherent clock information, thereby each system on the network is kept synchronously.In Manchester's code, the time is divided into equally spaced segment.Wherein every segment is represented the one digit number certificate.Each short time itself is dimidiation again, and preceding half time period is for transmitted number the radix-minus-one complement that this time period transmits bit value, and what back half time period transmitted is bit value itself.As seen in a period of time, the total once variation of signal level of its intermediate point; Therefore this yard carries the synchronizing information of signal transmission and do not need to transmit in addition synchronizing signal.The basic function of Manchester encoder is the outputting data signals that the data-signal of CPU output and clock signal are integrated into single Manchester coding form, the basic function of Manchester decoder is that the input data signal with the Manchester coding form is decomposed into data-signal and clock signal, so that CPU or processing units such as DSP, MCU read.The Manchester coding is widely used, and has to be integrated with Manchester encoder and Manchester decoder in the multiple network Communication Control chip, and special Manchester Code And Decode chip is also arranged.The common feature of these chips is that Code And Decode is realized based on PLL (phase-locked loop), the circuit complexity.
Summary of the invention:, provide a kind of circuit structure simple encoder in order to overcome the defective of existing Manchester encoder circuit complexity.The present invention is achieved by following proposal: a kind of Manchester encoder, it is made up of encoder 1 and decoder 2, encoder 1 is integrated into data-signal and clock signal the outputting data signals of single Manchester coding form, the transmitting-receiving two-end clock signal synchronous that this outputting data signals decomposes the data communication system of sening as an envoy to by data wire 3 input decoders 2 backs, encoder 1 is by inverter K1, variable connector U1, XOR gate K2, trigger (the D1 of three " D " types, D2 and D3) and power supply+V composition, data-in port SPI connects the pin A2 of variable connector U1 and the input of inverter K1, the output of inverter K1 connects the pin A1 of variable connector U1, input end of clock mouth SPCLK connects the input of XOR gate K2 and the input D of trigger D1, the control end of trigger D1 (PRN and CLRN) connects the control end (PRN and CLRN) of trigger D2, the control end of trigger D3 (PRN and CLRN) and power supply+V, the input end of clock of trigger D1 connects high frequency clock port CLK, the input end of clock of the input end of clock of trigger D2 and trigger D3, the output Q of trigger D1 connects the input D of trigger D2, the output Q of trigger D2 connects the input D of trigger D3 and the pin WRSL of variable connector U1, the output Q of trigger D3 connects another input of XOR gate K2, the pin CLKN of the output connected with multiple switch U1 of XOR gate K2, the pin QA of variable connector U1 connects encoder output MC-T, decoder 2 is by the trigger (T1-T6) of six T-shapes, inverter K3, inverter K4, or door K5, trigger (the D4 of two " D " types, D5) and power supply+V forms, decoder input MC-N connects encoder output MC-T by data wire 3, decoder input MC-N connects the input of inverter K4 and the input end of clock of trigger T1, the control end PRN of trigger T1 connects input T and the power supply+V of trigger T1, the output Q company of trigger T1 or the input of door K5, the control end CLRN of trigger T1 connects the control end CLRN of trigger T2 and the output Q of trigger D5, the output of inverter K4 connects the input end of clock of trigger T2, the control end PRN of trigger T2 connects input T and the power supply+V of trigger T2, the output Q connection of trigger T2 or another input of door K5, or the output of door K5 connects the input D of trigger D4, two control ends (PRN and CLRN) of trigger D4 link together and are connected with power supply+V, the output Q of trigger D4 connects decoder output SPI-N, the control end CLRN of trigger T3, the control end CLRN of trigger T4, the control end PRN of trigger T5 and the control end PRN of trigger T6, the input end of clock of trigger D4 connects high frequency clock input CLK1, the input end of clock of the input of inverter K3 and trigger T3, the input T of trigger T3 is connected input T and the control end PRN of trigger T4 with control end PRN, the input T of trigger T5 and control end CLRN, the input T of trigger T6 and control end CLRN, power supply+V, the output Q of trigger T3 connects the input end of clock of trigger T4, the output Q of trigger T4 connects the input end of clock of trigger T5, the output Q of trigger T5 connects the input end of clock of trigger T6, the output Q of trigger T6 connects the input D of trigger D5, the input end of clock of trigger D5 connects the output of inverter K3, the control end PRN of trigger D5 connects power supply+V, and the control end CLRN of trigger D5 connects initializing signal input INIT.The operation principle of encoder 1 is: data-signal and inversion signal thereof are delivered to two inputs of U1 respectively, the output of arbitrary moment encoder 1 all is in these two input signals, the selection of two input signals is realized by the clock signal of SPCLK end, for eliminating the asynchronous influence of SPI end to encoder performance with SPCLK end signal edge, be used to export 2 clk cycles of SPCLK end signal delay (being realized by D1 and D2) of selection, the SPCLK end signal that is used for the synchronised clock of U1 postpones 3 clk cycles (being realized by D1, D2 and D3).Decoder 2 operation principles are shown in table 1 " Manchester decoder sequential ".The trailing edge of INIT end signal is initialized as a definite state with the Manchester decoder, and IMT end signal rising edge subsequently and CLK1 end signal trailing edge are in the Manchester decoder and wait for the state that receives the input data; Shown in the step 1 to 4 in the table 1.
When MC-N end input signal changed, the Manchester decoder press shown in the step 5 to 14 in the table 1 and is changed continuously, has realized the Manchester decoding, and the SPI-N end output signal that obtains is and MC-N holds the input signal clock signal synchronous.When one-period was finished, the Manchester decoder automatically restored to the state that receives the input data of waiting for, prepared to accept the MC-N end and changed next time.
What the step 5 to 14 in the table 1 provided is that MC-N holds the sequential when taking place to change from high to low.When MC-N holds generation to change from low to high, only need T1 in the table 1 and T2 two row exchanges can be changed sequential accordingly.
Table 1 Manchester decoder sequential
The present invention only is made up of better simply circuit, does not need phase-locked loop, has simple and reliable, with low cost and is easy to the advantage that realizes and use.
Description of drawings: Fig. 1 is a structured flowchart of the present invention, and Fig. 2 is the electrical block diagram of encoder 1 in the embodiment, and Fig. 3 is the electrical block diagram of decoder 2 in the execution mode.
Embodiment: specify present embodiment below in conjunction with Fig. 1 to Fig. 3.Present embodiment is made up of encoder 1 and decoder 2, encoder 1 is integrated into data-signal and clock signal the outputting data signals of single Manchester coding form, the transmitting-receiving two-end clock signal synchronous that this outputting data signals decomposes the data communication system of sening as an envoy to by data wire 3 input decoders 2 backs, encoder 1 is by inverter K1, variable connector U1, XOR gate K2, trigger (the D1 of three " D " types, D2 and D3) and power supply+V composition, data-in port SPI connects the pin A2 of variable connector U1 and the input of inverter K1, the output of inverter K1 connects the pin A1 of variable connector U1, input end of clock mouth SPCLK connects the input of XOR gate K2 and the input D of trigger D1, the control end of trigger D1 (PRN and CLRN) connects the control end (PRN and CLRN) of trigger D2, the control end of trigger D3 (PRN and CLRN) and power supply+V, the input end of clock of trigger D1 connects high frequency clock port CLK, the input end of clock of the input end of clock of trigger D2 and trigger D3, the output Q of trigger D1 connects the input D of trigger D2, the output Q of trigger D2 connects the input D of trigger D3 and the pin WRSL of variable connector U1, the output Q of trigger D3 connects another input of XOR gate K2, the pin CLKN of the output connected with multiple switch U1 of XOR gate K2, the pin QA of variable connector U1 connects encoder output MC-T, decoder 2 is by the trigger (T1-T6) of six T-shapes, inverter K3, inverter K4, or door K5, trigger (the D4 of two " D " types, D5) and power supply+V forms, decoder input MC-N connects encoder output MC-T by data wire 3, decoder input MC-N connects the input of inverter K4 and the input end of clock of trigger T1, the control end PRN of trigger T1 connects input T and the power supply+V of trigger T1, the output Q company of trigger T1 or the input of door K5, the control end CLRN of trigger T1 connects the control end CLRN of trigger T2 and the output Q of trigger D5, the output of inverter K4 connects the input end of clock of trigger T2, the control end PRN of trigger T2 connects input T and the power supply+V of trigger T2, the output Q connection of trigger T2 or another input of door K5, or the output of door K5 connects the input D of trigger D4, two control ends (PRN and CLRN) of trigger D4 link together and are connected with power supply+V, the output Q of trigger D4 connects decoder output SPI-N, the control end CLRN of trigger T3, the control end CLRN of trigger T4, the control end PRN of trigger T5 and the control end PRN of trigger T6, the input end of clock of trigger D4 connects high frequency clock input CLK1, the input end of clock of the input of inverter K3 and trigger T3, the input T of trigger T3 is connected input T and the control end PRN of trigger T4 with control end PRN, the input T of trigger T5 and control end CLRN, the input T of trigger T6 and control end CLRN, power supply+V, the output Q of trigger T3 connects the input end of clock of trigger T4, the output Q of trigger T4 connects the input end of clock of trigger T5, the output Q of trigger T5 connects the input end of clock of trigger T6, the output Q of trigger T6 connects the input D of trigger D5, the input end of clock of trigger D5 connects the output of inverter K3, the control end PRN of trigger D5 connects power supply+V, and the control end CLRN of trigger D5 connects initializing signal input IMT.The model of variable connector U1 is 74298, the clock signal of input end of clock SPCLK input 4MHZ, the clock signal of high frequency clock port CLK and CLK1 input 40MHZ.
Claims (1)
1, a kind of Manchester encoder, it is made up of encoder (1) and decoder (2), encoder (1) is integrated into the outputting data signals of single Manchester coding form with data-signal and clock signal, the transmitting-receiving two-end clock signal synchronous that this outputting data signals decomposes the data communication system of sening as an envoy to by data wire (3) input decoder (2) back; It is characterized in that encoder (1) is by inverter K1, variable connector (U1), XOR gate K2, trigger (the D1 of three " D " types, D2 and D3) and power supply (+V) form, data-in port (SPI) connects the pin A2 of variable connector (U1) and the input of inverter K1, the output of inverter K1 connects the pin A1 of variable connector (U1), input end of clock mouth (SPCLK) connects the input of XOR gate K2 and the input D of trigger D1, the control end PRN of trigger D1 and control end CLRN connect control end PRN and the control end CLRN of trigger D2, the control end PRN of trigger D3 and control end CLRN and power supply (+V), the input end of clock of trigger D1 connects high frequency clock port (CLK), the input end of clock of the input end of clock of trigger D2 and trigger D3, the output Q of trigger D1 connects the input D of trigger D2, the output Q of trigger D2 connects the input D of trigger D3 and the pin WRSL of variable connector (U1), the output Q of trigger D3 connects another input of XOR gate K2, the pin CLKN of the output connected with multiple switch (U1) of XOR gate K2, the pin QA of variable connector (U1) connects encoder output (MC-T); Decoder (2) is by the trigger (T1-T6) of six T-shapes, inverter K3, inverter K4, or door K5, trigger (the D4 of two " D " types, D5) and power supply (+V) form, decoder input (MC-N) connects encoder output (MC-T) by data wire (3), decoder input (MC-N) connects the input of inverter K4 and the input end of clock of trigger T1, the control end PRN of trigger T1 connect the input T of trigger T1 and power supply (+V), the output Q company of trigger T1 or the input of door K5, the control end CLRN of trigger T1 connects the control end CLRN of trigger T2 and the output Q of trigger D5, the output of inverter K4 connects the input end of clock of trigger T2, the input T of the control end PRN connection trigger T2 of trigger T2 and power supply (+V), the output Q connection of trigger T2 or another input of door K5, or the output of door K5 connects the input D of trigger D4, the control end PRN of trigger D4 link together with control end CLRN and with power supply (+V) be connected, the output Q of trigger D4 connects decoder output (SPI-N), the control end CLRN of trigger T3, the control end CLRN of trigger T4, the control end PRN of trigger T5 and the control end PRN of trigger T6, the input end of clock of trigger D4 connects high frequency clock input (CLK1), the input end of clock of the input of inverter K3 and trigger T3, the input T of trigger T3 is connected input T and the control end PRN of trigger T4 with control end PRN, the input T of trigger T5 and control end CLRN, the input T of trigger T6 and control end CLRN, power supply (+V), the output Q of trigger T3 connects the input end of clock of trigger T4, the output Q of trigger T4 connects the input end of clock of trigger T5, the output Q of trigger T5 connects the input end of clock of trigger T6, the output Q of trigger T6 connects the input D of trigger D5, the input end of clock of trigger D5 connects the output of inverter K3, the control end PRN of trigger D5 connect power supply (+V), the control end CLRN of trigger D5 connects initializing signal input (INIT).
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| Application Number | Priority Date | Filing Date | Title |
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| CN 03132569 CN1255952C (en) | 2003-08-21 | 2003-08-21 | Manchester coder and decoder |
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| CN 03132569 CN1255952C (en) | 2003-08-21 | 2003-08-21 | Manchester coder and decoder |
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| CN1255952C true CN1255952C (en) | 2006-05-10 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100376084C (en) * | 2006-05-19 | 2008-03-19 | 宁波中科集成电路设计中心有限公司 | Manchester code decoding method and application apparatus therefor |
| CN102256118B (en) * | 2011-08-15 | 2014-03-26 | 成都市广达电子电讯技术开发有限公司 | Synchronous circuit and method for TS (Telecommunication Service) code streams |
| CN104978291B (en) * | 2014-04-09 | 2019-10-22 | Nxp股份有限公司 | One-wire interface Bus Transmit-receive System system and I2C single-wire communication method based on I2C bus protocol |
| CN105281776B (en) * | 2014-07-08 | 2019-03-05 | 南车株洲电力机车研究所有限公司 | It is a kind of can error correction manchester decoder devices and methods therefor |
| CN108847849B (en) * | 2018-07-25 | 2021-06-01 | 北京隆普智能科技有限公司 | Basic coding and decoding unit and coder-decoder |
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Effective date of registration: 20190801 Address after: 150000 Heilongjiang Province, Harbin City Economic Development Zone haping Road District Dalian road and Xingkai road junction Patentee after: Harbin University of Technology Robot Group Co., Ltd. Address before: 150001 Harbin, Nangang, West District, large straight street, No. 92 Patentee before: Harbin Institute of Technology |
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Granted publication date: 20060510 Termination date: 20190821 |