CN102256118B - Synchronous circuit and method for TS (Telecommunication Service) code streams - Google Patents
Synchronous circuit and method for TS (Telecommunication Service) code streams Download PDFInfo
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Abstract
The invention discloses a synchronous circuit and method for TS (Telecommunication Service) code streams and particularly relates to the field of broadcast television. The invention has the technical main points that the synchronous circuit comprises a TS code stream data latch circuit, a synchronous character detection circuit, a message synchronous detection circuit, a synchronous character separation circuit and a synchronous indicating signal shaping circuit, wherein the TS code stream data latch circuit is used for outputting the delayed TS code stream data; the synchronous character detection circuit is used for detecting synchronous bytes in the TS code streams; the message synchronous detection circuit is used for judging that the same position of multiple continuous messages in the TS code streams has the synchronous bytes; the synchronous character separation circuit is used for separating synchronous pulse after the TS code streams are synchronous; and the synchronous indicating signal shaping circuit is used for outputting the synchronous indicating signals of the TS code streams after the TS code streams are synchronous and indicating that the current TS code streams are the message with the bytes 188 or 204. The invention has the functions of self adaption, automatic resynchronization, message length detection and the like of the message with the bytes 188/204.
Description
Technical field
The present invention relates to television network broadcast digital signal transmission field, especially relate to message synchronous circuit and the method for transport stream (Transport Stream is designated hereinafter simply as TS code stream).
Background technology
At present, China is used the universal coding part 1 of GB/T17975.1 < < information technology moving image and sound information thereof: the TS flow transmission Digital Television defining in system > > standard and other data-signal.TS stream is widely used in Hybrid Fiber Coaxial (Hybrid Fiber-Coax Network, is designated hereinafter simply as hfc plant) and satellite digital TV network.The TS stream synchronous circuit that the present invention sets forth, for field of digital television transmission, completes the TS stream packet delimitative function to input, is the requisite basic circuit modules of equipment such as digital TV multiplexer, modulator, transcoder.
TS stream is comprised of message flow, and message length is the fixed length message of 188 bytes or 204 bytes, frame structure as shown in Figure 1: wherein, the value of sync byte is hexadecimal number 0x47, for the demarcation of message.Because this value also likely appears in message inside, therefore before processing message, equipment needs advanced line search, determine separation and the message length (188/204) of message.
Summary of the invention
The invention discloses the details that realizes of a kind of TS code stream synchronous circuit and method.The technical solution used in the present invention is such: a kind of TS code stream synchronous circuit, comprises that TS bit stream data latch cicuit, synchronization character testing circuit, message sync detection circuit, synchronization character split circuit and synchronous indicating signal form circuit;
TS bit stream data latch cicuit is for accepting TS bit stream data the TS bit stream data of output through postponing of 188 byte messages or 204 byte messages;
Synchronization character testing circuit is used for accepting the TS bit stream data of 188 byte messages or 204 byte messages, and detects the sync byte in described TS code stream;
Message sync detection circuit all detects sync byte, the TS code stream synchronous indicating signal of output 188 byte messages or 204 byte messages, described n >=8 for judging synchronization character testing circuit in the same position of TS code stream n continuous message;
Synchronization character split circuit, isolates lock-out pulse for realize TS code stream at message sync detection circuit synchronously;
Synchronous indicating signal forms circuit, at message sync detection circuit, realize TS code stream synchronous after output TS code stream synchronous indicating signal, and indication synchronous TS code stream be 188 byte messages or 204 byte messages.
Data useful signal forms circuit, for exporting useful signal or after realizing synchronously and when current TS code stream is front 188 byte of 204 byte messages, export useful signal when current TS code stream being 188 byte message.
Described TS bit stream data latch cicuit comprises the one 8 latch and the 28 latch; The input access TS code stream of the one 8 latch, the one 8 be latch, and output is connected with the input of the 28 latch, and the output of the 28 latch is the TS bit stream data output that passes through time delay.
Described synchronization character testing circuit comprises sync byte comparator, 3 latchs, the one 2 input or door, 2 not gates, 22 inputs and door, with mould 188 up-counters of asynchronous resetting and carry output, with mould 204 up-counters of asynchronous resetting and carry output;
The input access TS code stream of described sync byte comparator, output is connected to the first latch and the one 2 input or door simultaneously, the output of the first latch is connected with another input of the one 2 input or door, and the output of described the one 2 input or door is connected to the input of 2 described not gates simultaneously;
The output of the first not gate is connected with an output of door with the one 2 input, the one 2 input is connected with the carry signal output of described mould 188 up-counters with another input of door, and the one 2 input is connected with the input of the second latch with the output of door;
The output of the second latch is connected with the clear terminal of mould 188 up-counters, and the clear terminal of the second latch is connected with the carry signal output of mould 188 up-counters;
The output of the second not gate is connected with an output of door with the 22 input, and the 22 input is connected with the carry signal output of mould 204 up-counters with another input of door, and the 22 input is connected with the input of the 3rd latch with the output of door;
The output of the 3rd latch is connected with the clear terminal of mould 204 up-counters, and the clear terminal of the 3rd latch is connected with the carry signal output of mould 204 up-counters;
Mould 188 up-counters and mould 204 up-counters also have respectively enumeration data output.
Described message sync detection circuit comprises 8 bit shift register that 2 bands enable, 28 inputs and door;
The Enable Pin of described the first shift register is connected with the carry signal output of mould 188 up-counters, and its data input pin is connected with the output of the first latch, and 8 outputs correspondences of the first shift register are connected with the input of door with the one 8 input; The one 8 input is 188 byte message TS code stream synchronous indicating signal outputs with the output of door;
The Enable Pin of described the second shift register is connected with the carry signal output of mould 204 up-counters, and its data input pin is connected with the output of the first latch, and 8 outputs correspondences of the second shift register are connected with the input of door with the 28 input; The 28 input is 204 byte message TS code stream synchronous indicating signal outputs with the output of door.
Described synchronization character split circuit comprises 2 latchs, 22 inputs and Men Yuyi No. 4 selectors;
Described the 32 input is connected with the output of the first latch with an input of door, and another input is connected with the carry signal output of mould 188 up-counters; The 32 input is connected with the input of quad latch with the output of door;
Described the 42 input is connected with the output of the first latch with an input of door, and another input is connected with the carry signal output of mould 204 up-counters; The 42 input is connected with the input of the 5th latch with the output of door;
Two address gating signal inputs of described No. 4 selectors connect respectively the one 8 input and the output of door and the output of the 28 input and door; The second road signal input part of No. 4 selectors is connected with the output of described quad latch; The Third Road signal input part of No. 4 selectors is connected with the output of described the 5th latch; The output of No. 4 selectors is lock-out pulse output.
Described synchronous indicating signal forms circuit and comprises the 22 input or door, and the input of the 22 input or door connects respectively the output of the output of the one 8 input and door and the 28 input and door, described second or the output of door for synchronously completing indication output end;
Described the one 8 input is 188 byte message indication output end with the output of door;
Described the 28 input is 204 byte message indication output end with the output of door.
Described data useful signal forms circuit and comprises that unsigned number is less than 203 comparators, unsigned number and is more than or equal to 187 comparators, 2 latchs and 3 input nand gates;
The enumeration data output of mould 204 up-counters is connected with the input that unsigned number is less than 203 comparators, and the output that unsigned number is less than 203 comparators is connected to 3 input nand gates by the 6th latch;
The enumeration data output of mould 188 up-counters is connected with the input that unsigned number is more than or equal to 187 comparators, and the output that unsigned number is more than or equal to 187 comparators is connected to 3 input nand gates by the 7th latch;
The 3rd input of described 3 input nand gates is connected with the output of door with the 28 input; The output of 3 input nand gates is the effective indication output end of data.
A TS code stream synchronous method, comprising:
Step 1: whether the TS stream byte that detects input equals sync byte, when equaling sync byte, forwards step 2 to, and this time point meter is made T0; When being not equal to sync byte, repeated execution of steps 1;
Step 2: judge successively whether TS stream byte corresponding to the n * L work clock constantly starting from T0 equals sync byte, n is integer, and 0<n<8, L is TS code stream message byte number: if equal sync byte, repeated execution of steps 2; If be not equal to sync byte, return to step 1;
When 8th * L TS stream byte corresponding to work clock being detected, equal sync byte, enter step 3;
Step 3: successively judge whether the n * L TS stream byte corresponding to work clock equals sync byte, n is integer, and n>8: be not equal to sync byte if the TS stream byte that the n * L work clock is corresponding detected, think synchronization loss, get back to step 1.
Described TS code stream message byte number L is 188 or 204.
In sum, owing to having adopted technique scheme, the invention has the beneficial effects as follows:
Possess 188/204 byte message self adaptation, automatically heavy synchronous, message length detection, valid data detection, synchronization character position probing, synchronously complete deixis.
Accompanying drawing explanation
Examples of the present invention will be described by way of reference to the accompanying drawings, wherein:
Fig. 1 is that length is the frame structure of the fixed length message of 188 or 204 bytes;
Fig. 2 is the input/output interface schematic diagram of synchronous circuit in the present invention;
Fig. 3 is synchronous circuit output timing diagram in the present invention;
Fig. 4 is the circuit diagram of synchronous circuit embodiment in the present invention;
Fig. 5 shows is the TS bit stream data latch cicuit in the circuit diagram of the embodiment of synchronous circuit shown in Fig. 4;
Fig. 6 shows is the synchronization character testing circuit in the circuit diagram of the embodiment of synchronous circuit shown in Fig. 4;
Fig. 7 shows is the message sync detection circuit in the circuit diagram of the embodiment of synchronous circuit shown in Fig. 4;
Fig. 8 shows is the synchronization character split circuit in the circuit diagram of the embodiment of synchronous circuit shown in Fig. 4;
Fig. 9 shows is that data useful signal in the circuit diagram of the embodiment of synchronous circuit shown in Fig. 4 forms circuit;
Figure 10 shows is that synchronous indicating signal in the circuit diagram of the embodiment of synchronous circuit shown in Fig. 4 forms circuit;
Figure 11 is synchronous method flow chart in the present invention.
Embodiment
Disclosed all features in this specification, or the step in disclosed all methods or process, except mutually exclusive feature and/or step, all can combine by any way.
Disclosed arbitrary feature in this specification (comprising any accessory claim, summary and accompanying drawing), unless narration especially all can be replaced by other equivalences or the alternative features with similar object.That is,, unless narration especially, each feature is an example in a series of equivalences or similar characteristics.
Synchronous circuit in the present invention comprises that TS bit stream data latch cicuit, synchronization character testing circuit, message sync detection circuit, data useful signal form circuit and synchronous indicating signal forms circuit.
The circuit diagram of an embodiment of synchronous circuit in the present invention as shown in Figure 4.
TS bit stream data latch cicuit comprises that 8 latch p1 and 8 are latch p2 as described in Figure 5; The input access TS code stream of 8 latch p1, the output of 8 latch p1 is connected with the input of 8 latch p2, and the output of 8 latch p2 is the TS bit stream data output through time delay.
As described in Figure 6 synchronization character testing circuit comprise sync byte comparator p3,3 latchs, 2 inputs or door, 2 not gates, 22 inputs and door, with the mould 188 up-counter p11 of asynchronous resetting and carry output and mould 204 up-counter p20 with asynchronous resetting and carry output.
The input access TS code stream of described sync byte comparator p3, output is connected to latch p4 and 2 inputs or door p8 simultaneously, the output of latch p4 is connected with another input of 2 inputs or door p8, and the output of described 2 inputs or door p8 is connected to 2 not gate p7, p17 simultaneously.
The output of not gate p7 is connected with an input of door p6 with 2 inputs, and 2 inputs are connected with the carry signal output of described mould 188 up-counter p11 with another input of door p6, and 2 inputs are connected with the input of latch p5 with the output of door p6.
The output of latch p5 is connected with the clear terminal of mould 188 up-counter p11, and the clear terminal of latch p5 is connected with the carry signal output of mould 188 up-counter p11.
The output of not gate p17 is connected with an input of door p16 with 2 inputs, and 2 inputs are connected with the carry signal output of mould 204 up-counter p20 with another input of door p16, and 2 inputs are connected with the input of latch p15 with the output of door p16.
The output of latch p15 is connected with the clear terminal of mould 204 up-counter p20, and the clear terminal of latch p15 is connected with the carry signal output of mould 204 up-counter p20.
The operation principle of synchronization character testing circuit is: P3 is by DI[7..0] compare with constant 0x47, if equated, the aeb output high level of P3.DI[7..0 detected] on occurred that this event of 0x47 is latched device P5 and P15 latchs, the output of latch can cause the asynchronous resetting end of counter P11 and P20 to occur low level, counter starts to count from zero.P11 is mould 188 counters with carry output, counting down at 188 o'clock, at rising edge clock P11 carry output high level, remove the event that the last time of recording in P5 detects 0x47, at the trailing edge of clock, again detect DI[7..0] on whether there is synchronization character 0x47.P20 is mould 204 counters with carry output, counting down at 204 o'clock, at rising edge clock P20 carry output high level, remove the event that the last time of recording in P15 detects 0x47, at the trailing edge of clock, again detect DI[7..0] on whether there is synchronization character 0x47.
As Fig. 7, described message sync detection circuit comprises 22 inputs and door, 2 latchs, 28 bit shift register, 28 inputs and door that band enables.
Described 2 inputs are connected with the output of latch p4 with an input of door p9, and another input is connected with the carry signal output of mould 188 up-counter p11; 2 inputs are connected with the input of latch p10 with the output of door p9.
The Enable Pin of described shift register p12 is connected with the carry signal output of mould 188 up-counter p11, and its data input pin is connected with the output of latch p4,8 outputs of shift register p12 and input corresponding be connected of 8 inputs with a p13.
Described 2 inputs are connected with the output of latch p4 with an input of door p18, and another input is connected with the carry signal output of mould 204 up-counter p20; 2 inputs are connected with the input of latch p19 with the output of door p18.
The Enable Pin of described shift register p21 is connected with the carry signal output of mould 204 up-counter p20, and its data input pin is connected with the output of latch p4,8 outputs of shift register p21 and input corresponding be connected of 8 inputs with a p22.
The operation principle of message sync detection circuit is: the output that P4 is received in the shiftin input of P12 and P21.P4 is d type flip flop, at the rising edge of clock, latchs P3(0x47 unsigned number comparator) Output rusults.
The enable signal of P12 is received P11(mould 188 counters) carry output, P11 starts counting after P4 detects synchronization character 0x47, for playing the 187 carry digit cout of byte place backward and will uprise 0x47 being detected.The enable of P12 becomes effectively, and the synchronization character comparative result that current P4 is latched is saved in shift register.When the output of P4 is continuous, be all for 8 times effective, show to be consecutively detected synchronization character 0x47 at 188 byte boundary places, think that synchronous circuit has been synchronized to the TS stream that message length is 188 bytes, 188 byte message TS code stream synchronous indicating signal SYNC_SEL0 outputs effectively.
The enable signal of P21 is received P20(mould 204 counters) carry output, P20 starts counting after P4 detects synchronization character 0x47, for playing the 203 carry digit cout of byte place backward and will uprise 0x47 being detected.The enable of P21 becomes effectively, and the synchronization character comparative result that current P4 is latched is saved in shift register.When the output of P4 is continuous, be all for 8 times effective, show to be consecutively detected synchronization character 0x47 at 204 byte boundary places, think that synchronous circuit has been synchronized to the TS stream that message length is 204 bytes, 204 byte message TS code stream synchronous indicating signal SYNC_SEL1 outputs effectively.
As Fig. 8, synchronization character split circuit is for isolate lock-out pulse after being synchronized to 188 or 204 byte TS streams.This function is comprised of with door P18 with door P9,2 inputs Port Multiplier P14, d type flip flop P10, d type flip flop P19,2 inputs.
After being synchronized to certain (188/204) code stream, SYNC_SEL[1..0] be output as the TS stream that 0x1(is synchronized to 188 bytes) or 0x2(be synchronized to the TS stream of 204 bytes).When not synchronous, the selecting side of Port Multiplier is input as 0x0, and the output of DSYNC lock-out pulse is invalid.
After being synchronized to the TS stream of 188 bytes, Port Multiplier P14 selects data1 as output.The input of data1 is the output of P10, is the P9 Output rusults that clock trailing edge is latched into d type flip flop P10.2 inputs are P11(mould 188 counters with door P9 input) carry output, another input is the Output rusults of synchronization character comparator.If there is synchronization character 0x47 at 188 byte boundary places, Port Multiplier P14 exports the lock-out pulse of a clock width.
After being synchronized to the TS stream of 204 bytes, Port Multiplier P14 selects data2 as output.The input of data2 is the output of P19, is 18 Output rusults that clock trailing edge is latched into d type flip flop P19.2 inputs are P21(mould 204 counters with door P18 input) carry output, another input is the Output rusults of synchronization character comparator.If there is synchronization character 0x47 at 204 byte boundary places, Port Multiplier P14 exports the lock-out pulse of a clock width.
As Fig. 9, it is to establish in order to facilitate the processing of subsequent conditioning circuit that described data useful signal forms circuit, can be used for removing the slack byte of message, comprise that unsigned number is less than 203 comparator p24, unsigned number and is more than or equal to 187 comparator p28,2 latchs and 3 input nand gates.
The enumeration data output of mould 204 up-counter p20 is connected with the input that unsigned number is less than 203 comparator p24, and the output that unsigned number is less than 203 comparator p24 is connected to 3 input nand gate p26 by latch p25.
The enumeration data output of mould 188 up-counter p11 is connected with the input that unsigned number is more than or equal to 187 comparator p28, and the output that unsigned number is more than or equal to 187 comparator p28 is connected to 3 input nand gate p26 by latch p29.
The 3rd input of described 3 input nand gate p26 is connected with the output of door p22 with 8 inputs; The output of 3 input nand gate p26 is the effective indication output end of data.
The operation principle that data useful signal forms circuit is: in the TS of 188 bytes stream, DV signal is continuously effective, and in the TS of 204 bytes stream, DV signal after 188 bytes just in invalid.
Data useful signal only need to just come into force in the message of 204 bytes, and therefore three NAND gate P26 have an input to receive 204 byte message synchronous indicating signal SYNC_SEL1, when this invalidating signal, and DV signal output continuously effective.
After being synchronized to the TS of 204 bytes, SYNC_SEL1 is effective, and other two inputs are depended in the output of DV.P25 and P29 are d type flip flops, for latched comparator P24(203 unsigned number, " are less than " comparator) and P28(187 unsigned number " be more than or equal to " comparator) output.In front 188 bytes of TS message, the input value that the input value of P28 is less than 187, P24 is less than 203, P29 and is output as effectively, and P25 is output as invalid, and DV is output as effectively.In the 189th to 204 bytes of TS message, P29 is output as effectively, and P25 is output as effectively, and DV is output as invalid.
As Figure 10, synchronous indicating signal is by SYNC_SEL0 and SYNC_SEL1 phase or form, and SYNC_SEL0 and SYNC_SEL1 indicate respectively TS stream to be comprised of 188 byte messages or 204 byte messages.
Fig. 2 is the input/output interface schematic diagram of synchronous circuit in the present invention, and synchronous circuit offers outside interface signal and is defined as follows:
Input TS flow data (DI[7..0]): the input of TS flow data, these data are synchronized to DI_CLK signal.
Input TS stream clock (DI_CLK): TS flows input clock.
Output TS flow data (DO[7..0]): the output of TS flow data, these data are synchronized to DO_CLK signal.
Output TS stream clock (DO_CLK): TS flows output clock, and this signal is the another name of DI_CLK.
Sync byte indication (DSYNC): export low when code stream is not synchronous.After code stream is synchronous, as DO[7..0] export while there is sync byte on line high.
Data are effectively indicated (DV): when code stream is not synchronous, export low.After code stream is synchronous, normal high in 188 byte message situations, in 204 byte message situations, front 188 byte outputs are high, and rear 16 byte outputs are low.
Synchronously complete indication (SYNC): when code stream is not synchronous, export low.After code stream is synchronous, be output as height, represent synchronously successful.
188 byte message indications (L188): export low when code stream is not synchronous.After code stream is synchronous, if incoming message is that 188 byte long outputs are high, otherwise be low.
204 byte message indications (L204): export low when code stream is not synchronous.After code stream is synchronous, if incoming message is that 204 byte long outputs are high, otherwise be low.The sequential chart of each output signal is shown in Fig. 3.
As Figure 11, in the present invention, synchronous method is:
Step 1: whether the TS stream byte that detects input equals sync byte 0x47, when equaling 0x47, forwards step 2 to, and this time point meter is made T0; When being not equal to 0x47, repeated execution of steps 1;
Step 2: judge successively whether n * 188 or 204 TS stream bytes corresponding to work clock that constantly start from T0 equal 0x47, n is integer, and 0<n<8,188 or 204 is TS code stream message byte number: if equal 0x47, repeated execution of steps 2; If be not equal to 0x47, return to step 1;
When 8th * 188 or 204 TS stream bytes corresponding to work clock being detected, equal 0x47, enter step 3;
Step 3: successively judge whether n * 188 or 204 TS stream bytes corresponding to work clock equal 0x47, n is integer, and n>8: if n * 188 detected or TS stream bytes corresponding to 204 work clocks are not equal to 0x47, think synchronization loss, get back to step 1.
The present invention is not limited to aforesaid embodiment.The present invention expands to any new feature or any new combination disclosing in this manual, and the arbitrary new method disclosing or step or any new combination of process.
Claims (8)
1. a TS code stream synchronous circuit, is characterized in that, comprises that TS bit stream data latch cicuit, synchronization character testing circuit, message sync detection circuit, synchronization character split circuit and synchronous indicating signal form circuit;
TS bit stream data latch cicuit is for accepting TS bit stream data the TS bit stream data of output through postponing of 188 byte messages or 204 byte messages;
Synchronization character testing circuit is used for accepting the TS bit stream data of 188 byte messages or 204 byte messages, and detects the sync byte in described TS code stream;
Message sync detection circuit all detects sync byte, the TS code stream synchronous indicating signal of output 188 byte messages or 204 byte messages, described n >=8 for judging synchronization character testing circuit in the same position of TS code stream n continuous message;
Synchronization character split circuit, isolates lock-out pulse for realize TS code stream at message sync detection circuit synchronously;
Synchronous indicating signal forms circuit, at message sync detection circuit, realize TS code stream synchronous after output TS code stream synchronous indicating signal, and indication synchronous TS code stream be 188 byte messages or 204 byte messages;
Described synchronization character testing circuit comprises sync byte comparator, 3 latchs, the one 2 input or door, 2 not gates, 22 inputs and door, with mould 188 up-counters of asynchronous resetting and carry output, with mould 204 up-counters of asynchronous resetting and carry output;
The input access TS code stream of described sync byte comparator, output is connected to the first latch and the one 2 input or door simultaneously, the output of the first latch is connected with another input of the one 2 input or door, and the output of described the one 2 input or door is connected to the input of 2 described not gates simultaneously;
The output of the first not gate is connected with an output of door with the one 2 input, the one 2 input is connected with the carry signal output of described mould 188 up-counters with another input of door, and the one 2 input is connected with the input of the second latch with the output of door;
The output of the second latch is connected with the clear terminal of mould 188 up-counters, and the clear terminal of the second latch is connected with the carry signal output of mould 188 up-counters;
The output of the second not gate is connected with an output of door with the 22 input, and the 22 input is connected with the carry signal output of mould 204 up-counters with another input of door, and the 22 input is connected with the input of the 3rd latch with the output of door;
The output of the 3rd latch is connected with the clear terminal of mould 204 up-counters, and the clear terminal of the 3rd latch is connected with the carry signal output of mould 204 up-counters;
Mould 188 up-counters and mould 204 up-counters also have respectively enumeration data output.
2. a kind of TS code stream synchronous circuit according to claim 1, it is characterized in that, possess data useful signal and form circuit, for exporting useful signal or after realizing synchronously and when current TS code stream is front 188 byte of 204 byte messages, export useful signal when current TS code stream being 188 byte message.
3. a kind of TS code stream synchronous circuit according to claim 2, is characterized in that, described TS bit stream data latch cicuit comprises the one 8 latch and the 28 latch; The input access TS code stream of the one 8 latch, the output of the one 8 latch is connected with the input of the 28 latch, and the output of the 28 latch is the TS bit stream data output through time delay.
4. a kind of TS code stream synchronous circuit according to claim 1, is characterized in that, described message sync detection circuit comprises 8 bit shift register that 2 bands enable, 28 inputs and door;
The Enable Pin of the first shift register is connected with the carry signal output of mould 188 up-counters, and its data input pin is connected with the output of the first latch, and 8 outputs correspondences of the first shift register are connected with the input of door with the one 8 input; The one 8 input is 188 byte message TS code stream synchronous indicating signal outputs with the output of door;
The Enable Pin of the second shift register is connected with the carry signal output of mould 204 up-counters, and its data input pin is connected with the output of the first latch, and 8 outputs correspondences of the second shift register are connected with the input of door with the 28 input; The 28 input is 204 byte message TS code stream synchronous indicating signal outputs with the output of door.
5. a kind of TS code stream synchronous circuit according to claim 4, is characterized in that, described synchronization character split circuit comprises 2 latchs, 22 inputs and Men Yuyi No. 4 selectors;
The 32 input is connected with the output of the first latch with an input of door, and another input is connected with the carry signal output of mould 188 up-counters; The 32 input is connected with the input of quad latch with the output of door;
The 42 input is connected with the output of the first latch with an input of door, and another input is connected with the carry signal output of mould 204 up-counters; The 42 input is connected with the input of the 5th latch with the output of door;
Two address gating signal inputs of described No. 4 selectors connect respectively the one 8 input and the output of door and the output of the 28 input and door; The second road signal input part of No. 4 selectors is connected with the output of described quad latch; The Third Road signal input part of No. 4 selectors is connected with the output of described the 5th latch; The output of No. 4 selectors is lock-out pulse output.
6. a kind of TS code stream synchronous circuit according to claim 5, it is characterized in that, described synchronous indicating signal forms circuit and comprises the 22 input or door, the 22 input or door input connect respectively the 1 input with door output and the 28 input with door output, described the 22 input or door output for synchronously completing indication output end.
7. a kind of TS code stream synchronous circuit according to claim 6, it is characterized in that, possess data useful signal and form circuit, described data useful signal forms circuit and comprises that unsigned number is less than 203 comparators, unsigned number and is more than or equal to 187 comparators, 2 latchs and 3 input nand gates;
The enumeration data output of mould 204 up-counters is connected with the input that unsigned number is less than 203 comparators, and the output that unsigned number is less than 203 comparators is connected to 3 input nand gates by the 6th latch;
The enumeration data output of mould 188 up-counters is connected with the input that unsigned number is more than or equal to 187 comparators, and the output that unsigned number is more than or equal to 187 comparators is connected to 3 input nand gates by the 7th latch;
The 3rd input of described 3 input nand gates is connected with the output of door with the 28 input; The output of 3 input nand gates is the effective indication output end of data.
8. a kind of TS code stream synchronous circuit according to claim 1, is characterized in that, described TS bit stream data latch cicuit comprises the one 8 latch and the 28 latch; The input access TS code stream of the one 8 latch, the output of the one 8 latch is connected with the input of the 28 latch, and the output of the 28 latch is the TS bit stream data output through time delay.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110231866.XA CN102256118B (en) | 2011-08-15 | 2011-08-15 | Synchronous circuit and method for TS (Telecommunication Service) code streams |
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| CN201110231866.XA CN102256118B (en) | 2011-08-15 | 2011-08-15 | Synchronous circuit and method for TS (Telecommunication Service) code streams |
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| CN102256118B true CN102256118B (en) | 2014-03-26 |
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| CN201110231866.XA Expired - Fee Related CN102256118B (en) | 2011-08-15 | 2011-08-15 | Synchronous circuit and method for TS (Telecommunication Service) code streams |
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| CN104702977A (en) * | 2015-03-04 | 2015-06-10 | 上海电力学院 | Achievement method for searching TS stream synchronization head of digital TV |
| CN106776394B (en) * | 2017-01-11 | 2019-05-14 | 深圳大普微电子科技有限公司 | A kind of hardware system and memory of data conversion |
| CN110492986B (en) * | 2019-09-11 | 2023-06-23 | 吉林省广播电视研究所(吉林省广播电视局科技信息中心) | Single-fiber precise time prediction synchronous electronic system |
| CN110460332B (en) * | 2019-09-11 | 2024-03-19 | 长春思拓电子科技有限责任公司 | Centered equal ratio predictive electronic system |
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| CN202190357U (en) * | 2011-08-15 | 2012-04-11 | 成都市广达电子电讯技术开发有限公司 | TS (transport stream) synchronous circuit |
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| JPH05160825A (en) * | 1991-12-03 | 1993-06-25 | Fujitsu Ltd | Synchronizing circuit |
| US7161995B1 (en) * | 2002-03-15 | 2007-01-09 | Xilinx, Inc. | Method and apparatus for Viterbi synchronization |
| CN1255952C (en) * | 2003-08-21 | 2006-05-10 | 哈尔滨工业大学 | Manchester coder and decoder |
| CN100452686C (en) * | 2004-04-22 | 2009-01-14 | 东南大学 | Parallel frame alignment circuit applied to optical synchronous digital transferring system |
| CN2774019Y (en) * | 2005-02-04 | 2006-04-19 | Ut斯达康通讯有限公司 | 64-bit series frame synchronizing coder/decoder of optical synchronized digital transmission system |
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| CN202190357U (en) * | 2011-08-15 | 2012-04-11 | 成都市广达电子电讯技术开发有限公司 | TS (transport stream) synchronous circuit |
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| 一种MPEG-2 TS流的同步字节识别;王麒;《中国有线电视》;20041231(第15期);41-43 * |
| 王麒.一种MPEG-2 TS流的同步字节识别.《中国有线电视》.2004,(第15期),41-43. |
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