CN102256118A - Synchronous circuit and method for TS (Telecommunication Service) code streams - Google Patents
Synchronous circuit and method for TS (Telecommunication Service) code streams Download PDFInfo
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Abstract
The invention discloses a synchronous circuit and method for TS (Telecommunication Service) code streams and particularly relates to the field of broadcast television. The invention has the technical main points that the synchronous circuit comprises a TS code stream data latch circuit, a synchronous character detection circuit, a message synchronous detection circuit, a synchronous character separation circuit and a synchronous indicating signal shaping circuit, wherein the TS code stream data latch circuit is used for outputting the delayed TS code stream data; the synchronous character detection circuit is used for detecting synchronous bytes in the TS code streams; the message synchronous detection circuit is used for judging that the same position of multiple continuous messages in the TS code streams has the synchronous bytes; the synchronous character separation circuit is used for separating synchronous pulse after the TS code streams are synchronous; and the synchronous indicating signal shaping circuit is used for outputting the synchronous indicating signals of the TS code streams after the TS code streams are synchronous and indicating that the current TS code streams are the message with the bytes 188 or 204. The invention has the functions of self adaption, automatic resynchronization, message length detection and the like of the message with the bytes 188/204.
Description
Technical field
The present invention relates to the television network broadcast digital signal transmission field, especially relate to the message synchronous circuit and the method for transport stream (Transport Stream is designated hereinafter simply as the TS code stream).
Background technology
At present, China uses TS flow transmission Digital Television and other data-signal that defines in GB/T17975.1 " the universal coding part 1 of information technology moving image and sound information thereof: the system " standard.TS stream is widely used in Hybrid Fiber Coaxial (Hybrid Fiber-Coax Network is designated hereinafter simply as hfc plant) and satellite digital TV network.The TS stream synchronous circuit that the present invention sets forth is used for field of digital television transmission, finishes the TS stream packet delimitative function to input, is the requisite basic circuit modules of equipment such as digital TV multiplexer, modulator, transcoder.
TS stream is made up of message flow, and message length is the fixed length message of 188 bytes or 204 bytes, frame structure as shown in Figure 1: wherein, the value of sync byte is hexadecimal number 0x47, is used for the demarcation of message.Because message inside also this value might occur, therefore before handling message, equipment needs advanced line search, determine the separation and the message length (188/204) of message.
Summary of the invention
The invention discloses the realization details of a kind of TS code stream synchronous circuit and method.The technical solution used in the present invention is such: a kind of TS code stream synchronous circuit comprises that TS bit stream data latch cicuit, synchronization character testing circuit, message sync detection circuit, synchronization character split circuit and synchronous indicating signal form circuit;
TS bit stream data latch cicuit is used to accept the TS bit stream data and the TS bit stream data of output through postponing of 188 byte messages or 204 byte messages;
The synchronization character testing circuit is used to accept the TS bit stream data of 188 byte messages or 204 byte messages, and detects the sync byte in the described TS code stream;
The message sync detection circuit is used for judging that the synchronization character testing circuit all detects sync byte on the same position of TS code stream n continuous message, exports the TS code stream synchronous indicating signal of 188 byte messages or 204 byte messages, described n 〉=8;
The synchronization character split circuit is used for isolating lock-out pulse at message sync detection circuit realization TS code stream synchronously;
Synchronous indicating signal forms circuit, be used for realizing TS code stream back output synchronously TS code stream synchronous indicating signal at the message sync detection circuit, and the synchronous TS code stream of indication is 188 byte messages or 204 byte messages.
The data useful signal forms circuit, is used for when the current TS code stream is 188 byte messages output useful signal or when realizing that back synchronously and current TS code stream are preceding 188 bytes of one 204 byte message, the output useful signal.
Described TS bit stream data latch cicuit comprises the one 8 latch and the 28 latch; The input of the one 8 latch inserts the TS code stream, and the one 8 be that the output of latch is connected with the input of the 28 latch, and the output of the 28 latch is to pass through the TS bit stream data output of delaying time.
Described synchronization character testing circuit comprises mould 204 up-counters of sync byte comparator, 3 latchs, the one 2 input or door, 2 not gates, 22 inputs and mould 188 up-counters, band asynchronous resetting and the carry output of door, band asynchronous resetting and carry output;
The input of described sync byte comparator inserts the TS code stream, output is connected to first latch and the one 2 input or door simultaneously, the output of first latch is connected with another input of the one 2 input or door, and the output of described the one 2 input or door is connected to the input of described 2 not gates simultaneously;
The output of first not gate is connected with an output of door with the one 2 input, the one 2 input is connected with the carry signal output of described mould 188 up-counters with another input of door, and the one 2 input is connected with the input of second latch with the output of door;
The output of second latch is connected with the clear terminal of mould 188 up-counters, and the clear terminal of second latch is connected with the carry signal output of mould 188 up-counters;
The output of second not gate is connected with an output of door with the 22 input, and the 22 input is connected with the carry signal output of mould 204 up-counters with another input of door, and the 22 input is connected with the input of the 3rd latch with the output of door;
The output of the 3rd latch is connected with the clear terminal of mould 204 up-counters, and the clear terminal of the 3rd latch is connected with the carry signal output of mould 204 up-counters;
Mould 188 up-counters and mould 204 up-counters also have the enumeration data output respectively.
Described message sync detection circuit comprises 8 bit shift register that 2 bands enable, 28 inputs and door;
The Enable Pin of described first shift register is connected with the carry signal output of mould 188 up-counters, and its data input pin is connected with the output of first latch, and 8 outputs of first shift register are corresponding to be connected with the input of door with the one 8 input; The one 8 input is 188 byte message TS code stream synchronous indicating signal outputs with the output of door;
The Enable Pin of described second shift register is connected with the carry signal output of mould 204 up-counters, and its data input pin is connected with the output of first latch, and 8 outputs of second shift register are corresponding to be connected with the input of door with the 28 input; The 28 input is 204 byte message TS code stream synchronous indicating signal outputs with the output of door.
Described synchronization character split circuit comprises 2 latchs, 22 inputs and Men Yuyi No. 4 selectors;
Described the 32 input is connected with the output of first latch with an input of door, and another input is connected with the carry signal output of mould 188 up-counters; The 32 input is connected with the input of quad latch with the output of door;
Described the 42 input is connected with the output of first latch with an input of door, and another input is connected with the carry signal output of mould 204 up-counters; The 42 input is connected with the input of the 5th latch with the output of door;
Two address gating signal inputs of described No. 4 selectors connect the one 8 input and the output of door and the output of the 28 input and door respectively; The second road signal input part of No. 4 selectors is connected with the output of described quad latch; The Third Road signal input part of No. 4 selectors is connected with the output of described the 5th latch; The output of No. 4 selectors is the lock-out pulse output.
Described synchronous indicating signal forms circuit and comprises the 22 input or door, and the input of the 22 input or door connects the output of the output of the one 8 input and door and the 28 input and door respectively, described second or the output of door for finishing indication output end synchronously;
Described the one 8 input is 188 byte message indication output end with the output of door;
Described the 28 input is 204 byte message indication output end with the output of door.
Described data useful signal form circuit comprise unsigned number less than 203 comparators, unsigned number more than or equal to 187 comparators, 2 latchs and 3 input nand gates;
The enumeration data output of mould 204 up-counters is connected with the input of unsigned number less than 203 comparators, and unsigned number is connected to 3 input nand gates less than the output of 203 comparators by the 6th latch;
The enumeration data output of mould 188 up-counters is connected with the input of unsigned number more than or equal to 187 comparators, and unsigned number is connected to 3 input nand gates more than or equal to the output of 187 comparators by the 7th latch;
The 3rd input of described 3 input nand gates is connected with the output of door with the 28 input; The output of 3 input nand gates is the effective indication output end of data.
A kind of TS code stream method for synchronous comprises:
Step 1: whether the TS stream byte that detects input equals sync byte, when equaling sync byte, forwards step 2 to, and this time point meter is made T0; Repeated execution of steps 1 when being not equal to sync byte;
Step 2: whether the TS stream byte of judging the n * L the work clock correspondence that begins constantly from T0 successively equals sync byte, and n is an integer, and 0＜n＜8, and L is a TS code stream message byte number: if equal sync byte, and repeated execution of steps 2; If be not equal to sync byte, then return step 1;
When the TS stream byte that detects the 8th * L work clock correspondence equals sync byte, then enter step 3;
Step 3: whether the TS stream byte of judging the n * L work clock correspondence one by one equals sync byte, and n is an integer, and n〉8: flow byte and be not equal to sync byte if detect the TS of the n * L work clock correspondence, then think synchronization loss, get back to step 1.
Described TS code stream message byte number L is 188 or 204.
In sum, owing to adopted technique scheme, the invention has the beneficial effects as follows:
Possess 188/204 byte message self adaptation, automatically heavy synchronously, message length detection, valid data detection, synchronization character position probing, finish deixis synchronously.
Description of drawings
The present invention will illustrate by example and with reference to the mode of accompanying drawing, wherein:
Fig. 1 is that length is the frame structure of the fixed length message of 188 or 204 bytes;
Fig. 2 is the input/output interface schematic diagram of synchronous circuit among the present invention;
Fig. 3 is a synchronous circuit output timing diagram among the present invention;
Fig. 4 is the circuit diagram of synchronous circuit embodiment among the present invention;
Fig. 5 shows is TS bit stream data latch cicuit in the circuit diagram of synchronous circuit embodiment shown in Figure 4;
Fig. 6 shows is synchronization character testing circuit in the circuit diagram of synchronous circuit embodiment shown in Figure 4;
Fig. 7 shows is message sync detection circuit in the circuit diagram of synchronous circuit embodiment shown in Figure 4;
Fig. 8 shows is synchronization character split circuit in the circuit diagram of synchronous circuit embodiment shown in Figure 4;
Fig. 9 shows is that data useful signal in the circuit diagram of synchronous circuit embodiment shown in Figure 4 forms circuit;
Figure 10 shows is that synchronous indicating signal in the circuit diagram of synchronous circuit embodiment shown in Figure 4 forms circuit;
Figure 11 is a method for synchronous flow chart among the present invention.
Embodiment
Disclosed all features in this specification, or the step in disclosed all methods or the process except mutually exclusive feature and/or step, all can make up by any way.
Disclosed arbitrary feature in this specification (comprising any accessory claim, summary and accompanying drawing) is unless special narration all can be replaced by other equivalences or the alternative features with similar purpose.That is, unless special narration, each feature is an example in a series of equivalences or the similar characteristics.
Synchronous circuit among the present invention comprises that TS bit stream data latch cicuit, synchronization character testing circuit, message sync detection circuit, data useful signal form circuit and synchronous indicating signal forms circuit.
The circuit diagram of an embodiment of synchronous circuit among the present invention as shown in Figure 4.
TS bit stream data latch cicuit comprises that 8 latch p1 and 8 are latch p2 as described in Figure 5; The input of 8 latch p1 inserts the TS code stream, and the output of 8 latch p1 is connected with the input of 8 latch p2, and the output of 8 latch p2 is the TS bit stream data output through time-delay.
The synchronization character testing circuit comprises sync byte comparator p3,3 latchs, 2 inputs or door, 2 not gates, 22 inputs and the mould 188 up-counter p11 of door, band asynchronous resetting and carry output and the mould 204 up-counter p20 of band asynchronous resetting and carry output as described in Figure 6.
The input of described sync byte comparator p3 inserts the TS code stream, output is connected to latch p4 and 2 inputs or door p8 simultaneously, the output of latch p4 is connected with another input of 2 inputs or door p8, and the output of described 2 inputs or door p8 is connected to 2 not gate p7, p17 simultaneously.
The output of not gate p7 is connected with the input of 2 inputs with door p6, and 2 inputs are connected with the carry signal output of described mould 188 up-counter p11 with another input of door p6, and 2 inputs are connected with the input of latch p5 with the output of door p6.
The output of latch p5 is connected with the clear terminal of mould 188 up-counter p11, and the clear terminal of latch p5 is connected with the carry signal output of mould 188 up-counter p11.
The output of not gate p17 is connected with the input of 2 inputs with door p16, and 2 inputs are connected with the carry signal output of mould 204 up-counter p20 with another input of door p16, and 2 inputs are connected with the input of latch p15 with the output of door p16.
The output of latch p15 is connected with the clear terminal of mould 204 up-counter p20, and the clear terminal of latch p15 is connected with the carry signal output of mould 204 up-counter p20.
The operation principle of synchronization character testing circuit is: P3 is with DI[7..0] compare with constant 0x47, if equate then the aeb output high level of P3.Detect DI[7..0] on occurred that this incident of 0x47 is latched device P5 and P15 latchs, the output of latch can cause the asynchronous resetting of counter P11 and P20 to bring out existing low level, counter begins to count from zero.P11 is mould 188 counters of bringing position output into, counting down at 188 o'clock, at rising edge clock P11 carry output high level, remove the incident that the last time of writing down among the P5 detects 0x47, detect DI[7..0 once more at the trailing edge of clock] on whether synchronization character 0x47 has appearred.P20 is mould 204 counters of bringing position output into, counting down at 204 o'clock, at rising edge clock P20 carry output high level, remove the incident that the last time of writing down among the P15 detects 0x47, detect DI[7..0 once more at the trailing edge of clock] on whether synchronization character 0x47 has appearred.
As Fig. 7, described message sync detection circuit comprises 22 inputs and door, 2 latchs, 28 bit shift register, 28 inputs and door that band enables.
Described 2 inputs are connected with the output of latch p4 with the input of door p9, and another input is connected with the carry signal output of mould 188 up-counter p11; 2 inputs are connected with the input of latch p10 with the output of door p9.
The Enable Pin of described shift register p12 is connected with the carry signal output of mould 188 up-counter p11, and its data input pin is connected with the output of latch p4,8 outputs of shift register p12 and input corresponding be connected of 8 inputs with a p13.
Described 2 inputs are connected with the output of latch p4 with the input of door p18, and another input is connected with the carry signal output of mould 204 up-counter p20; 2 inputs are connected with the input of latch p19 with the output of door p18.
The Enable Pin of described shift register p21 is connected with the carry signal output of mould 204 up-counter p20, and its data input pin is connected with the output of latch p4,8 outputs of shift register p21 and input corresponding be connected of 8 inputs with a p22.
The operation principle of message sync detection circuit is: the output that P4 is received in the shiftin input of P12 and P21.P4 is a d type flip flop, latchs P3(0x47 unsigned number comparator at the rising edge of clock) the output result.
The enable signal of P12 is received P11(mould 188 counters) the carry output, P11 enabling counting after P4 detects synchronization character 0x47 is used for playing backward to detecting 0x47 that the 187 carry digit cout of byte place will uprise.The enable of P12 becomes effectively, and the synchronization character comparative result that current P4 is latched is saved in the shift register.Continuous 8 times all is effective when the output of P4, show at 188 byte boundary places and be consecutively detected synchronization character 0x47, think that synchronous circuit has been synchronized to the TS stream that message length is 188 bytes, 188 byte message TS code stream synchronous indicating signal SYNC_SEL0 output effectively.
The enable signal of P21 is received P20(mould 204 counters) the carry output, P20 enabling counting after P4 detects synchronization character 0x47 is used for playing backward to detecting 0x47 that the 203 carry digit cout of byte place will uprise.The enable of P21 becomes effectively, and the synchronization character comparative result that current P4 is latched is saved in the shift register.Continuous 8 times all is effective when the output of P4, show at 204 byte boundary places and be consecutively detected synchronization character 0x47, think that synchronous circuit has been synchronized to the TS stream that message length is 204 bytes, 204 byte message TS code stream synchronous indicating signal SYNC_SEL1 output effectively.
As Fig. 8, the synchronization character split circuit is to be used for isolating lock-out pulse after being synchronized to 188 or 204 byte TS stream.This function is made up of with door P18 with door P9,2 inputs Port Multiplier P14, d type flip flop P10, d type flip flop P19,2 inputs.
After being synchronized to certain (188/204) code stream, SYNC_SEL[1..0] be output as the TS stream that 0x1(is synchronized to 188 bytes) or 0x2(be synchronized to the TS stream of 204 bytes).When not synchronous, the selecting side of Port Multiplier is input as 0x0, and the output of DSYNC lock-out pulse is invalid.
Behind the TS stream that is synchronized to 188 bytes, Port Multiplier P14 selects data1 as output.The input of data1 is the output of P10, is the P9 output result that the clock trailing edge is latched into d type flip flop P10.2 inputs are P11(mould 188 counters with door P9 input) the carry output, another input is the output result of synchronization character comparator.If synchronization character 0x47 occurs at 188 byte boundary places, Port Multiplier P14 then exports the lock-out pulse of a clock width.
Behind the TS stream that is synchronized to 204 bytes, Port Multiplier P14 selects data2 as output.The input of data2 is the output of P19, is the 18 output results that the clock trailing edge is latched into d type flip flop P19.2 inputs are P21(mould 204 counters with door P18 input) the carry output, another input is the output result of synchronization character comparator.If synchronization character 0x47 occurs at 204 byte boundary places, Port Multiplier P14 then exports the lock-out pulse of a clock width.
As Fig. 9, it is to establish for convenience of the processing of subsequent conditioning circuit that described data useful signal forms circuit, can be used for removing the slack byte of message, comprise unsigned number less than 203 comparator p24, unsigned number more than or equal to 187 comparator p28,2 latchs and 3 input nand gates.
The enumeration data output of mould 204 up-counter p20 is connected with the input of unsigned number less than 203 comparator p24, and unsigned number is connected to 3 input nand gate p26 less than the output of 203 comparator p24 by latch p25.
The enumeration data output of mould 188 up-counter p11 is connected with the input of unsigned number more than or equal to 187 comparator p28, and unsigned number is connected to 3 input nand gate p26 more than or equal to the output of 187 comparator p28 by latch p29.
The 3rd input of described 3 input nand gate p26 is connected with the output of 8 inputs with door p22; The output of 3 input nand gate p26 is the effective indication output end of data.
The operation principle that the data useful signal forms circuit is: in the TS of 188 bytes stream, the DV signal is a continuously effective, and in the TS of 204 bytes stream, it is invalid that the DV signal just is in later in 188 bytes.
The data useful signal only need just come into force in the message of 204 bytes, and therefore three NAND gate P26 have an input to receive 204 byte message synchronous indicating signal SYNC_SEL1, when this invalidating signal, and DV signal output continuously effective.
Behind the TS that is synchronized to 204 bytes, SYNC_SEL1 is effective, and other two inputs are depended in the output of DV.P25 and P29 are d type flip flops, be used for latched comparator P24(203 unsigned number " less than " comparator) and the P28(187 unsigned number " more than or equal to " comparator) output.In preceding 188 bytes of TS message, the input value of P28 is less than 187, and the input value of P24 is less than 203, and P29 is output as effectively, and P25 is output as invalid, and DV is output as effectively.In the 189th to 204 byte of TS message, P29 is output as effectively, and P25 is output as effectively, and DV is output as invalid.
As Figure 10, synchronous indicating signal by SYNC_SEL0 and SYNC_SEL1 mutually or form, it still is that 204 byte messages are formed by 188 byte messages that SYNC_SEL0 and SYNC_SEL1 then indicate TS stream respectively.
Fig. 2 is the input/output interface schematic diagram of synchronous circuit among the present invention, and synchronous circuit offers outside interface signal and is defined as follows:
Input TS flow data (DI[7..0]): the input of TS flow data, this data sync is to the DI_CLK signal.
Input TS stream clock (DI_CLK): TS flows input clock.
Output TS flow data (DO[7..0]): the output of TS flow data, this data sync is to the DO_CLK signal.
Output TS stream clock (DO_CLK): TS stream output clock, this signal is the another name of DI_CLK.
Sync byte indication (DSYNC): output was not low when code stream was synchronous.Code stream synchronously after, as DO[7..0] when sync byte occurring on the line output high.
Data are effectively indicated (DV): output was not low when code stream was synchronous.Code stream synchronously after, normal high under 188 byte message situations, under 204 byte message situations, preceding 188 bytes output is high, back 16 bytes output is low.
Finish indication (SYNC) synchronously: output was not low when code stream was synchronous.After code stream is synchronous, be output as height, represent successful synchronously.
188 byte messages indications (L188): output was not low when code stream was synchronous.After code stream was synchronous, output was high if incoming message is 188 byte longs, otherwise is low.
204 byte messages indications (L204): output was not low when code stream was synchronous.After code stream was synchronous, output was high if incoming message is 204 byte longs, otherwise is low.The sequential chart of each output signal is seen Fig. 3.
As Figure 11, method for synchronous is among the present invention:
Step 1: whether the TS stream byte that detects input equals sync byte 0x47, when equaling 0x47, forwards step 2 to, and this time point meter is made T0; Repeated execution of steps 1 when being not equal to 0x47;
Step 2: judge from the TS stream byte of n * the 188 or 204 work clock correspondence that T0 begins constantly whether equal 0x47 successively, n is an integer, and 0＜n＜8,188 or 204 are TS code stream message byte number: if equal 0x47, and repeated execution of steps 2; If be not equal to 0x47, then return step 1;
When the TS stream byte that detects the 8th * 188 or 204 work clock correspondence equals 0x47, then enter step 3;
Step 3: whether the TS stream byte of judging n * 188 or 204 a work clock correspondence one by one equals 0x47, n is an integer, and n〉8: be not equal to 0x47 if detect the TS stream byte of n * 188 or 204 a work clock correspondence, then think synchronization loss, get back to step 1.
The present invention is not limited to aforesaid embodiment.The present invention expands to any new feature or any new combination that discloses in this manual, and the arbitrary new method that discloses or step or any new combination of process.
Claims (10)
1. a TS code stream synchronous circuit is characterized in that, comprises that TS bit stream data latch cicuit, synchronization character testing circuit, message sync detection circuit, synchronization character split circuit and synchronous indicating signal form circuit;
TS bit stream data latch cicuit is used to accept the TS bit stream data and the TS bit stream data of output through postponing of 188 byte messages or 204 byte messages;
The synchronization character testing circuit is used to accept the TS bit stream data of 188 byte messages or 204 byte messages, and detects the sync byte in the described TS code stream;
The message sync detection circuit is used for judging that the synchronization character testing circuit all detects sync byte on the same position of TS code stream n continuous message, exports the TS code stream synchronous indicating signal of 188 byte messages or 204 byte messages, described n 〉=8;
The synchronization character split circuit is used for isolating lock-out pulse at message sync detection circuit realization TS code stream synchronously;
Synchronous indicating signal forms circuit, be used for realizing TS code stream back output synchronously TS code stream synchronous indicating signal at the message sync detection circuit, and the synchronous TS code stream of indication is 188 byte messages or 204 byte messages.
2. a kind of TS code stream synchronous circuit according to claim 1, it is characterized in that, possess the data useful signal and form circuit, be used for when the current TS code stream is 188 byte messages the output useful signal or when realizing that back synchronously and current TS code stream are preceding 188 bytes of one 204 byte message, the output useful signal.
3. a kind of TS code stream synchronous circuit according to claim 1 and 2 is characterized in that described TS bit stream data latch cicuit comprises the one 8 latch and the 28 latch; The input of the one 8 latch inserts the TS code stream, and the output of the one 8 latch is connected with the input of the 28 latch, and the output of the 28 latch is the TS bit stream data output through time-delay.
4. a kind of TS code stream synchronous circuit according to claim 3, it is characterized in that described synchronization character testing circuit comprises mould 204 up-counters of sync byte comparator, 3 latchs, the one 2 input or door, 2 not gates, 22 inputs and mould 188 up-counters, band asynchronous resetting and the carry output of door, band asynchronous resetting and carry output;
The input of described sync byte comparator inserts the TS code stream, output is connected to first latch and the one 2 input or door simultaneously, the output of first latch is connected with another input of the one 2 input or door, and the output of described the one 2 input or door is connected to the input of described 2 not gates simultaneously;
The output of first not gate is connected with an output of door with the one 2 input, the one 2 input is connected with the carry signal output of described mould 188 up-counters with another input of door, and the one 2 input is connected with the input of second latch with the output of door;
The output of second latch is connected with the clear terminal of mould 188 up-counters, and the clear terminal of second latch is connected with the carry signal output of mould 188 up-counters;
The output of second not gate is connected with an output of door with the 22 input, and the 22 input is connected with the carry signal output of mould 204 up-counters with another input of door, and the 22 input is connected with the input of the 3rd latch with the output of door;
The output of the 3rd latch is connected with the clear terminal of mould 204 up-counters, and the clear terminal of the 3rd latch is connected with the carry signal output of mould 204 up-counters;
Mould 188 up-counters and mould 204 up-counters also have the enumeration data output respectively.
5. a kind of TS code stream synchronous circuit according to claim 4 is characterized in that, described message sync detection circuit comprises 8 bit shift register that 2 bands enable, 28 inputs and door;
The Enable Pin of described first shift register is connected with the carry signal output of mould 188 up-counters, and its data input pin is connected with the output of first latch, and 8 outputs of first shift register are corresponding to be connected with the input of door with the one 8 input; The one 8 input is 188 byte message TS code stream synchronous indicating signal outputs with the output of door;
The Enable Pin of described second shift register is connected with the carry signal output of mould 204 up-counters, and its data input pin is connected with the output of first latch, and 8 outputs of second shift register are corresponding to be connected with the input of door with the 28 input; The 28 input is 204 byte message TS code stream synchronous indicating signal outputs with the output of door.
6. a kind of TS code stream synchronous circuit according to claim 5 is characterized in that, described synchronization character split circuit comprises 2 latchs, 22 inputs and Men Yuyi No. 4 selectors;
Described the 32 input is connected with the output of first latch with an input of door, and another input is connected with the carry signal output of mould 188 up-counters; The 32 input is connected with the input of quad latch with the output of door;
Described the 42 input is connected with the output of first latch with an input of door, and another input is connected with the carry signal output of mould 204 up-counters; The 42 input is connected with the input of the 5th latch with the output of door;
Two address gating signal inputs of described No. 4 selectors connect the one 8 input and the output of door and the output of the 28 input and door respectively; The second road signal input part of No. 4 selectors is connected with the output of described quad latch; The Third Road signal input part of No. 4 selectors is connected with the output of described the 5th latch; The output of No. 4 selectors is the lock-out pulse output.
7. a kind of TS code stream synchronous circuit according to claim 6, it is characterized in that, described synchronous indicating signal forms circuit and comprises the 22 input or door, the 22 the input or the door input connect respectively the 1 the input with the door output and the 28 the input with the door output, described the 22 the input or the door output for finishing indication output end synchronously.
8. a kind of TS code stream synchronous circuit according to claim 7 is characterized in that, described data useful signal form circuit comprise unsigned number less than 203 comparators, unsigned number more than or equal to 187 comparators, 2 latchs and 3 input nand gates;
The enumeration data output of mould 204 up-counters is connected with the input of unsigned number less than 203 comparators, and unsigned number is connected to 3 input nand gates less than the output of 203 comparators by the 6th latch;
The enumeration data output of mould 188 up-counters is connected with the input of unsigned number more than or equal to 187 comparators, and unsigned number is connected to 3 input nand gates more than or equal to the output of 187 comparators by the 7th latch;
The 3rd input of described 3 input nand gates is connected with the output of door with the 28 input; The output of 3 input nand gates is the effective indication output end of data.
9. a TS code stream method for synchronous is characterized in that, comprising:
Step 1: whether the TS stream byte that detects input equals sync byte, when equaling sync byte, forwards step 2 to, and this time point meter is made T0; Repeated execution of steps 1 when being not equal to sync byte;
Step 2: whether the TS stream byte of judging the n * L the work clock correspondence that begins constantly from T0 successively equals sync byte, and n is an integer, and 0＜n＜8, and L is a TS code stream message byte number: if equal sync byte, and repeated execution of steps 2; If be not equal to sync byte, then return step 1;
When the TS stream byte that detects the 8th * L work clock correspondence equals sync byte, then enter step 3;
Step 3: whether the TS stream byte of judging the n * L work clock correspondence one by one equals sync byte, and n is an integer, and n〉8: flow byte and be not equal to sync byte if detect the TS of the n * L work clock correspondence, then think synchronization loss, get back to step 1.
10. a kind of TS code stream method for synchronous according to claim 9 is characterized in that, described TS code stream message byte number L is 188 or 204.
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