CN104601179A - Erasure code coding circuit and decoding circuit and coding and encoding circuit of storage system - Google Patents
Erasure code coding circuit and decoding circuit and coding and encoding circuit of storage system Download PDFInfo
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- CN104601179A CN104601179A CN201410769151.3A CN201410769151A CN104601179A CN 104601179 A CN104601179 A CN 104601179A CN 201410769151 A CN201410769151 A CN 201410769151A CN 104601179 A CN104601179 A CN 104601179A
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Abstract
The invention discloses an erasure code coding circuit and decoding circuit of a storage system. The erasure code coding circuit comprises three erasure code coding circuit units; every erasure code coding circuit unit comprises an input port and an output port, wherein the input port is used for inputting data to be coded; the erasure code coding circuit is used for multiplying the input data to be coded and corresponding coefficients through Galois field multiplication to obtain the Galois field multiplication output and performing exclusive OR operation on the plurality of Galois field multiplication values to obtain calibration data, wherein the coefficients of any two of the erasure code coding circuit units are linearly independent. According to the erasure code coding circuit and decoding circuit and a coding and encoding circuit of the storage system, the efficient coding and decoding of erasure codes can be implemented.
Description
[technical field]
The present invention relates to area information storage, particularly relate to a kind of storage system correcting and eleting codes coding, decoding circuit and coding-decoding circuit.
[background technology]
In transfer of data and field of data storage, correcting and eleting codes is all a very important concept.The principle of correcting and eleting codes is with M data block, calculates N number of checking data block.Having altogether in M+N data block, as long as the data block of losing is no more than N number of, just can recover whole initial data.Especially in field of data storage, be the means ensureing that data reliability is very important.In field of storage, if generally can tolerate that three dishes lost efficacy, and had just reached the reliability index of system.
The modes such as current correcting and eleting codes many uses RS coding realize, and can realize the M+N of arbitrary size.The mode that this M and N is optional, flexibility is very large, but it is also very large to realize expense.For conventional RS code, realize M=15, the byte correcting and eleting codes of N=3, need tens clock cycle time delays.
[summary of the invention]
In order to overcome the deficiencies in the prior art, the invention provides a kind of storage system correcting and eleting codes coding, decoding circuit, to improve the efficiency of coding or decoding.
A kind of storage system correcting and eleting codes coding circuit, comprise three correcting and eleting codes coding circuit unit, described correcting and eleting codes coding circuit unit comprises input port for inputting data to be encoded and output port, described correcting and eleting codes coding circuit is used for the data to be encoded of input to be multiplied with coefficient of correspondence Galois Field multiplication, obtain Galois Field multiplication to export, and XOR is carried out in multiple Galois Field multiplication output, obtain checking data, linear independence between the coefficient of any two correcting and eleting codes coding circuit unit.
In one embodiment, described three correcting and eleting codes coding circuit unit are the first correcting and eleting codes coding circuit unit, the second correcting and eleting codes coding circuit unit and the 3rd correcting and eleting codes coding circuit unit;
Described first correcting and eleting codes coding circuit unit has XOR device, and in described first correcting and eleting codes coding circuit unit, described Galois Field multiplication exports the described data to be encoded for input;
Described second correcting and eleting codes coding circuit unit has XOR device and Galois field multiplying unit, in described second correcting and eleting codes coding circuit unit, the described Galois Field multiplication of a part exports and the data to be encoded of the correspondence of input and corresponding coefficient is carried out being multiplied obtaining by described Galois field multiplying unit, and a part of described Galois Field multiplication exports as corresponding data to be encoded;
Described 3rd correcting and eleting codes coding circuit unit has XOR device and Galois field multiplying unit, in described 3rd correcting and eleting codes coding circuit unit, the described Galois Field multiplication of a part exports and the data to be encoded of the correspondence of input and corresponding coefficient is carried out being multiplied obtaining by described Galois field multiplying unit, and a part of described Galois Field multiplication exports as corresponding data to be encoded.
Present invention also offers the storage system correcting and eleting codes decoding circuit that a kind of with described storage system correcting and eleting codes coding circuit coordinates, comprise: the first correcting and eleting codes coding circuit unit, the second correcting and eleting codes coding circuit unit, the 3rd correcting and eleting codes coding circuit unit and two decoding multiplier modules, described decoding multiplier module comprises first input end, the second input, the 3rd input, four-input terminal, the 5th input, the 6th input, the 7th input, the 8th input, the 9th input and output;
Described decoding multiplier module is used for the first Galois Field multiplication value, the second Galois Field multiplication value, the 3rd Galois Field multiplication value, the 4th Galois Field multiplication value, the 5th Galois Field multiplication value and the 6th Galois Field multiplication value to carry out XOR; Wherein, described first Galois Field multiplication value is the Galois Field multiplication value of first input end, the 5th input and the 9th input, second Galois Field multiplication value is the Galois Field multiplication value of the second input, the 6th input and the 7th input, 3rd Galois Field multiplication value is the Galois Field multiplication value of the 3rd input, four-input terminal and the 8th input, and the 4th Galois Field multiplication value is the Galois Field multiplication value of the 3rd input, the 5th input and the 7th input; 5th Galois Field multiplication value is the Galois Field multiplication value of the second input, four-input terminal and the 9th input; 6th Galois Field multiplication value is the Galois Field multiplication value of first input end, the 6th input and the 8th input;
The data of losing in described data to be encoded are substituted with zero, input the first correcting and eleting codes coding circuit unit of described storage system correcting and eleting codes decoding circuit, the second correcting and eleting codes coding circuit unit and the 3rd correcting and eleting codes coding circuit unit respectively, obtain the first intermediate data, the second intermediate data and the 3rd intermediate data respectively;
The 3rd checking data XOR that the second checking data that the first checking data produced by the first correcting and eleting codes coding circuit unit that described first intermediate data, the second intermediate data and the 3rd intermediate data produce with described storage system correcting and eleting codes coding circuit respectively, the second correcting and eleting codes coding circuit unit produce, the 3rd correcting and eleting codes coding circuit unit produce, obtains the first calculated data, the second calculated data and the 3rd calculated data respectively;
The first input end of the first decoding multiplier module, the second input and the 3rd input input the coefficient of the first correcting and eleting codes coding circuit unit corresponding to first data of losing, second data of losing and the 3rd position of data in described data to be encoded of losing respectively; The four-input terminal of described first decoding multiplier module, the 5th input and the 6th input input the coefficient of the second correcting and eleting codes coding circuit unit corresponding to first data of losing, second data of losing and the 3rd position of data in described data to be encoded of losing respectively; 7th input of described first decoding multiplier module, the 8th input and the 9th input input the coefficient of the 3rd correcting and eleting codes coding circuit unit corresponding to first data of losing, second data of losing and the 3rd position of data in described data to be encoded of losing respectively;
Second input of the second decoding multiplier module and the 3rd input input the coefficient of second data of losing and the 3rd the first correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively; 5th input of described second decoding multiplier module and the 6th input input the coefficient of second data of losing and the 3rd the second correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively; 8th input of described second decoding multiplier module and the 9th input input the coefficient of second data of losing and the 3rd the 3rd correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively; The first input end of the second decoding multiplier module, four-input terminal and the 7th input input described first calculated data, the second calculated data and the 3rd calculated data respectively.
In one embodiment, the 3rd decoding multiplier module and the 4th decoding multiplier module is also comprised;
The first input end of described 3rd decoding multiplier module and the 3rd input input the coefficient of first data of losing and the 3rd the first correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively; The four-input terminal of described 3rd decoding multiplier module and the 6th input input the coefficient of first data of losing and the 3rd the second correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively; 7th input of described 3rd decoding multiplier module and the 9th input input the coefficient of first data of losing and the 3rd the 3rd correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively; Second input of the 3rd decoding multiplier module, the 5th input and the 8th input input described first calculated data, the second calculated data and the 3rd calculated data respectively;
The first input end of described 4th decoding multiplier module and the second input input the coefficient of first data of losing and second the first correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively; The four-input terminal of described 4th decoding multiplier module and the 5th input input the coefficient of first data of losing and second the second correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively; 7th input of described 4th decoding multiplier module and the 8th input input the coefficient of first data of losing and second the 3rd correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively; The four-input terminal of the 4th decoding multiplier module, the 6th input and the 9th input input described first calculated data, the second calculated data and the 3rd calculated data respectively.
In one embodiment, also comprise the first galois field to binary field mapping table, second galois field is to binary field mapping table, 3rd galois field is to binary field mapping table, 4th galois field is to binary field mapping table, first subtracter, second subtracter and the 3rd subtracter, described first galois field is to binary field mapping table, second galois field is to binary field mapping table, 3rd galois field to binary field mapping table and the 4th galois field to the input of binary field mapping table respectively with the first decoding multiplier module, second decoding multiplier module, 3rd decoding multiplier module is connected with the output of the 4th decoding multiplier module, described first subtracter is used for described second galois field to deduct the output of the first galois field to binary field mapping table to the output of binary field mapping table, described second subtracter is used for described 3rd galois field to deduct the output of the first galois field to binary field mapping table to the output of binary field mapping table, described 3rd subtracter is used for described 4th galois field to deduct the output of the first galois field to binary field mapping table to the output of binary field mapping table.
In one embodiment, also comprise the first binary field to galois field mapping table, the second binary field to galois field mapping table and the 3rd binary field to galois field mapping table, described first binary field is connected with the output of described first subtracter, the second subtracter and the 3rd subtracter with the input of the 3rd binary field to galois field mapping table to galois field mapping table, the second binary field respectively to galois field mapping table.
In one embodiment, also comprise at least two M road selectors, M road selector is used for will the positional information of obliterated data in described data to be encoded of input, exports as the coefficient of the correcting and eleting codes coding circuit unit of correspondence is to the corresponding input of decoding multiplier module; Wherein, M is the number of data to be encoded.
In one embodiment,
M data to be encoded, the first checking data, the second checking data and the 3rd checking data are arranged in order the array of composition M+3 data; Coefficient in first group of coefficient that M+3 data of described data are corresponding is followed successively by en1_1, en1_2 ... en1_M, 8 ' h1,8 ' h0,8 ' h0; Coefficient in second group of coefficient that M+3 data of described data are corresponding is followed successively by en2_1, en2_2 ... en2_M, 8 ' h0,8 ' h1,8 ' h0; Coefficient in the 3rd group of coefficient that M+3 data of described data are corresponding is followed successively by en3_1, en3_2 ... en3_M, 8 ' h0,8 ' h0,8 ' h1; Wherein, en1_1, en1_2 ... en1_M is followed successively by coefficient corresponding to M data to be encoded of the first correcting and eleting codes coding circuit unit, en2_1, en2_2 ... en2_M is followed successively by coefficient corresponding to M data to be encoded of the first correcting and eleting codes coding circuit unit, en3_1, en3_2 ... en3_M is followed successively by coefficient corresponding to M data to be encoded of the first correcting and eleting codes coding circuit unit;
If certain loss of data in described array, substitute the data of described loss with zero;
The first input end of the first decoding multiplier module, the second input and the 3rd input input the coefficient of first data of losing, second data of losing and the 3rd data of the losing first group coefficient corresponding in the position of described array respectively; The four-input terminal of described first decoding multiplier module, the 5th input and the 6th input input the coefficient of second group of coefficient corresponding to first data of losing, second data of losing and the 3rd position of data in described array of losing respectively; 7th input of described first decoding multiplier module, the 8th input and the 9th input input the coefficient of first data of losing, second data of losing and the 3rd data of the losing three group coefficient corresponding in the position of described array respectively;
Second input of the second decoding multiplier module and the 3rd input input the coefficient of second data of losing and the 3rd first group of coefficient corresponding to the position of data in described array lost respectively; 5th input of described second decoding multiplier module and the 6th input input the coefficient of second data of losing and the 3rd second group of coefficient corresponding to the position of data in described array lost respectively; 8th input of described second decoding multiplier module and the 9th input input the coefficient of second data of losing and the 3rd the 3rd group of coefficient corresponding to the position of data in described array lost respectively;
The first input end of described 3rd decoding multiplier module and the 3rd input input the coefficient of first data of losing and the 3rd first group of coefficient corresponding to the position of data in described array lost respectively; The four-input terminal of described 3rd decoding multiplier module and the 6th input input the coefficient of first data of losing and the 3rd second group of coefficient corresponding to the position of data in described array lost respectively; 7th input of described 3rd decoding multiplier module and the 9th input input the coefficient of first data of losing and the 3rd the 3rd group of coefficient corresponding to the position of data in described array lost respectively;
The first input end of described 4th decoding multiplier module and the second input input the coefficient of first data of losing and second first group of coefficient corresponding to the position of data in described array lost respectively; The four-input terminal of described 4th decoding multiplier module and the 5th input input the coefficient of first data of losing and second second group of coefficient corresponding to the position of data in described array lost respectively; 7th input of described 4th decoding multiplier module and the 8th input input the coefficient of first data of losing and second the 3rd group of coefficient corresponding to the position of data in described array lost respectively.
Present invention also offers a kind of storage system correcting and eleting codes coding-decoding circuit, comprise described storage system correcting and eleting codes coding circuit and described storage system correcting and eleting codes decoding circuit.
The data of loss can be recovered by the present invention more efficiently, and in certain embodiments, the delaying of coding only needs a clock cycle, and the delaying of decoding only needs four clock cycle.The present invention is applicable to the recovery of the obliterated data of distributed memory system.
[accompanying drawing explanation]
Fig. 1 is the partial circuit figure of the storage system correcting and eleting codes coding circuit of an embodiment of the present invention;
Fig. 2 is the partial circuit figure of the storage system correcting and eleting codes coding circuit of an embodiment of the present invention;
Fig. 3 is the partial circuit figure of the storage system correcting and eleting codes coding circuit of an embodiment of the present invention;
Fig. 4 is the partial circuit figure of the storage system correcting and eleting codes decoding circuit of an embodiment of the present invention;
Fig. 5 is the partial circuit figure of the storage system correcting and eleting codes decoding circuit of an embodiment of the present invention;
Fig. 6 is the partial circuit figure of the storage system correcting and eleting codes decoding circuit of an embodiment of the present invention;
Fig. 7 is the partial circuit figure of the storage system correcting and eleting codes decoding circuit of an embodiment of the present invention.
[embodiment]
Below the preferred embodiment of invention is described in further detail.
As shown in Figures 1 to 3, a kind of first correcting and eleting codes coding circuit unit of storage system correcting and eleting codes coding circuit of embodiment, the second correcting and eleting codes coding circuit unit and the 3rd correcting and eleting codes coding circuit unit.First correcting and eleting codes coding circuit unit comprises input port for inputting data to be encoded D_in1 to Din_12 and output port, specifically comprise the XOR device of four three inputs, for XOR will be carried out as data to be encoded D_in1 to Din_12, obtain the first checking data dout1 and export from output port.The Galois Field multiplication that the data to be encoded that the input of each XOR device can regard corresponding input as are multiplied with coefficient 1 and obtain exports, the such as input D_in1 of one of them XOR device XOR1, can regard the Galois Field multiplication obtained after data to be encoded D_in1 is multiplied with coefficient 1 as and export.The coefficient that data to be encoded D_in1 to Din_12 is corresponding is all 1.Each data to be encoded size can be 8bit.
Equally, second correcting and eleting codes coding circuit unit and the 3rd correcting and eleting codes coding circuit unit also include the input port for inputting data to be encoded D_in1 to Din_12, and output port, specifically comprise the XOR device of four three inputs, and 11 Galois field multiplying units, each Galois field multiplying unit is used for certain data to be encoded and corresponding multiplication, obtain Galois Field multiplication export and input to corresponding XOR device, equally, the coefficient of data to be encoded D_in1 can regard 1 as, finally, second correcting and eleting codes coding circuit unit exports the second checking data dout2, the coefficient that data to be encoded D_in1 to Din_12 is corresponding is respectively: 8 ' h1, 8 ' h2, 8 ' h4, 8 ' h8, 8 ' h10, 8 ' h20, 8 ' h40, 8 ' h80, 8 ' h1d, 8 ' h3a, 8 ' h74, 8 ' he8.And in the 3rd correcting and eleting codes coding circuit unit, the coefficient that data to be encoded D_in1 to Din_12 is corresponding is respectively: 8 ' h1,8 ' h4,8 ' h10,8 ' h40,8 ' h1d, 8 ' h74,8 ' hcd, 8 ' h13,8 ' h4c, 8 ' h2d, 8 ' hb4,8 ' hea.
Wherein, as long as meeting between whole group of coefficient of any two correcting and eleting codes coding circuit unit is linear independence, above-mentioned concrete coefficient is thus not limited to.And all adopt 1 due to the coefficient of the first correcting and eleting codes coding circuit unit, namely can omit corresponding Galois field multiplying unit, thus simplify circuit structure.
In the present embodiment, each clock cycle, namely the first checking data dout1, the second checking data dout2 and the 3rd checking data dout3 can be obtained according to the data to be encoded D_in1 to Din_12 of input.
As shown in Fig. 4 to 7, the storage system correcting and eleting codes decoding circuit matched with the storage system correcting and eleting codes coding circuit of above-described embodiment, comprising: mis1 computing module, mis2 computing module, mis3 computing module, four decoding multiplier modules, four galois fields are to binary field mapping table, three subtracters and three binary fields to galois field mapping table.
As shown in Figure 3, described decoding multiplier module comprises first input end a1, the second input a2, the 3rd input a3, four-input terminal a4, the 5th input a5, the 6th input a6, the 7th input a7, the 8th input a8, the 9th input a9 and output Res_o;
Described decoding multiplier module is used for the first Galois Field multiplication value, the second Galois Field multiplication value, the 3rd Galois Field multiplication value, the 4th Galois Field multiplication value, the 5th Galois Field multiplication value and the 6th Galois Field multiplication value to carry out XOR; Wherein, described first Galois Field multiplication value is the Galois Field multiplication value of first input end a1, the 5th input a5 and the 9th input a9, second Galois Field multiplication value is the Galois Field multiplication value of the second input a2, the 6th input a6 and the 7th input a7,3rd Galois Field multiplication value is the Galois Field multiplication value of the 3rd input a3, four-input terminal a4 and the 8th input a8, and the 4th Galois Field multiplication value is the Galois Field multiplication value of the 3rd input a3, the 5th input a5 and the 7th input a7; 5th Galois Field multiplication value is the Galois Field multiplication value of the second input a2, four-input terminal a4 and the 9th input a9; 6th Galois Field multiplication value is the Galois Field multiplication value of first input end a1, the 6th input a6 and the 8th input a8.As shown in Figure 3, decoding multiplier module can adopt 12 two Galois field multiplying units inputted and 3 three input XOR device compositions, 6 three Galois field multiplying units inputted and one six input XOR device composition can certainly be adopted, equally also can realize the output of above-mentioned Res_o.
Mis1 computing module, the circuit structure of mis2 computing module and mis3 computing module respectively with the first correcting and eleting codes coding circuit unit, second correcting and eleting codes coding circuit unit is identical with the circuit structure of the 3rd correcting and eleting codes coding circuit unit, as shown in Figure 5, if certain data to be encoded is lost, then the data to be encoded of this loss are set to 0, then the mis1 computing module of correspondence position is given, in mis2 computing module and mis3 computing module, such as, D_in1 loses, then D_in1 is set to 0, and input to mis1 computing module, D_in1 input port in mis2 computing module and mis3 computing module, obtain the first intermediate data mis1 respectively, second intermediate data mis2 and the 3rd intermediate data mis3,
The 3rd checking data dout3 that the second checking data dout2 that the first checking data dout1 produced by the first correcting and eleting codes coding circuit unit that described first intermediate data mis1, the second intermediate data mis2 and the 3rd intermediate data mis3 produce with described storage system correcting and eleting codes coding circuit respectively, the second correcting and eleting codes coding circuit unit produce, the 3rd correcting and eleting codes coding circuit unit produce carries out XOR, obtains the first calculated data cnt1, the second calculated data cnt2 and the 3rd calculated data cnt3 respectively.First checking data dout1, the second checking data dout2 and the 3rd checking data dout3 input from p_in1, p_in2 and p_in3 port respectively.
As shown in Figure 7, first input end a1, the second input a2 of the first decoding multiplier module and the 3rd input a3 input the coefficient of the first correcting and eleting codes coding circuit unit corresponding to first data of losing, second data of losing and the 3rd position of data in described data to be encoded of losing respectively.Because the coefficient of the first correcting and eleting codes coding circuit unit is 1, thus first input end a1, the second input a2 and the 3rd input a3 all input 8 ' h1.Four-input terminal a4, the 5th input a5 of described first decoding multiplier module and the 6th input a6 input the coefficient of first data of losing, second data of losing and the 3rd the second correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively.Such as, the data of loss are the 1st, 2 and 3 of data to be encoded, and so four-input terminal a4, the 5th input a5 and the 6th input a6 input 8 ' h1,8 ' h2 and 8 ' h4 respectively.7th input a7, the 8th input a8 of described first decoding multiplier module and the 9th input a9 input the coefficient of first data of losing, second data of losing and the 3rd the 3rd correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively.
Second input a2 of the second decoding multiplier module and the 3rd input a3 inputs the coefficient of second data of losing and the 3rd the first correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively, and both are 8 ' h1 in the present embodiment.5th input a5 of described second decoding multiplier module and the 6th input a6 inputs the coefficient of second data of losing and the 3rd the second correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively.8th input a8 of described second decoding multiplier module and the 9th input a9 inputs the coefficient of second data of losing and the 3rd the 3rd correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively.First input end a1, the four-input terminal a4 of the second decoding multiplier module and the 7th input a7 input described first calculated data cnt1, the second calculated data cnt2 and the 3rd calculated data cnt3 respectively.
The first input end a1 of the 3rd decoding multiplier module and the 3rd input a3 inputs the coefficient of first data of losing and the 3rd the first correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively, in the present embodiment, both are 8 ' h1.The four-input terminal a4 of described 3rd decoding multiplier module and the 6th input a6 inputs the coefficient of first data of losing and the 3rd the second correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively; 7th input a7 of described 3rd decoding multiplier module and the 9th input a9 inputs the coefficient of first data of losing and the 3rd the 3rd correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively; Second input a2, the 5th input a5 of the 3rd decoding multiplier module and the 8th input a8 input described first calculated data cnt1, the second calculated data cnt2 and the 3rd calculated data cnt3 respectively.
The first input end a1 of the 4th decoding multiplier module and the second input a2 inputs the coefficient of first data of losing and second the first correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively, in the present embodiment, both are 8 ' h1.The four-input terminal a4 of described 4th decoding multiplier module and the 5th input a5 inputs the coefficient of first data of losing and second the second correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively; 7th input a7 of described 4th decoding multiplier module and the 8th input a8 inputs the coefficient of first data of losing and second the 3rd correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively; Four-input terminal a4, the 6th input a6 of the 4th decoding multiplier module and the 9th input a9 input described first calculated data cnt1, the second calculated data cnt2 and the 3rd calculated data cnt3 respectively.
As shown in Figure 6, M road selector is used for will the positional information of obliterated data in described data to be encoded of input, exports as the coefficient of the correcting and eleting codes coding circuit unit of correspondence is to the corresponding input of decoding multiplier module; Wherein, M is the number of data to be encoded.In the present embodiment, M is 12, and therefore three are No. 12 selectors.Because all coefficients of the first correcting and eleting codes coding circuit unit are 8 ' h1, therefore, output a1, a2 and a3 of the one No. 12 selector always 1, therefore, can omit the one No. 12 selector.When first, the data to be encoded position of losing, second and the 3rd time, so, a4, a5, a6 of the two No. 12 selector export the first to three coefficient being respectively the second correcting and eleting codes coding circuit unit: 8 ' h1,8 ' h2,8 ' h4.And output a7, a8 and a9 of the three No. 12 selector export the first to three coefficient being respectively the 3rd correcting and eleting codes coding circuit unit: 8 ' h1,8 ' h4,8 ' h10.
Galois field is used for galois field value to be mapped as binary value to binary field mapping table, and specific implementation can be: using galois field value as address, and the storing value of correspondence is binary value, and ram can be utilized to realize.First galois field is to binary field mapping table, second galois field is to binary field mapping table, 3rd galois field to binary field mapping table and the 4th galois field to the input of binary field mapping table respectively with the output Res_o1 of the first decoding multiplier module, the output Res_o2 of the second decoding multiplier module, the output Res_o3 of the 3rd decoding multiplier module is connected with the output Res_o4 of the 4th decoding multiplier module, described first subtracter is used for described second galois field to deduct the output gf1 of the first galois field to binary field mapping table to the output gf2 of binary field mapping table, described second subtracter is used for described 3rd galois field to deduct the output gf1 of the first galois field to binary field mapping table to the output gf3 of binary field mapping table, described 3rd subtracter is used for described 4th galois field to deduct the output gf1 of the first galois field to binary field mapping table to the output gf4 of binary field mapping table.
Described first binary field is to galois field mapping table, second binary field to galois field mapping table and the 3rd binary field to the input of galois field mapping table respectively with the output Dec_addr1 of described first subtracter, the output Dec_addr2 of the second subtracter is connected with the output Dec_addr3 of the 3rd subtracter, first binary field is to the output rec1 of galois field mapping table, namely second binary field is respectively three data of losing successively to the output rec2 of galois field mapping table and the 3rd binary field to the output rec3 of galois field mapping table, what such as lose is first to the 3rd data to be encoded, then rec1, rec2 and rec3 is respectively first to the 3rd data to be encoded.
In the present embodiment, according to the feature of correcting and eleting codes 12+3, during retaking of a year or grade, only need retaking of a year or grade 12 data to be encoded and 3 checking datas, 12 in 15 data, just can whole 15 data to be encoded full recoveries.
Extra, this circuit converts a little, even if some or all checking data is lost, also can utilize M data in M data to be encoded and three common M+3 data of checking data, total data be recovered.In the present embodiment, data to be encoded D_in1 to Din_12, dout1, dout2 and dout3 are arranged in order composition array, also namely these 3 checking datas of dout1, dout2 and dout3 are regarded as d_in13, d_in14, d_in15 successively.No. 12 selectors are become No. 15 selectors, and losing and now lose position can be 1 ~ 15.First No. 15 selector can not be omitted.In the present embodiment, 3 and coefficient corresponding to checking data can be increased after three No. 12 selectors, be respectively:
Former one No. 12 selector coefficient: (be entirely 1 can omit)
8’h1,8’h1,8’h1,8’h1,8’h1,8’h1,8’h1,8’h1,8’h1,8’h1,8’h1,8’h1,
Change now the one No. 15 selector coefficient into: (newly-increased 3, be not now 1 entirely, can not omit) below
8’h1,8’h1,8’h1,8’h1,8’h1,8’h1,8’h1,8’h1,8’h1,8’h1,8’h1,8’h1,8’h1,8’h0,8’h0
Former two No. 12 selector coefficient:
8’h1,8’h2,8’h4,8’h8,8’h10,8’h20,8’h40,8’h80,8’h1d,8’h3a,8’h74,8’he8。
Change now the two No. 15 selector coefficient into: (below newly-increased 3)
8’h1,8’h2,8’h4,8’h8,8’h10,8’h20,8’h40,8’h80,8’h1d,8’h3a,8’h74,8’he8，8’h0,8’h1,8’h0。
Former two No. 12 selector coefficient:
8’h1,8’h4,8’h10,8’h40,8’h1d,8’h74,8’hcd,8’h13,8’h4c,8’h2d,8’hb4,8’hea。
Change now the three No. 15 selector coefficient into: (below newly-increased 3)
8’h1,8’h4,8’h10,8’h40,8’h1d,8’h74,8’hcd,8’h13,8’h4c,8’h2d,8’hb4,8’hea 8’h0,8’h0,8’h1。
For above-mentioned array, if 13rd, 14 and 15 bit data are lost, namely the first checking data dout1, the second checking data dout2 and the 3rd checking data dout3 lose, and so output a1, a2 and a3 of the one No. 15 selector are then 8 ' h1,8 ' h0,8 ' h0.
Above content is in conjunction with concrete preferred implementation further description made for the present invention, can not assert that specific embodiment of the invention is confined to these explanations.For general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, some simple deduction or replace can also be made, all should be considered as belonging to the scope of patent protection that the present invention is determined by submitted to claims.
Claims (9)
1. a storage system correcting and eleting codes coding circuit, it is characterized in that, comprise three correcting and eleting codes coding circuit unit, described correcting and eleting codes coding circuit unit comprises input port for inputting data to be encoded and output port, described correcting and eleting codes coding circuit is used for the data to be encoded of input to be multiplied with coefficient of correspondence Galois Field multiplication, obtain Galois Field multiplication to export, and XOR is carried out in multiple Galois Field multiplication output, obtain checking data, linear independence between the coefficient of any two correcting and eleting codes coding circuit unit.
2. storage system correcting and eleting codes coding circuit as claimed in claim 1, it is characterized in that, described three correcting and eleting codes coding circuit unit are the first correcting and eleting codes coding circuit unit, the second correcting and eleting codes coding circuit unit and the 3rd correcting and eleting codes coding circuit unit;
Described first correcting and eleting codes coding circuit unit has XOR device, and in described first correcting and eleting codes coding circuit unit, described Galois Field multiplication exports the described data to be encoded for input;
Described second correcting and eleting codes coding circuit unit has XOR device and Galois field multiplying unit, in described second correcting and eleting codes coding circuit unit, the described Galois Field multiplication of a part exports and the data to be encoded of the correspondence of input and corresponding coefficient is carried out being multiplied obtaining by described Galois field multiplying unit, and a part of described Galois Field multiplication exports as corresponding data to be encoded;
Described 3rd correcting and eleting codes coding circuit unit has XOR device and Galois field multiplying unit, in described 3rd correcting and eleting codes coding circuit unit, the described Galois Field multiplication of a part exports and the data to be encoded of the correspondence of input and corresponding coefficient is carried out being multiplied obtaining by described Galois field multiplying unit, and a part of described Galois Field multiplication exports as corresponding data to be encoded.
3. the storage system correcting and eleting codes decoding circuit coordinated with storage system correcting and eleting codes coding circuit according to claim 1, it is characterized in that, comprise: the first correcting and eleting codes coding circuit unit, the second correcting and eleting codes coding circuit unit, the 3rd correcting and eleting codes coding circuit unit and two decoding multiplier modules, described decoding multiplier module comprises first input end, the second input, the 3rd input, four-input terminal, the 5th input, the 6th input, the 7th input, the 8th input, the 9th input and output;
Described decoding multiplier module is used for the first Galois Field multiplication value, the second Galois Field multiplication value, the 3rd Galois Field multiplication value, the 4th Galois Field multiplication value, the 5th Galois Field multiplication value and the 6th Galois Field multiplication value to carry out XOR; Wherein, described first Galois Field multiplication value is the Galois Field multiplication value of first input end, the 5th input and the 9th input, second Galois Field multiplication value is the Galois Field multiplication value of the second input, the 6th input and the 7th input, 3rd Galois Field multiplication value is the Galois Field multiplication value of the 3rd input, four-input terminal and the 8th input, and the 4th Galois Field multiplication value is the Galois Field multiplication value of the 3rd input, the 5th input and the 7th input; 5th Galois Field multiplication value is the Galois Field multiplication value of the second input, four-input terminal and the 9th input; 6th Galois Field multiplication value is the Galois Field multiplication value of first input end, the 6th input and the 8th input;
The data of losing in described data to be encoded are substituted with zero, input the first correcting and eleting codes coding circuit unit of described storage system correcting and eleting codes decoding circuit, the second correcting and eleting codes coding circuit unit and the 3rd correcting and eleting codes coding circuit unit respectively, obtain the first intermediate data, the second intermediate data and the 3rd intermediate data respectively;
The 3rd checking data XOR that the second checking data that the first checking data produced by the first correcting and eleting codes coding circuit unit that described first intermediate data, the second intermediate data and the 3rd intermediate data produce with described storage system correcting and eleting codes coding circuit respectively, the second correcting and eleting codes coding circuit unit produce, the 3rd correcting and eleting codes coding circuit unit produce, obtains the first calculated data, the second calculated data and the 3rd calculated data respectively;
The first input end of the first decoding multiplier module, the second input and the 3rd input input the coefficient of the first correcting and eleting codes coding circuit unit corresponding to first data of losing, second data of losing and the 3rd position of data in described data to be encoded of losing respectively; The four-input terminal of described first decoding multiplier module, the 5th input and the 6th input input the coefficient of the second correcting and eleting codes coding circuit unit corresponding to first data of losing, second data of losing and the 3rd position of data in described data to be encoded of losing respectively; 7th input of described first decoding multiplier module, the 8th input and the 9th input input the coefficient of the 3rd correcting and eleting codes coding circuit unit corresponding to first data of losing, second data of losing and the 3rd position of data in described data to be encoded of losing respectively;
Second input of the second decoding multiplier module and the 3rd input input the coefficient of second data of losing and the 3rd the first correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively; 5th input of described second decoding multiplier module and the 6th input input the coefficient of second data of losing and the 3rd the second correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively; 8th input of described second decoding multiplier module and the 9th input input the coefficient of second data of losing and the 3rd the 3rd correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively; The first input end of the second decoding multiplier module, four-input terminal and the 7th input input described first calculated data, the second calculated data and the 3rd calculated data respectively.
4. storage system correcting and eleting codes decoding circuit as claimed in claim 3, is characterized in that, also comprise the 3rd decoding multiplier module and the 4th decoding multiplier module;
The first input end of described 3rd decoding multiplier module and the 3rd input input the coefficient of first data of losing and the 3rd the first correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively; The four-input terminal of described 3rd decoding multiplier module and the 6th input input the coefficient of first data of losing and the 3rd the second correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively; 7th input of described 3rd decoding multiplier module and the 9th input input the coefficient of first data of losing and the 3rd the 3rd correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively; Second input of the 3rd decoding multiplier module, the 5th input and the 8th input input described first calculated data, the second calculated data and the 3rd calculated data respectively;
The first input end of described 4th decoding multiplier module and the second input input the coefficient of first data of losing and second the first correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively; The four-input terminal of described 4th decoding multiplier module and the 5th input input the coefficient of first data of losing and second the second correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively; 7th input of described 4th decoding multiplier module and the 8th input input the coefficient of first data of losing and second the 3rd correcting and eleting codes coding circuit unit corresponding to the position of data in described data to be encoded lost respectively; The four-input terminal of the 4th decoding multiplier module, the 6th input and the 9th input input described first calculated data, the second calculated data and the 3rd calculated data respectively.
5. storage system correcting and eleting codes decoding circuit as claimed in claim 4, it is characterized in that, also comprise the first galois field to binary field mapping table, second galois field is to binary field mapping table, 3rd galois field is to binary field mapping table, 4th galois field is to binary field mapping table, first subtracter, second subtracter and the 3rd subtracter, described first galois field is to binary field mapping table, second galois field is to binary field mapping table, 3rd galois field to binary field mapping table and the 4th galois field to the input of binary field mapping table respectively with the first decoding multiplier module, second decoding multiplier module, 3rd decoding multiplier module is connected with the output of the 4th decoding multiplier module, described first subtracter is used for described second galois field to deduct the output of the first galois field to binary field mapping table to the output of binary field mapping table, described second subtracter is used for described 3rd galois field to deduct the output of the first galois field to binary field mapping table to the output of binary field mapping table, described 3rd subtracter is used for described 4th galois field to deduct the output of the first galois field to binary field mapping table to the output of binary field mapping table.
6. storage system correcting and eleting codes decoding circuit as claimed in claim 5, it is characterized in that, also comprise the first binary field to galois field mapping table, the second binary field to galois field mapping table and the 3rd binary field to galois field mapping table, described first binary field is connected with the output of described first subtracter, the second subtracter and the 3rd subtracter with the input of the 3rd binary field to galois field mapping table to galois field mapping table, the second binary field respectively to galois field mapping table.
7. storage system correcting and eleting codes decoding circuit as claimed in claim 4, it is characterized in that, also comprise at least two M road selectors, M road selector is used for will the positional information of obliterated data in described data to be encoded of input, exports as the coefficient of the correcting and eleting codes coding circuit unit of correspondence is to the corresponding input of decoding multiplier module; Wherein, M is the number of data to be encoded.
8. storage system correcting and eleting codes decoding circuit as claimed in claim 4, is characterized in that,
M data to be encoded, the first checking data, the second checking data and the 3rd checking data are arranged in order the array of composition M+3 data; Coefficient in first group of coefficient that M+3 data of described data are corresponding is followed successively by en1_1, en1_2 ... en1_M, 8 ' h1,8 ' h0,8 ' h0; Coefficient in second group of coefficient that M+3 data of described data are corresponding is followed successively by en2_1, en2_2 ... en2_M, 8 ' h0,8 ' h1,8 ' h0; Coefficient in the 3rd group of coefficient that M+3 data of described data are corresponding is followed successively by en3_1, en3_2 ... en3_M, 8 ' h0,8 ' h0,8 ' h1; Wherein, en1_1, en1_2 ... en1_M is followed successively by coefficient corresponding to M data to be encoded of the first correcting and eleting codes coding circuit unit, en2_1, en2_2 ... en2_M is followed successively by coefficient corresponding to M data to be encoded of the first correcting and eleting codes coding circuit unit, en3_1, en3_2 ... en3_M is followed successively by coefficient corresponding to M data to be encoded of the first correcting and eleting codes coding circuit unit;
If certain loss of data in described array, substitute the data of described loss with zero;
The first input end of the first decoding multiplier module, the second input and the 3rd input input the coefficient of first data of losing, second data of losing and the 3rd data of the losing first group coefficient corresponding in the position of described array respectively; The four-input terminal of described first decoding multiplier module, the 5th input and the 6th input input the coefficient of second group of coefficient corresponding to first data of losing, second data of losing and the 3rd position of data in described array of losing respectively; 7th input of described first decoding multiplier module, the 8th input and the 9th input input the coefficient of first data of losing, second data of losing and the 3rd data of the losing three group coefficient corresponding in the position of described array respectively;
Second input of the second decoding multiplier module and the 3rd input input the coefficient of second data of losing and the 3rd first group of coefficient corresponding to the position of data in described array lost respectively; 5th input of described second decoding multiplier module and the 6th input input the coefficient of second data of losing and the 3rd second group of coefficient corresponding to the position of data in described array lost respectively; 8th input of described second decoding multiplier module and the 9th input input the coefficient of second data of losing and the 3rd the 3rd group of coefficient corresponding to the position of data in described array lost respectively;
The first input end of described 3rd decoding multiplier module and the 3rd input input the coefficient of first data of losing and the 3rd first group of coefficient corresponding to the position of data in described array lost respectively; The four-input terminal of described 3rd decoding multiplier module and the 6th input input the coefficient of first data of losing and the 3rd second group of coefficient corresponding to the position of data in described array lost respectively; 7th input of described 3rd decoding multiplier module and the 9th input input the coefficient of first data of losing and the 3rd the 3rd group of coefficient corresponding to the position of data in described array lost respectively;
The first input end of described 4th decoding multiplier module and the second input input the coefficient of first data of losing and second first group of coefficient corresponding to the position of data in described array lost respectively; The four-input terminal of described 4th decoding multiplier module and the 5th input input the coefficient of first data of losing and second second group of coefficient corresponding to the position of data in described array lost respectively; 7th input of described 4th decoding multiplier module and the 8th input input the coefficient of first data of losing and second the 3rd group of coefficient corresponding to the position of data in described array lost respectively.
9. a storage system correcting and eleting codes coding-decoding circuit, is characterized in that, comprises storage system correcting and eleting codes coding circuit as claimed in claim 1 and storage system correcting and eleting codes decoding circuit according to claim 3.
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