CN107947902A - The data error processing system and method for a kind of high-speed interface chip - Google Patents
The data error processing system and method for a kind of high-speed interface chip Download PDFInfo
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- CN107947902A CN107947902A CN201711260898.6A CN201711260898A CN107947902A CN 107947902 A CN107947902 A CN 107947902A CN 201711260898 A CN201711260898 A CN 201711260898A CN 107947902 A CN107947902 A CN 107947902A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
Abstract
The invention discloses the data error processing system and method for a kind of high-speed interface chip, it realizes that process is：Configuration codes algorithm first, ECC encryption algorithms and BCH decoding error correction algorithms are combined, i.e., embedded BCH decodings error correction algorithm in ECC encryption algorithms；Then the data encoding in high-speed interface chip, error correction are checked whether to need BCH to decode by encryption algorithm；Finally the data after processing are continued to handle by high-speed interface chip internal.The data error processing system and method for a kind of high-speed interface chip of the present invention compared with prior art, by the embedded BCH code error correction algorithm in ECC algorithm, it is poor to solve conventional error correction algorithm error correcting capability, the problem of decoding is complicated and time-consuming, it is highly practical, it is applied widely, it is easy to spread.
Description
Technical field
The present invention relates to microelectronic, specifically a kind of data difference fault of highly practical high-speed interface chip
Manage system and method.
Background technology
With the arrival of information age and the development of electronic technology, in Information Technology Development rapid today, people are not
It is disconnected to pursue mass memory capacity, high-performance, high security, high availability, scalability, manageability etc..In electronics, microelectronics
And the communications field, the characteristics of one prominent in recent years are exactly the growing day by day of volume of transmitted data, this is also to the interface tackled therewith
Chip proposes the requirement of higher, the opportunity also occurred as a large amount of high-speed interface chips.
And data during storage either transmission due to interference or the reason such as hardware fault there is a possibility that transmission
Data produce certain error, therefore, improve reliability, correctness and the uniformity of information storage and transmission, and can in time into
The verification of correctness and Fault recovery of row data are very necessary.
Error-correcting code technique is currently a kind of important and necessary means for improving information transmission reliability and accuracy.Number at present
There are even-odd check, CRC check, FEC, repetition code check, ECC, Hamming code, RS codes and BCH code etc. according to the inspection common method of error correction
Deng.
But current error-correcting code technique is all there are certain shortcoming, such as the error correcting capability of ECC error correction algorithm are poor,
Mistake more than 1 bit can not be corrected, mistakes more than 2 bits is not ensured to be detected；Calculated based on RS codes and BCH code error correction
The decoding of method takes long；And odd-even check, CRC check etc. do not have error correction.
Based on this, conventional error correction algorithm error correcting capability difference or time-consuming new correction process skill can be solved there is an urgent need for a kind of
Art.
The content of the invention
The technical assignment of the present invention is to be directed to above shortcoming, there is provided a kind of number of highly practical high-speed interface chip
According to error handling system and method.
A kind of data error processing system of high-speed interface chip, including：
Data coding module, error correction algorithm, the data to be sent to high-speed interface chip are decoded by ECC encryption algorithms and BCH
Encoded；
Data processing module, by ECC encryption algorithms, the data to be sent to high-speed interface chip carry out error correction, are translated by BCH
The data that needs decode are carried out BCH decodings by code error correction algorithm；
Data transmission module, for the data sending after data coding module is encoded to correcting data error module, and will be through data
Data transfer to high-speed interface chip internal after correction module processing is handled.
The data coding module, data processing module are mutually tied by the way that ECC encryption algorithms are decoded error correction algorithm with BCH
Close and realize, i.e., the embedded BCH decodings error correction algorithm in ECC encryption algorithms, when data coding module is to data encoding to be sent,
ECC codings are carried out first, and the data after ECC is encoded then are subjected to Bose-Chaudhuri-Hocquenghem Code again, finally again will be through by data transmission module
Data transfer after Bose-Chaudhuri-Hocquenghem Code carries out error-correcting decoding processing to data processing module.
The detailed process that the data coding module encodes data to be sent is：
ECC codings are carried out first：By packet to be sent, every 256 B data is one group；Then 256 B datas are regarded as
The matrix of 256x8, one bit of each element representation of matrix；Matrix is encoded, matrix is given birth to respectively after being encoded
Into the row check information of 6bit and the row check information of 16bit, the i.e. check code of 22bit；
Then Bose-Chaudhuri-Hocquenghem Code is carried out：Data after ECC is encoded are grouped, and are one group of carry out Bose-Chaudhuri-Hocquenghem Code by every 256 B data；
Then 256 B datas are regarded as the matrix of 256x8, one bit of each element representation of matrix；Compiled using 8 parallel-by-bit BCH
Code algorithm, i.e., calculate per 8bit at the same time as one group, by information bit be calculated verification and, by information bit and verification and jointly
Form one group of BCH code.
The data processing module is to the process of correcting data error：The data after coding are grouped first, by every 256
B data is one group, and the check code of 22bit is equally generated with ECC codings；Stored when then by the check code of acquisition and transmission data
Check code carry out step-by-step xor operation；When the result that xor operation obtains is 0, then mistake is not present in data；When exclusive or is grasped
Value in the result for making to obtain there are 11bit is 1, then there are a bit-errors, and is corrected；Obtained when xor operation
When as a result only existing 1bit mistakes, then the check code generated malfunctions, and mistake is not present in data；When the result that xor operation obtains is
Then there are multi-bit errors in other situations, can not correct, it is necessary to carry out BCH decodings.
The data transmission module includes transmitting terminal interface unit, the receiving terminal interface unit of high-speed interface chip, relatively
Answer, data coding module is connected with transmitting terminal interface unit communications, and data processing module connects with receiving terminal interface unit communications
Connect；Data after data coding module coding are sent by transmitting terminal interface unit, are transferred to after being received by receiving terminal interface unit
Data processing module processing.
A kind of data error processing method of high-speed interface chip, it realizes that process is：
First, configuration codes algorithm first, ECC encryption algorithms and BCH decoding error correction algorithms is combined, i.e., in ECC encryption algorithms
Embedded BCH decodings error correction algorithm；
Two then by encryption algorithm to the data encoding in high-speed interface chip, error correction, check whether to need BCH to decode；
3rd, finally the data after step 2 is handled are continued to handle by high-speed interface chip internal.
It is to the process of data code correction in the step 2：First ECC codings are carried out to sent data order
And Bose-Chaudhuri-Hocquenghem Code, then the transmission end interface through high-speed interface chip send, the reception end interface of high-speed interface chip receives
ECC error correction is carried out after data.
Carrying out ECC cataloged procedures to sent data is：
First by packet to be sent, every 256 B data is one group；
Then 256 B datas are regarded as the matrix of 256x8, one bit of each element representation of matrix；
Matrix is encoded, matrix generates the row check information of 6bit and the row check information of 16bit respectively after being encoded,
That is the check code of 22bit.
Carry out carrying out the process of Bose-Chaudhuri-Hocquenghem Code again after ECC codings to sent data be：
Data after ECC is encoded are grouped, and are one group of carry out Bose-Chaudhuri-Hocquenghem Code by every 256 B data；
Then 256 B datas are regarded as the matrix of 256x8, one bit of each element representation of matrix；
Using 8 parallel-by-bit Bose-Chaudhuri-Hocquenghem Code algorithms, i.e., calculated at the same time as one group per 8bit, by information bit be calculated verification and,
By information bit and verification and collectively constitute one group of BCH code；
Sent after the completion of Bose-Chaudhuri-Hocquenghem Code from the transmission end interface of high-speed interface chip.
It is to the detailed process of correcting data error in step 2：
1）After the receiving terminal of high-speed interface chip receives data, it is grouped first into being about to data, is one by every 256 B data
Group, the check code of 22bit is equally generated with ECC codings；
2）By step 1）In check code and the check code that stores carries out step-by-step xor operation when sending data；
3）When the result that xor operation obtains is 0, then mistake is not present in data；
4）When in the result that xor operation obtains there are 11bit value be 1, then there are a bit-errors, and corrected；
5）When the result that xor operation obtains only exists 1bit mistakes, then the check code generated malfunctions, and mistake is not present in data；
6）When the result that xor operation obtains multi-bit errors then occurs for other situations, can not correct, and indicate to need to carry out
BCH is decoded.
The present invention a kind of high-speed interface chip data error processing system and method compared to the prior art, have with
Lower beneficial effect：
The data error processing system and method for a kind of high-speed interface chip of the present invention, are calculated quick based on ECC encryption algorithms
Feature and the controllable random error correcting capability of BCH code are strong, and two kinds of algorithms are combined and solve conventional error correction algorithm error correcting capability
The problem of poor, can correct the more bit random errors occurred in high-speed interface chip data transmission；Overcome tradition and be based on BCH
The problem of code or complicated and time-consuming RS codes error correction algorithm decoding, the reliability and accuracy of data transfer are improved, it is highly practical,
It is applied widely, it is easy to spread.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is attached drawing needed in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
The embodiment of invention, for those of ordinary skill in the art, without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Attached drawing 1 is the structure diagram of present system.
Attached drawing 2 realizes flow chart for the method for the present invention.
Embodiment
In order to make those skilled in the art more fully understand the solution of the present invention, with reference to embodiment to this
Invention is described in further detail.Obviously, described embodiment is only part of the embodiment of the present invention, rather than all
Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art institute without making creative work
The every other embodiment obtained, belongs to the scope of protection of the invention.
As shown in Figure 1, a kind of data error processing system of high-speed interface chip, including：
Data coding module, error correction algorithm, the data to be sent to high-speed interface chip are decoded by ECC encryption algorithms and BCH
Encoded；
Data processing module, by ECC encryption algorithms, the data to be sent to high-speed interface chip carry out error correction, are translated by BCH
The data that needs decode are carried out BCH decodings by code error correction algorithm；
Data transmission module, for the data sending after data coding module is encoded to correcting data error module, and will be through data
Data transfer to high-speed interface chip internal after correction module processing is handled.
The data coding module, data processing module are mutually tied by the way that ECC encryption algorithms are decoded error correction algorithm with BCH
Close and realize, i.e., the embedded BCH decodings error correction algorithm in ECC encryption algorithms, when data coding module is to data encoding to be sent,
ECC codings are carried out first, and the data after ECC is encoded then are subjected to Bose-Chaudhuri-Hocquenghem Code again, finally again will be through by data transmission module
Data transfer after Bose-Chaudhuri-Hocquenghem Code carries out error-correcting decoding processing to data processing module.
The detailed process that the data coding module encodes data to be sent is：
ECC codings are carried out first：By packet to be sent, every 256 B data is one group；Then 256 B datas are regarded as
The matrix of 256x8, one bit of each element representation of matrix；Matrix is encoded, matrix is given birth to respectively after being encoded
Into the row check information of 6bit and the row check information of 16bit, the i.e. check code of 22bit；
Then Bose-Chaudhuri-Hocquenghem Code is carried out：Data after ECC is encoded are grouped, and are one group of carry out Bose-Chaudhuri-Hocquenghem Code by every 256 B data；
Then 256 B datas are regarded as the matrix of 256x8, one bit of each element representation of matrix；Compiled using 8 parallel-by-bit BCH
Code algorithm, i.e., calculate per 8bit at the same time as one group, by information bit be calculated verification and, by information bit and verification and jointly
Form one group of BCH code.
The data processing module is to the process of correcting data error：The data after coding are grouped first, by every 256
B data is one group, and the check code of 22bit is equally generated with ECC codings；Stored when then by the check code of acquisition and transmission data
Check code carry out step-by-step xor operation；When the result that xor operation obtains is 0, then mistake is not present in data；When exclusive or is grasped
Value in the result for making to obtain there are 11bit is 1, then there are a bit-errors, and is corrected；Obtained when xor operation
When as a result only existing 1bit mistakes, then the check code generated malfunctions, and mistake is not present in data；When the result that xor operation obtains is
Then there are multi-bit errors in other situations, can not correct, it is necessary to carry out BCH decodings.
The data transmission module includes transmitting terminal interface unit, the receiving terminal interface unit of high-speed interface chip, relatively
Answer, data coding module is connected with transmitting terminal interface unit communications, and data processing module connects with receiving terminal interface unit communications
Connect；Data after data coding module coding are sent by transmitting terminal interface unit, are transferred to after being received by receiving terminal interface unit
Data processing module processing.
As shown in Figure 2, a kind of data error processing method of high-speed interface chip, in the method, high-speed interface core
Piece first carries out ECC codings and Bose-Chaudhuri-Hocquenghem Code to sent data, is then sent through sending end interface；High-speed interface chip
Receiving terminal carries out ECC error correction after receiving data；High-speed interface chip receiving terminal indicates whether to carry out BCH according to ECC error correction result
Decoding；High-speed interface chip is further to the data after corrected processing to be handled.
Based on foregoing description, the process of realizing of this method is：
First, configuration codes algorithm first, ECC encryption algorithms and BCH decoding error correction algorithms is combined, i.e., in ECC encryption algorithms
Embedded BCH decodings error correction algorithm；
Two then by encryption algorithm to the data encoding in high-speed interface chip, error correction, check whether to need BCH to decode；
3rd, finally the data after step 2 is handled are continued to handle by high-speed interface chip internal.
It is to the process of data code correction in the step 2：First ECC codings are carried out to sent data order
And Bose-Chaudhuri-Hocquenghem Code, then the transmission end interface through high-speed interface chip send, the reception end interface of high-speed interface chip receives
ECC error correction is carried out after data.
Carrying out ECC cataloged procedures to sent data is：
First by packet to be sent, every 256 B data is one group；
Then 256 B datas are regarded as the matrix of 256x8, one bit of each element representation of matrix；
Matrix is encoded, matrix generates the row check information of 6bit and the row check information of 16bit respectively after being encoded,
That is the check code of 22bit.
Carry out carrying out the process of Bose-Chaudhuri-Hocquenghem Code again after ECC codings to sent data be：
Data after ECC is encoded are grouped, and are one group of carry out Bose-Chaudhuri-Hocquenghem Code by every 256 B data；
Then 256 B datas are regarded as the matrix of 256x8, one bit of each element representation of matrix；
Since Bose-Chaudhuri-Hocquenghem Code is actually to carry out arithmetic operation to binary serial bit stream, if calculated using traditional Bose-Chaudhuri-Hocquenghem Code
Method, treatment effeciency is very low, and the present invention proposes one kind and uses 8 parallel-by-bit Bose-Chaudhuri-Hocquenghem Code algorithms, i.e., is counted at the same time as one group per 8bit
Calculate, this computing technique is more mature, therefore details are not described herein.Coding is the mistake that verification sum is calculated by information bit
Journey, information bit and verification and collectively constitute one group of BCH code.Sent after the completion of Bose-Chaudhuri-Hocquenghem Code from high-speed interface chip transmitting terminal.
It is to the detailed process of correcting data error in step 2：
1）After the receiving terminal of high-speed interface chip receives data, it is grouped first into being about to data, is one by every 256 B data
Group, the check code of 22bit is equally generated with ECC codings；
2）By step 1）In check code and the check code that stores carries out step-by-step xor operation when sending data；
3）When the result that xor operation obtains is 0, then mistake is not present in data；
4）When in the result that xor operation obtains there are 11bit value be 1, then there are a bit-errors, and corrected；
5）When the result that xor operation obtains only exists 1bit mistakes, then the check code generated malfunctions, and mistake is not present in data；
6）When the result that xor operation obtains multi-bit errors then occurs for other situations, can not correct, and indicate to need to carry out
BCH is decoded.
BCH decodings process can use existing process, i.e., calculated by syndrome, solve error location polynomial, Search Error
The three step compositions in position and error correction.Improved encoding and decoding algorithm is all to be compiled code operation by unit of one group of BCH code, can
Effectively to shorten extra delay, data-handling efficiency is improved.
The data received are by detecting and transferring to high-speed interface chip internal module to be further processed after correction process.
The foregoing is merely presently preferred embodiments of the present invention, scope of patent protection of the invention includes but not limited to above-mentioned tool
Body embodiment, within the spirit and principles of the invention, any modification, equivalent substitution, improvement and etc. done, should all include
Within the scope of patent protection of the present invention.
By embodiment above, the those skilled in the art can readily realize the present invention.Herein
Apply specific case to be set forth the principle of the present invention and embodiment, the explanation of above example is only intended to help
Understand the method and its core concept of the present invention.It should be pointed out that for those skilled in the art, do not taking off
On the premise of from the principle of the invention, some improvement and modification can also be carried out to the present invention, these are improved and modification also falls into this
In invention scope of the claims.
Claims (10)
- A kind of 1. data error processing system of high-speed interface chip, it is characterised in that including：Data coding module, error correction algorithm, the data to be sent to high-speed interface chip are decoded by ECC encryption algorithms and BCH Encoded；Data processing module, by ECC encryption algorithms, the data to be sent to high-speed interface chip carry out error correction, are translated by BCH The data that needs decode are carried out BCH decodings by code error correction algorithm；Data transmission module, for the data sending after data coding module is encoded to correcting data error module, and will be through data Data transfer to high-speed interface chip internal after correction module processing is handled.
- A kind of 2. data error processing system of high-speed interface chip according to claim 1, it is characterised in that the number Realization is combined by the way that ECC encryption algorithms and BCH are decoded error correction algorithm according to coding module, data processing module, i.e., in ECC Embedded BCH decodings error correction algorithm, when data coding module is to data encoding to be sent, carries out ECC volumes first in encryption algorithm Then data after ECC is encoded are carried out Bose-Chaudhuri-Hocquenghem Code by code again, finally again by data transmission module by the number after Bose-Chaudhuri-Hocquenghem Code Error-correcting decoding processing is carried out according to data processing module is transferred to.
- A kind of 3. data error processing system of high-speed interface chip according to claim 2, it is characterised in that the number The detailed process encoded according to coding module to data to be sent is：ECC codings are carried out first：By packet to be sent, every 256 B data is one group；Then 256 B datas are regarded as The matrix of 256x8, one bit of each element representation of matrix；Matrix is encoded, matrix is given birth to respectively after being encoded Into the row check information of 6bit and the row check information of 16bit, the i.e. check code of 22bit；Then Bose-Chaudhuri-Hocquenghem Code is carried out：Data after ECC is encoded are grouped, and are one group of carry out Bose-Chaudhuri-Hocquenghem Code by every 256 B data； Then 256 B datas are regarded as the matrix of 256x8, one bit of each element representation of matrix；Compiled using 8 parallel-by-bit BCH Code algorithm, i.e., calculate per 8bit at the same time as one group, by information bit be calculated verification and, by information bit and verification and jointly Form one group of BCH code.
- A kind of 4. data error processing system of high-speed interface chip according to claim 2, it is characterised in that the number It is to the process of correcting data error according to processing module：The data after coding are grouped first, are one group by every 256 B data, The check code of 22bit is equally generated with ECC codings；The check code stored when then by the check code of acquisition and transmission data carries out Step-by-step xor operation；When the result that xor operation obtains is 0, then mistake is not present in data；When the result that xor operation obtains The middle value there are 11bit is 1, then there are a bit-errors, and is corrected；When the result that xor operation obtains only exists During 1bit mistakes, then the check code generated malfunctions, and mistake is not present in data；When the result that xor operation obtains for other situations then There are multi-bit errors, can not correct, it is necessary to carry out BCH decodings.
- 5. according to a kind of data error processing system of any high-speed interface chips of claim 1-4, it is characterised in that The data transmission module includes transmitting terminal interface unit, the receiving terminal interface unit of high-speed interface chip, corresponding, data Coding module is connected with transmitting terminal interface unit communications, and data processing module is connected with receiving terminal interface unit communications；Data are compiled Data after code module coding are sent by transmitting terminal interface unit, and data processing mould is transferred to after being received by receiving terminal interface unit Block processing.
- 6. a kind of data error processing method of high-speed interface chip, it is characterised in that it realizes that process is：First, configuration codes algorithm first, ECC encryption algorithms and BCH decoding error correction algorithms is combined, i.e., in ECC encryption algorithms Embedded BCH decodings error correction algorithm；Two then by encryption algorithm to the data encoding in high-speed interface chip, error correction, check whether to need BCH to decode；3rd, finally the data after step 2 is handled are continued to handle by high-speed interface chip internal.
- A kind of 7. data error processing method of high-speed interface chip according to claim 6, it is characterised in that the step It is to the process of data code correction in rapid two：ECC codings and Bose-Chaudhuri-Hocquenghem Code are carried out to sent data order first, then Transmission end interface through high-speed interface chip is sent, and the reception end interface of high-speed interface chip carries out ECC after receiving data Error correction.
- 8. the data error processing method of a kind of high-speed interface chip according to claim 7, it is characterised in that to pending The data sent carry out ECC cataloged procedures：First by packet to be sent, every 256 B data is one group；Then 256 B datas are regarded as the matrix of 256x8, one bit of each element representation of matrix；Matrix is encoded, matrix generates the row check information of 6bit and the row check information of 16bit respectively after being encoded, That is the check code of 22bit.
- 9. the data error processing method of a kind of high-speed interface chip according to claim 7 or 8, it is characterised in that right The process that data to be sent carry out again after ECC codings Bose-Chaudhuri-Hocquenghem Code is：Data after ECC is encoded are grouped, and are one group of carry out Bose-Chaudhuri-Hocquenghem Code by every 256 B data；Then 256 B datas are regarded as the matrix of 256x8, one bit of each element representation of matrix；Using 8 parallel-by-bit Bose-Chaudhuri-Hocquenghem Code algorithms, i.e., calculated at the same time as one group per 8bit, by information bit be calculated verification and, By information bit and verification and collectively constitute one group of BCH code；Sent after the completion of Bose-Chaudhuri-Hocquenghem Code from the transmission end interface of high-speed interface chip.
- A kind of 10. data error processing method of high-speed interface chip according to claim 9, it is characterised in that step It is to the detailed process of correcting data error in two：1）After the receiving terminal of high-speed interface chip receives data, it is grouped first into being about to data, is one by every 256 B data Group, the check code of 22bit is equally generated with ECC codings；2）By step 1）In check code and the check code that stores carries out step-by-step xor operation when sending data；3）When the result that xor operation obtains is 0, then mistake is not present in data；4）When in the result that xor operation obtains there are 11bit value be 1, then there are a bit-errors, and corrected；5）When the result that xor operation obtains only exists 1bit mistakes, then the check code generated malfunctions, and mistake is not present in data；6）When the result that xor operation obtains multi-bit errors then occurs for other situations, can not correct, and indicate to need to carry out BCH is decoded.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110213015A (en) * | 2019-04-28 | 2019-09-06 | 杭州电子科技大学 | A kind of combination coding and decoding method for short code |
| CN110995392A (en) * | 2019-11-28 | 2020-04-10 | 上海集成电路研发中心有限公司 | Data transmission method and device |
| CN111597072A (en) * | 2020-05-07 | 2020-08-28 | 中国科学院微电子研究所 | Error Control Coding (ECC) system and memory device including the same |
| WO2022078426A1 (en) * | 2020-10-15 | 2022-04-21 | 华为技术有限公司 | Data transmission method and system, and computer-readable storage medium |
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| CN110213015A (en) * | 2019-04-28 | 2019-09-06 | 杭州电子科技大学 | A kind of combination coding and decoding method for short code |
| CN110995392A (en) * | 2019-11-28 | 2020-04-10 | 上海集成电路研发中心有限公司 | Data transmission method and device |
| CN111597072A (en) * | 2020-05-07 | 2020-08-28 | 中国科学院微电子研究所 | Error Control Coding (ECC) system and memory device including the same |
| CN111597072B (en) * | 2020-05-07 | 2024-03-12 | 中国科学院微电子研究所 | Error control coding ECC system and memory device including the same |
| WO2022078426A1 (en) * | 2020-10-15 | 2022-04-21 | 华为技术有限公司 | Data transmission method and system, and computer-readable storage medium |
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