WO2022078426A1

WO2022078426A1 - Data transmission method and system, and computer-readable storage medium

Info

Publication number: WO2022078426A1
Application number: PCT/CN2021/123743
Authority: WO
Inventors: 杜思清; 常鸣; 糟永明; 乐培玉
Original assignee: 华为技术有限公司
Priority date: 2020-10-15
Filing date: 2021-10-14
Publication date: 2022-04-21
Also published as: CN114374470A; CN114374470B

Abstract

Provided are a data transmission method and system, and a computer-readable storage medium. The method comprises: if an environmental parameter of a transmission channel meets a first algorithm enabling condition, encoding acquired transmission data by means of a first error detection and correction algorithm, so as to generate first encoded data, and sending the first encoded data to a second device; and if the environmental parameter of the transmission channel meets a second algorithm enabling condition, encoding the acquired transmission data by means of a second error detection and correction algorithm, so as to generate second encoded data, and sending the second encoded data to the second device, wherein the second error detection and correction algorithm is different from the first error detection and correction algorithm. In the embodiments of the present application, the data transmission efficiency is improved while also ensuring the data transmission reliability.

Description

Data transmission method, system and computer readable storage medium

This application claims the priority of the Chinese patent application with the application number 202011106012.4 and the application title "Data Transmission Method, System and Computer-readable Storage Medium" filed with the China Patent Office on October 15, 2020, the entire contents of which are incorporated by reference in this application.

technical field

The present application relates to the field of communication technologies, and in particular, to a data transmission method, system, and computer-readable storage medium.

Background technique

With the development of communication technology, the application of electronic equipment has higher and higher requirements for image and video processing. In the process of image and video transmission, it is necessary to perform error detection and correction processing on the transmission data through error detection and correction technology to ensure the reliability of data transmission.

However, there is no data transmission method in the related art that can improve the data transmission efficiency on the basis of ensuring the reliability of the data transmission.

SUMMARY OF THE INVENTION

In view of this, the present application provides a data transmission method, system, and computer-readable storage medium, which are used to improve data transmission efficiency on the basis of ensuring data transmission reliability.

In a first aspect, an embodiment of the present application provides a data transmission method, which is applied to a first device, and the method includes:

If the environmental parameters of the transmission channel meet the conditions for enabling the first algorithm, encode the acquired transmission data through the first error detection and correction algorithm, generate first encoded data, and send the first encoded data to the second device;

If the environmental parameters of the transmission channel meet the conditions for enabling the second algorithm, the acquired transmission data is encoded by the second error detection and correction algorithm, second encoded data is generated, and the second encoded data is sent to the second device. The second error detection and correction algorithm is different from the first error detection and correction algorithm.

In a possible implementation manner, the method further includes: acquiring environmental parameters of the transmission channel.

In a possible implementation manner, the environmental parameter of the transmission channel includes a bit error rate; the obtaining the environmental parameter of the transmission channel includes:

Send the first sequence and the second sequence to the second device in sequence, so that the second device can count the number of bits of the correct second sequence received, and the first sequence is used to implement state machine equalization training;

receiving the correct number of bits of the second sequence sent by the second device;

The bit error rate is calculated according to the correct number of bits of the second sequence sent by the second device and the total number of bits of the second sequence sent by the second device.

In a possible implementation, if the environmental parameter of the transmission channel meets the first algorithm opening condition and if the environmental parameter of the transmission channel meets the second algorithm opening condition, the method further includes:

collect raw data;

Convert the encoding format to the original data to generate the transmission data.

In a possible implementation manner, the environment parameter of the transmission channel includes a system transmission rate; the obtaining the environment parameter of the transmission channel includes:

The system transfer rate is read from the Cutoff Status Register.

In a possible implementation manner, the environment parameter of the transmission channel includes a packet loss rate; the obtaining the environment parameter of the transmission channel includes:

Send a test data packet to the second device, and record the number of the sent test data packet;

Receive the number of correct test data packets received according to statistics returned by the second device;

Calculate the packet loss rate according to the number of correct test packets and the number of sent test packets.

In a possible implementation manner, before the encoding of the acquired transmission data by the first error detection and correction algorithm and before the encoding of the acquired transmission data by the second error detection and correction algorithm, the method further includes:

collect raw data;

In a possible implementation manner, the transmission channel environment parameter includes one of a bit error rate, a system transmission rate, and the packet loss rate or any combination thereof;

The transmission channel environment parameter meeting the first algorithm enabling condition includes: the bit error rate is greater than or equal to a first threshold, the system transmission rate is greater than or equal to a second threshold, and the packet loss rate is greater than or equal to a third threshold one or any combination thereof;

The transmission channel environment parameter meeting the condition for enabling the second algorithm includes: the bit error rate is less than the first threshold, the system transmission rate is less than the second threshold, and the packet loss rate is less than one of the third threshold or any combination thereof .

In a possible implementation manner, the first error detection and correction algorithm includes at least two error detection and correction algorithms, the second error detection and correction algorithm includes at least one error detection and correction algorithm, and the first error detection and correction algorithm includes at least one error detection and correction algorithm. The number of error detection and correction algorithms is greater than the number of error detection and correction algorithms in the second error detection and correction algorithm.

In a possible implementation manner, the first error detection and correction algorithm includes a forward error correction (FEC) algorithm, a clean core cyclic redundancy check (CRC) algorithm, and a packet header error correction code ECC algorithm; or

The first error detection and correction algorithm includes an FEC algorithm and a CRC algorithm; or

The first error detection and correction algorithm includes an FEC algorithm and an ECC algorithm.

In a possible implementation manner, the second error detection and correction algorithm includes an FEC algorithm; or

The second error detection and correction algorithm includes a CRC algorithm; or

The second error detection and correction algorithm includes an ECC algorithm; or

The second error detection and correction algorithm includes a CRC algorithm and an ECC algorithm.

In a possible implementation manner, the first encoded data includes an indication field, where the indication field is used to indicate that the environmental parameter complies with the condition for enabling the first algorithm.

In a possible implementation manner, the indication field includes a reserved field or a newly added field.

In a possible implementation manner, the first device includes a camera module, and the second device includes a motherboard or an electronic device; or

The first device includes a motherboard, a host or an electronic device, and the second device includes a display screen.

In a second aspect, an embodiment of the present application provides a data transmission method, which is applied to a second device, and the method includes:

If the first encoded data sent by the first device is received, the first encoded data is checked by a first error detection and correction algorithm to generate transmission data;

If the second encoded data sent by the first device is received, the second encoded data is verified by a second error detection and correction algorithm to generate transmission data.

In a possible implementation manner, the environmental parameter of the transmission channel includes a bit error rate; the method further includes:

receiving a first sequence and a second sequence sequentially sent by the first device, where the first sequence is used to implement state machine equalization training;

Calculate the bit error rate according to the number of bits of the correct second sequence received and the total number of bits of the second sequence sent;

If the bit error rate complies with the enabling condition of the first algorithm, a first bit error rate status is sent to the first device, where the first bit error rate status is used to indicate that the bit error rate conforms to the first algorithm open condition;

If the bit error rate complies with the enabling condition of the second algorithm, send a second bit error rate status to the first device, where the second bit error rate status is used to indicate that the bit error rate conforms to the second algorithm Turn on condition.

In a possible implementation manner, the environmental parameter of the transmission channel includes a packet loss rate; the method further includes:

receiving the test data packet sent by the first device;

Calculate the packet loss rate according to the number of correct test packets received and the number of test packets sent;

If the packet loss rate complies with the enabling condition of the first algorithm, send a first packet loss rate status to the first device, where the first packet loss rate status is used to indicate that the packet loss rate complies with the first algorithm open condition;

If the packet loss rate complies with the enabling condition of the second algorithm, a second packet loss rate status is sent to the first device, where the first packet loss rate status is used to indicate that the packet loss rate complies with the second algorithm Turn on condition.

In a possible implementation manner, the first error detection and correction algorithm includes an FEC algorithm, a CRC algorithm and an ECC algorithm; or

In a possible implementation manner, the performing verification on the first encoded data by using a first error detection and correction algorithm includes:

If it is determined that the first encoded data includes an indication field, perform FEC check on the first encoded data, and the indication field is used to indicate that the environment parameter complies with the first algorithm enabling condition;

CRC check and/or ECC check is performed on the first encoded data after the FEC check.

Perform FEC check on the first encoded data;

If it is determined that the first encoded data includes an indication field, perform CRC check and/or ECC check on the FEC-checked first encoded data, and the indication field is used to indicate that the environmental parameter conforms to the first encoded data. Algorithm start condition.

In a third aspect, embodiments of the present application provide a first device, including: one or more processors; a memory; and one or more computer programs, wherein the one or more computer programs are stored in the memory wherein, the one or more computer programs include instructions, which, when executed by the device, cause the device to execute the first aspect or the data transmission method in any possible implementation manner of the first aspect.

In a fourth aspect, embodiments of the present application provide a second device, comprising: one or more processors; a memory; and one or more computer programs, wherein the one or more computer programs are stored in the memory wherein, the one or more computer programs include instructions, which, when executed by the device, cause the device to execute the data transmission method in the second aspect or any possible implementation manner of the first aspect.

In a fifth aspect, an embodiment of the present application provides a data transmission system, including: a first device and a second device, where the first device and the second device are communicatively connected through a transmission channel;

The first device is configured to encode the acquired transmission data through a first error detection and correction algorithm if the environmental parameters of the transmission channel meet the conditions for enabling the first algorithm, generate first encoded data, and convert the first encoded data to the first device. Send to the second device; if the environmental parameters of the transmission channel meet the conditions for enabling the second algorithm, encode the acquired transmission data through the second error detection and correction algorithm, generate second encoded data, and send the second encoded data to a second device, wherein the second error detection and correction algorithm is different from the first error detection and correction algorithm;

The second device is configured to, if receiving the first encoded data sent by the first device, verify the first encoded data through a first error detection and correction algorithm to generate transmission data; if receiving the first encoded data sent by the first device The second encoded data is checked by a second error detection and correction algorithm to generate transmission data.

In a sixth aspect, an embodiment of the present application provides an electronic device, including: a first device and a second device, where the first device and the second device are communicatively connected through a transmission channel;

The second device is configured to, if receiving the first encoded data sent by the first device, verify the first encoded data through a first error detection and correction algorithm, and generate transmission data; if receiving the first encoded data sent by the first device The second encoded data is checked by a second error detection and correction algorithm to generate transmission data.

In a seventh aspect, an embodiment of the present application provides a computer-readable storage medium, where the computer-readable storage medium is used for program code executed by a device, and the program code includes the first aspect or any of the first aspect. Instructions for a method in a possible implementation.

In an eighth aspect, an embodiment of the present application provides a computer-readable storage medium, where the computer-readable storage medium is used for program code executed by a device, and the program code includes a program code for executing the second aspect or the second aspect. Instructions for a method in a possible implementation.

In a ninth aspect, an embodiment of the present application provides a computer program product containing instructions, wherein when the computer program product is run on a computer or any at least one processor, the computer is made to execute the above-mentioned first step. A data transmission method in one aspect or any possible implementation manner of the first aspect.

In a tenth aspect, an embodiment of the present application provides a computer program product containing instructions, wherein when the computer program product is run on a computer or any at least one processor, the computer is made to execute the above-mentioned first step. The data transmission method in the second aspect or any possible implementation manner of the second aspect.

In the technical solutions provided by the embodiments of the present application, the first device selects a first error detection and correction algorithm to encode the transmission data to generate the first encoded data according to the environmental parameters of the transmission channel meeting the conditions for enabling the first algorithm, or the first device generates the first encoded data according to the transmission channel. If the environmental parameters meet the conditions for enabling the second algorithm, select the second error detection and correction algorithm to encode the transmission data to generate the second encoded data, and the second device receives the encoded data. The algorithm verifies the encoded data to generate transmission data. If it is determined that the second algorithm is enabled, the encoded data is verified by the second error detection and correction algorithm to generate transmission data. The transmission data in the transmission process is subjected to error detection and correction processing, thereby improving the data transmission efficiency on the basis of ensuring the reliability of data transmission.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present application more clearly, the following briefly introduces the accompanying drawings used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort.

1 is a schematic diagram of an error detection and correction technique in some embodiments;

2 is a schematic structural diagram of a D-PHY-based data transmission system in the related art;

3 is a flowchart of a data transmission method based on D-PHY in the data transmission system in FIG. 2;

4 is a schematic diagram of the format of a second data block transmitted based on D-PHY in the related art;

5 is a schematic structural diagram of a data transmission system based on C-PHY in the related art;

6 is a flowchart of a data transmission method based on C-PHY in the data transmission system in FIG. 5;

7 is a schematic diagram of the format of a data packet transmitted based on C-PHY in the related art;

8 is a schematic diagram of a layered structure of a data transmission system based on CSI-3 in the related art;

Fig. 9 is based on the format schematic diagram of the MIPI UniPro L2 layer data frame of the data transmission system in Fig. 8;

10 is a schematic structural diagram of an HDMI-based data transmission system in the related art;

11 is a flowchart of a data transmission method based on HDMI in the data transmission system in FIG. 10;

12 is a schematic diagram of the format of a second data block transmitted based on HDMI in the related art;

13 is a schematic diagram of the format of a third data block transmitted based on HDMI in the related art;

14 is a schematic structural diagram of a DP-based data transmission system in the related art;

15 is a flowchart of a DP-based data transmission method in the related art;

16 is a schematic diagram of the format of a DP-based link layer (Link Layer) data frame;

17 is a schematic diagram of the format of a data frame that implements single-channel FEC at the PHY layer based on DP;

FIG. 18a is a schematic communication diagram of a data transmission system provided by some embodiments of the present application;

18b is a schematic diagram of a board-level connection between a first device and a second device provided by some embodiments of the present application;

18c is a schematic diagram of a board-level connection between a first device and a second device provided by other embodiments of the present application;

18d is a flowchart of a data transmission method provided by an embodiment of the present application;

19 is a schematic structural diagram of a data transmission system provided by some embodiments of the present application;

20 is a flowchart of a data transmission method provided by some embodiments of the present application;

21 is a schematic diagram of a data format of a training code stream in some embodiments of the present application;

FIG. 22 is a schematic diagram of the format of a data block transmitted based on D-PHY in some embodiments of the present application;

23 is a flowchart of a data transmission method provided by other embodiments of the present application;

24 is a schematic structural diagram of a data transmission system provided by other embodiments;

25 is a flowchart of a data transmission method provided by other embodiments;

26 is a schematic diagram of the format of a data block transmitted based on HDMI in an embodiment of the present application;

FIG. 27 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.

Detailed ways

In order to better understand the technical solutions of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

It should be clear that the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this application.

The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. As used in the embodiments of this application and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise.

It should be understood that the term "and/or" used in this article is only an association relationship to describe related objects, indicating that there can be three kinds of relationships, for example, A and/or B, which can mean that A exists alone, and A and B exist at the same time. B, there are three cases of B alone. In addition, the character "/" in this text generally indicates that the related objects are an "or" relationship.

With the advancement of electronic equipment, the application of electronic equipment has higher and higher requirements for image and data processing. Inside the electronic device, this requirement is mainly reflected in the requirement for the transfer rate of the interface between the System on Chip (SOC) and the peripheral device. Camera Serial Interface 2 (CSI-2), Camera Serial Interface 3 (CSI-3), Camera Serial Interface 3 (CSI-3), Mobile Industry Processor Interface (MIPI), The image and video transmission technologies represented by High-Definition Multimedia Interface (HDMI) and Display Port (DP) have shown many advantages in terms of processing flexibility and functionality.

However, due to the complex channel environment, transmission errors inevitably occur during the transmission of images and videos, especially the high bit error rate caused by factors such as signal transmission path loss, channel interference and terminal movement. For image and video transmission, since it is more sensitive to channel-introduced errors or burst data packet loss, a certain number of bit errors or packet loss may reduce the image quality by many orders of magnitude, directly affecting the final decoding recovery and vision. Therefore, it is necessary to adopt a strong channel coding method to ensure a certain bit error rate. Among them, bit error refers to random errors or burst errors in the received data caused by channels, equipment, etc.; packet loss refers to that the data of one or more data packets cannot be transmitted to the destination. Since different error detection and correction algorithms are suitable for different channel environments, different error detection and correction algorithms need to be used according to the bit error rate, packet loss rate, etc. The bit error rate and packet loss rate can improve the reconstruction quality of the image and video at the receiving end, and make the transmission process of the image and video have the characteristics of low complexity and simple implementation.

At present, the error detection and correction technology used in the image and video transmission process can be divided into the sending end error detection and correction technology and the receiving end error detection and correction technology according to the link in the communication. As shown in Figure 1, in the transmission process of images and videos, error detection and correction techniques may include source coding, channel coding, transmission line transmission, channel decoding and information source decoding, wherein, the source coding belongs to the source processing part, Channel coding, transmission line transmission and channel decoding belong to the channel processing part, and source decoding belongs to the sink processing part. The error detection and correction technology at the transmitting end is a method of adding redundant information during channel coding to enhance the error detection and correction capability of the coded bit stream. The error detection and correction technology at the receiving end is completed based on channel decoding. The decoder approximately restores the lost or erroneous data according to the decoding rules, and does not need to do technical processing at the sending end in advance, such as error compensation in fax images and video error compensation. Error hiding techniques, etc. In the error detection and correction technology at the transmitting end, the error detection and correction technology in the channel decoding stage is processed in advance at the transmitting end, adding redundant information that can be used for error detection or error correction. It should be noted that: the data transmission method provided by the embodiment of the present application uses the error detection and correction technology at the transmitting end to perform error detection and correction processing on the transmission data.

CSI-2 is an interface developed by the MIPI organization to transmit image data between the camera chip and the main control chip of an electronic device. CSI-2 is compatible with two port physical layers (Port Physical Layer, PHY for short), namely C-PHY and D-PHY, so CSI-2 corresponds to two different error detection and correction algorithms.

FIG. 2 is a schematic structural diagram of a D-PHY-based data transmission system in the related art. As shown in FIG. 2, the data transmission system may include a first device and a second device, the first device includes an image processing unit and a sending device, and the first device includes a transmission device. The second device includes a main processor unit and a receiving device, the transmitting device and the receiving device are communicatively connected through a transmission channel, the image processing unit is communicatively connected with the sending device, and the main processor unit is communicatively connected with the receiving device. Wherein, the sending device includes a first format conversion module, a protocol sending unit and a PHY layer sending module. The protocol sending unit includes an error correction code (Error Correction Code, ECC for short) coding module and a clean core cyclic redundancy check (Cyclic Redundancy Check, CRC for short) coding module. The receiving device includes a second format conversion module, a protocol receiving unit and a PHY layer receiving module, and the protocol receiving unit includes a packet header ECC decoding module and a clean core CRC decoding module. Wherein, the PHY layer sending module and the PHY layer receiving module are communicated and connected through a transmission channel.

The related art provides a data transmission method based on D-PHY, the first device includes a camera module, the second device includes a mainboard of a mobile phone, the protocol sending unit includes a CSI-2 sending unit, and the protocol receiving unit includes a CSI-2 receiving unit , the PHY layer sending module includes a D-PHY sending module, and the PHY layer receiving module includes a D-PHY receiving module.

FIG. 3 is a flowchart of the data transmission method based on D-PHY in the data transmission system in FIG. 2. As shown in FIG. 3, the method includes:

Step 102: The main processor unit configures parameters for the image processing unit.

Specifically, in all actual use scenarios, the main board can configure the working parameters of the camera module, so that the camera module can work according to the requirements of the working parameters. The working parameters may include resolution, frame rate, interface rate, and the like.

Step 104: The protocol sending unit sends the training code stream to the protocol receiving unit.

Specifically, the protocol sending unit sends the training code stream to the PHY layer sending module, the PHY layer sending module sends the training code stream to the PHY layer receiving module through the transmission channel, and then the PHY layer receiving module sends the training code stream to the protocol receiving unit, and the protocol The receiving unit receives the training code stream and adjusts the parameters adaptively to realize the CSI-2 state machine equalization training process. After the state machine equalization training is implemented, the first device starts to transmit the image data stream.

Step 106: The image processing unit collects the image data stream, and sends the collected image data stream to the first format conversion module.

Step 108: The first format conversion module converts the encoding format of the image data stream, generates a first data block, and adds a data packet header to the first data block.

FIG. 4 is a schematic diagram of the format of the second data block transmitted based on D-PHY in the related art. As shown in FIG. 4 , the first format conversion module (as shown in FIG. 2 ) performs binary encoding format conversion on the image data stream to Form a payload. Among them, "Payload" is used to represent the first data block. The data packet header may include a data type identifier (Data Identifier, referred to as Data ID), the number of bytes (16-bit WC) and a virtual channel identifier (Virtual Channel Extension, referred to as VCX). Among them, the number of bytes is used to mark the number of "Payload", and WC is the abbreviation of Word Count. The first format conversion module sends the first data block to which the data packet header is added to the protocol sending unit.

Step 110: The protocol sending unit performs ECC encoding on the data packet header through the packet header ECC encoding module to generate a first ECC field.

As shown in Figure 4, the packet header ECC encoding module (as shown in Figure 2) performs ECC encoding on Data ID, WC and VCX through a 6-bit extended Hamming code to generate a first ECC field, where, for example, the ECC field is: 6 -bit field. It should be noted that: the ECC field shown in FIG. 4 is the first ECC field.

Step 112: The protocol sending unit performs CRC encoding on the first data block through the clean core CRC encoding module to generate a CRC field.

As shown in Figure 4, the net core CRC encoding module (as shown in Figure 2) performs CRC encoding on "Payload" through a polynomial to generate a CRC field. The polynomial is, for example, X ¹⁶ +X ¹² +X ⁵ +X ⁰ , the CRC field is, for example, a 16-bit field, and the CRC field is “16-bit CRC” in FIG. 4 .

Step 114: The protocol sending unit generates a second data block according to the first data block, the data packet header, the first ECC field and the CRC field.

As shown in Figure 4, the protocol sending unit (as shown in Figure 2) places the first ECC field and the CRC field at the head and tail of the "Payload" respectively, and places the Data ID, WC and VCX in the packet header at the The designated position of the data packet, and the Start of Transmit (SoT) mark is set at the beginning of the data packet and the End of Transmit (EoT) mark is set at the end of the data packet to form Figure 4 The second data block in the long packet format shown.

Step 116: The protocol sending unit sends the second data block to the PHY layer sending module, the PHY layer sending module sends the second data block to the PHY layer receiving module through the transmission channel, and the PHY layer receiving module sends the second data block to the protocol receiving module. unit.

Step 118: The protocol receiving unit performs CRC check on the CRC field in the second data block through the clean core CRC decoding module, and generates a CRC check result.

The net-core CRC decoding module (as shown in Figure 2) divides the CRC field in the second data block and the polynomial by modulo 2 to obtain the remainder, which is the CRC check result. If the CRC check result is 0, it indicates that the received "Payload" is correct data; if the CRC check result is not 0, it indicates that the received "Payload" is wrong data. Wherein, the polynomial may include X ¹⁶ +X ¹² +X ⁵ +X ⁰ .

Step 120: The protocol receiving unit performs ECC verification on the data packet header in the second data block through the packet header ECC decoding module, and generates an ECC verification result.

The packet header ECC decoding module (as shown in Figure 2) encodes the Data ID, WC and VCX in the packet header to generate the second ECC field, and performs XOR calculation on the first ECC field and the second ECC field to obtain the ECC check result . If the ECC check result is 0, it indicates that the data packet header is correct; if the ECC check result is not 0 and the ECC check result indicates a 1-bit error and an error bit, it indicates that the error bit of the data packet header needs to be corrected; if If the ECC check result is not 0 and the ECC check result indicates that there are more than 2-bit errors, it indicates that an uncorrectable error has occurred in the data packet header.

Among them, the packet header ECC decoding module can use the same coding rules as the packet header ECC encoding module to perform ECC encoding on the Data ID, WC and VCX in the data packet header, that is, the packet header ECC decoding module can pass 6-bit extended Hamming code to Data ID, WC and VCX. WC and VCX perform ECC encoding to generate the second ECC field.

Step 122: If the protocol receiving unit recognizes that the CRC check result is 0 and the ECC check result is 0, it performs unpacking processing on the second data block to generate the first data block.

Specifically, the protocol receiving unit removes the SoT identifier, the EoT identifier, the first ECC field, the CRC field, the Data ID, the WC, and the VCX in the second data block, so that the second data block can be unpacked to obtain the first data block. .

The protocol receiving unit sends the unpacked first data block to the second format conversion module.

Step 124: The second format conversion module converts the encoding format of the first data block, generates an image data stream, and uploads the image data stream to the main processor unit.

The second format conversion module (as shown in FIG. 2 ) converts the first data block to pixel image coding format to generate an image data stream, and uploads the image data stream to the main processor unit.

As an optional solution, if the protocol receiving unit recognizes that the ECC check result is not 0 and the ECC check result indicates that there are 1-bit errors and erroneous bits, the protocol receiving unit corrects the erroneous bits of the data packet header, and corrects the second data The block is unpacked to generate a first data block, and then the first data block is converted into a pixel image coding format to generate an image data stream, and the image data stream is uploaded to the main processor unit.

As another optional solution, if the protocol receiving unit recognizes that the CRC check result is not 0 and/or that the ECC check result is not 0 and the ECC check result indicates that there are more than 2-bit errors, then The second data block is discarded, skipped directly, or retransmitted. In this case, the developer can determine the processing method for the second data block.

FIG. 5 is a schematic structural diagram of a data transmission system based on C-PHY in the related art. As shown in FIG. 5 , the data transmission system may include a first device and a second device. The first device includes an image processing unit and a sending device. The second device includes a main processor unit and a receiving device, the transmitting device and the receiving device are communicatively connected through a transmission channel, the image processing unit is communicatively connected with the sending device, and the main processor unit is communicatively connected with the receiving device. Wherein, the sending device includes a first format conversion module, a protocol sending unit and a PHY layer sending module. The protocol sending unit includes a packet header CRC encoding module and a clean core CRC encoding module. The receiving device includes a second format conversion module, a protocol receiving unit and a PHY layer receiving module, and the protocol receiving unit includes a packet header CRC decoding module and a clean core CRC decoding module. Wherein, the PHY layer sending module and the PHY layer receiving module are communicated and connected through a transmission channel.

The related art also provides a data transmission method based on C-PHY. The first device includes a camera module, the second device includes a mainboard of a mobile phone, the protocol sending unit includes a CSI-2 sending unit, and the protocol receiving unit includes a CSI-2 receiving unit. unit, the PHY layer sending module includes a C-PHY sending module, and the PHY layer receiving module includes a C-PHY receiving module. FIG. 6 is a flowchart of the data transmission method based on C-PHY in the data transmission system in FIG. 5 . As shown in FIG. 6 , the method includes:

Step 202: The main processor unit configures parameters for the image processing unit.

Step 204: The protocol sending unit sends the training code stream to the protocol receiving unit.

Step 206: The image processing unit collects the image data stream, and sends the collected image data stream to the first format conversion module.

For the description of steps 202 to 206, reference may be made to steps 102 to 106, and details are not repeated here.

Step 208: The first format conversion module converts the encoding format of the image data stream, generates a first data block, and adds a data packet header to the first data block.

FIG. 7 is a schematic diagram of the format of a data packet transmitted based on C-PHY in the related art. As shown in FIG. 5 and FIG. 7 , the first format conversion module (as shown in FIG. 5 ) performs binary encoding format conversion on the image data stream, to form the first data block "Payload". The packet header can include Data ID, 16-bit WC and VCX. The first format conversion module sends the first data block to which the data packet header is added to the protocol sending unit.

Step 210: The protocol sending unit performs CRC encoding on the data packet header through the packet header CRC encoding module to generate a PH-CRC field.

As shown in Figure 7, the packet header CRC encoding module (as shown in Figure 5) performs CEC encoding on the Data ID, WC and VCX in the data packet through a polynomial to generate a PH-CRC field. Wherein, the polynomial may include X ¹⁶ +X ¹² +X ⁵ +X ⁰ .

Step 212: The protocol sending unit performs CRC encoding on the first data block through the clean core CRC encoding module to generate a PF-CRC field.

As shown in Figure 7, the clean core CRC encoding module (as shown in Figure 5) performs CRC encoding on "Payload" through a polynomial to generate a PF-CRC field. The polynomial is, for example: X ¹⁶ +X ¹² +X ⁵ +X ⁰ .

Since C-PHY adopts a unique three-line encoding method, that is, three levels are encoded at the same time, if one level is wrongly encoded, the subsequent level encoding will also be wrong, resulting in multi-bit errors. Therefore, in order to enhance data reliability , detects multi-bit errors, and the CRC encoding module can perform CRC encoding and verification on the transmitted data.

Step 214: The protocol sending unit generates a second data block according to the first data block, the data packet header, the PH-CRC field, the PF-CRC field and the reserved field (Reserved Field, RES for short).

As shown in Figure 7, the protocol sending unit (as shown in Figure 5) places the PH-CRC field and the PF-CRC field at the head and tail of the "Payload" respectively, and sets the Data ID, WC, VCX, The RES and Filler fields are respectively placed at the designated positions of the second data block, and the SoT mark is set at the start position of the second data block and the EoT mark is set at the end position of the second data block, so as to form as shown in FIG. 7 . The second data block in long packet format.

Step 216: The protocol sending unit sends the second data block to the PHY layer sending module, the PHY layer sending module sends the second data block to the PHY layer receiving module through the transmission channel, and the PHY layer receiving module sends the second data block to the protocol receiving module. unit.

Step 218: The protocol receiving unit performs CRC check on the PH-CRC field in the second data block through the header CRC decoding module, and generates a first CRC check result.

The packet header CRC decoding module (as shown in FIG. 7 ) performs modulo-2 division calculation on the PH-CRC field in the second data block and the polynomial to obtain the remainder, which is the first CRC check result. The first CRC check result may be 0 or not. The polynomial is, for example: X ¹⁶ +X ¹² +X ⁵ +X ⁰ .

Step 220: The protocol receiving unit performs CRC check on the PF-CRC field in the second data block through the clean core CRC decoding module, and generates a second CRC check result.

The net-core CRC decoding module divides the PF-CRC field in the second data block and the polynomial by modulo 2 to obtain the remainder, and the remainder is the second CRC check result. The second CRC check result may be 0 or not. The polynomial is, for example: X ¹⁶ +X ¹² +X ⁵ +X ⁰ .

Step 222: If the protocol receiving unit recognizes that the first CRC check result and the second CRC check result are both 0, it unpacks the second data block to generate the first data block.

If the protocol receiving unit recognizes that the first CRC check result and the second CRC check result are both 0, it indicates that the information of the second data block is completely correct, and can continue to unpack the second data block.

Specifically, the protocol receiving unit removes the SoT identifier, EoT identifier, PH-CRC field, PF-CRC field, Data ID, WC, VCX, RES, and Filler in the second data block, so as to unpack the second data block The processing obtains the first data block.

Step 224: The second format conversion module converts the encoding format of the first data block, generates an image data stream, and uploads the image data stream to the main processor unit.

The protocol receiving unit performs pixel image coding format conversion on the first data block to generate an image data stream, and uploads the image data stream to the main processor unit.

As an optional solution, if the first CRC check result is not 0 and/or the second CRC check result is not 0, indicating that an uncorrectable error occurs in the field in the second data block, the protocol receiving unit will The second data block is discarded, skipped directly, or retransmitted. In this case, the developer can determine the processing method for the second data block.

FIG. 8 is a schematic diagram of a layered structure of a data transmission system based on CSI-3 in the related art. As shown in FIG. 8 , the data transmission system includes a first device and a second device. Channel communication connection. The first device includes an image processing unit, a sending device, a device management entity (Device Management Entity) and a PHY layer sending module, wherein the image processing unit includes a camera application layer (Camera Application Layer), and the sending device includes a transport layer (Transport) L4 layer, network layer (Network) L3 layer, Data Link layer (Data Link) L2 layer, PHY Adaptor layer (PHY Adaptor) L1.5 layer; the second device includes a main processor unit, a receiving device, a device management entity ( Device Management Entity) and a PHY layer receiving module, wherein the main processor unit includes a host application layer (Host Application Layer), and the receiving device includes a PHY Adaptor layer (PHY Adaptor) L1.5 layer, a data link layer (Data Link) The L2 layer, the network layer (Network) L3 layer, and the transport layer (Transport) layer L4. Among them, the PHY layer sending module and the PHY layer receiving module are communicated and connected through a transmission channel.

The related art also provides a data transmission method based on CSI-3. Figure 9 is a schematic diagram of the format of the MIPI UniPro L2 layer data frame based on the data transmission system in Figure 8, as shown in Figure 8 and Figure 9, for all camera modules in actual use scenarios, on the first device side, when the L3 layer When the image data block of the L3 layer is transmitted to the L2 layer, the L2 layer adds the L2 layer header character on the basis of the image data block of the L3 layer, and uses the CCITT CRC-16 algorithm to perform the verification calculation on the image data block of the L3 layer to generate 16-bit CRC check field. Add the 16-bit CRC check field to the end of the L2 layer data frame, as shown in Figure 9, the L2 layer data frame also includes the Data Link Layer Control Symbol Identifier (ESC_DL) field, L2 Layer data packet end frame identifier (End of Frame for even L2 SDU, referred to as EOF_EVEN) field, frame sequence number (Frame Sequence Number, referred to as Frame Seq Number) and traffic type (Traffic Class, referred to as TC) field. Then, at the L2 layer of the second device, the remainder is obtained by checking the image data block according to the modulo 2 division. If the remainder is 0, it means that the current data packet information is completely correct, and the L2 layer image data block is restored to the L3 layer image data. If the remainder is not 0, it means that an uncorrectable error has occurred in the L2 layer image data block, and the erroneous data packet will be discarded, skipped directly or repeated. In this case, the developer can determine the processing method of the data packet. For the flow of the CSI-3-based data transmission method in the related art, reference may be made to the C-PHY-based data transmission method shown in FIG. 6 , and the description will not be repeated here.

In the scheme of the data transmission method based on CSI-2 and CSI-3 in the above-mentioned related art, because the CRC algorithm and the ECC algorithm or the CRC algorithm is used to perform error detection and correction processing on the data, the data redundancy is small, so that the data redundancy can be reduced. Improve the efficiency of data transmission. However, due to the inability to achieve error correction of multi-bit error data, the reliable transmission of data cannot be effectively guaranteed for burst errors, and the transmission channel is interfered (for example, by additive noise and random noise) and the bit error rate is high. In this case, data packets will be lost, which will lead to image freezes and distortions, which greatly affects the user experience.

HDMI is an interface developed by HDMI Forum for high-definition multimedia transmission, which is mainly used for the transmission of video, images, etc. between devices. HDMI can be applied to multimedia transmission between a first device and a second device inside an electronic device, for example, the first device is, for example, a mainboard of a mobile phone, and the second device is, for example, a display screen of a mobile phone; or, HDMI can be applied to different Multimedia transmission between electronic devices, such as multimedia transmission between the host and the display screen.

FIG. 10 is a schematic structural diagram of an HDMI-based data transmission system in the related art. As shown in FIG. 10 , the data transmission system may include a first device and a second device. The first device includes a video data processing unit and a sending device, and the second device includes a video data processing unit and a sending device. The equipment includes a sink unit and a receiving device, the sending device and the receiving device are communicatively connected through a transmission channel, the video data processing unit is communicatively connected with the sending device, and the load unit is communicatively connected with the receiving device. Wherein, the sending device includes a first format conversion module, a protocol sending unit and a PHY layer sending module. The protocol sending unit includes a Transition-minimized Differential Signaling (TMDS) encoding module for Consumer Electronics Control (CEC) and a Forward Error Correction (FEC) encoding module. The receiving device includes a second format conversion module, a protocol receiving unit and a PHY layer receiving module, the protocol receiving unit includes a TMDS CEC decoding module and an FEC decoding module, wherein the PHY layer sending module and the PHY layer receiving module are communicated and connected through a transmission channel.

The related art also provides an HDMI-based data transmission method, wherein the load unit includes a display screen, the protocol sending unit includes an HDMI sending unit, and the protocol receiving unit includes an HDMI receiving unit. FIG. 11 is a flowchart of a data transmission method based on HDMI in the data transmission system in FIG. 10 . As shown in FIG. 11 , the method includes:

Step 302: The video data processing unit configures the working parameters of the load unit.

Specifically, in all actual use scenarios, the video processing unit can configure the working parameters of the video/image data controller of the display screen, so that the display screen can work according to the requirements of the working parameters. The working parameters may include resolution, frame rate, interface rate, and the like.

Step 304: The video data processing unit collects the image or video data stream, and sends the collected image or video data stream to the first format conversion module.

Step 306: The first format conversion module converts the encoding format of the image or video data stream, generates a first data block, and adds a data packet header to the first data block.

FIG. 12 is a schematic diagram of the format of the second data block transmitted based on HDMI in the related art. As shown in FIG. 12 , the data packet header includes a preamble (Premble), data synchronization information (Sync), control/data information (C/D) and Reserved Field (Rsvd). The first format conversion module (as shown in FIG. 10 ) adds the preamble (Premble), data synchronization information (Sync), control/data information (C/D) and reserved field (Rsvd) to the first data block (Payload) 's head. Among them, the preamble (Premble) is used to indicate that "Payload" is various types of packet information (Data Island) or video pixel data (Video Data), wherein the content of the packet information includes audio data packets or image information packets. The first format conversion module sends the first data block to which the data packet header is added to the protocol sending unit.

As shown in FIG. 12 , for example, the first data block (Payload) may include a command (Commad) or data (Data).

Step 308: The protocol sending unit performs ECC encoding on the first data block through the TMDS CEC encoding module to generate a first ECC field, and performs CRC encoding on the first data block to generate a CRC field.

Specifically, the TMDS CEC encoding module uses 6-bit extended Hamming code to perform ECC encoding on "Payload" to generate the first ECC field and the parity (Parity) field; the TMDS CEC encoding module uses 16-bit CRC to perform ECC encoding on "Payload" CRC encoding generates a CRC (16-bit CRC) field and a parity (Parity) field.

Step 310: The protocol sending unit adds the first ECC field and the CRC field to the end of the first data block to generate a second data block.

The specific format of the generated second data block can be referred to as shown in FIG. 12 . As shown in FIG. 12 , a parity (Parity) field may also be set after the first ECC field and the CRC field in the second data block.

Step 312: The protocol sending unit divides the second data block into multiple FEC data blocks through the FEC encoding module.

FIG. 13 is a schematic diagram of the format of a third data block transmitted based on HDMI in the related art. As shown in FIG. 13 , the FEC data block includes a Symbol data block (Super Block Payload). Among them, "Super Block Payload" can include command (Commad) or data (Data).

Step 314: The protocol sending unit performs FEC encoding on each FEC data block through the FEC encoding module to generate an FEC check code.

Specifically, the FEC encoding module performs FEC encoding on each FEC data block through the RS code encoding algorithm to generate an FEC check code (RS Block/Parity).

Step 316: The protocol sending unit adds the FEC check code to the end of the FEC data block through the FEC encoding module to generate a third data block.

The specific format of the third data block formed can be referred to as shown in FIG. 13 , and the third data block also includes a start bit (Start Super Block) field and a number of bytes (RS Block Symbol/Byte) field.

Step 318: The protocol sending unit sends the third data block to the PHY layer sending module, the PHY layer sending module sends the third data block to the PHY layer receiving module through the transmission channel, and the PHY layer receiving module sends the third data block to the protocol receiving module. unit.

Step 320: The protocol receiving unit performs FEC verification on the third data block through the FEC decoding module, and generates an FEC verification result.

Specifically, the FEC decoding module performs FEC check on the third data block by using the RS code decoding algorithm, and generates an FEC check result. FEC verification results include verification success, correctable error results or uncorrectable error results. Among them, the correctable error result is the error within the verification capability of the FEC algorithm, and this type of error can be corrected, so that the FEC algorithm can realize the error detection and correction of multi-bit error data; the uncorrectable error result is FEC Errors beyond the capabilities of the algorithm's verification capabilities, this type of erroneous data cannot be corrected.

Step 322, if the protocol receiving unit recognizes that the FEC check result includes a correctable error result through the FEC decoding module, the error data of the third data block is corrected and processed, and the protocol receiving unit unpacks the third data block to generate. second data block.

The protocol receiving unit removes the start bit (Start Super Block) field, the number of bytes (RS Block Symbol/Byte) field and the FEC check code in the third data block to obtain the second data block.

If the protocol receiving unit identifies through the FEC decoding module that the FEC verification result includes verification success, indicating that there is no erroneous data in the third data block, it can directly unpack the third data block to generate the second data block.

Then, the protocol receiving unit sends the second data block to the TMDS CEC decoding module.

If the protocol receiving unit recognizes that the FEC check result includes an uncorrectable error result through the FEC decoding module, the third data block will be discarded, skipped directly or retransmitted. How data blocks are handled.

Step 324, the protocol receiving unit performs CRC check on the CRC field in the second data block by the TMDS CEC decoding module, and generates a CRC check result.

The TMDS CEC decoding module performs modulo-2 division calculation on the CRC field in the second data block and the polynomial to obtain the remainder, which is the CRC check result. The CRC check result can be 0 or not. Wherein, the polynomial may include X ¹⁶ +X ¹² +X ⁵ +X ⁰ .

Step 326: The protocol receiving unit performs ECC verification on the first ECC field in the second data block through the TMDS CEC decoding module, and generates an ECC verification result.

The TMDS CEC decoding module performs ECC encoding on "Payload" in the second data block to generate a second ECC field, and performs XOR calculation on the first ECC field and the second ECC field to obtain an ECC check result. If the ECC check result is 0, it indicates that the "Payload" is correct; if the ECC check result is not 0 and the ECC check result indicates a 1-bit error and an error bit, it indicates that the error bit of "Payload" needs to be corrected ; If the ECC check result is not 0 and the ECC check result indicates that there are more than 2-bit errors, it means that an uncorrectable error has occurred in the "Payload". Among them, the TMDS CEC decoding module can use the same encoding rules as the TMDS CEC encoding module to perform ECC encoding on "Payload", that is, the TMDS CEC decoding module can perform ECC encoding on "Payload" through 6-bit extended Hamming code to generate a second ECC field.

Step 328: The protocol receiving unit judges whether the CRC check result and the ECC check result are both 0, and if so, go to Step 330; if it is judged to retransmit, go to Step 312.

Step 330: The protocol receiving unit depacketizes the second data block to generate the first data block, and sends the first data block to the second format conversion unit.

Specifically, the protocol receiving unit removes the preamble (Premble), data synchronization information (Sync), control/data information (C/D), reserved field (Rsvd), first ECC field, CRC field and A parity (Parity) field is used to obtain the first data block by unpacking the second data block.

Step 332: The second format conversion module converts the encoding format of the first data block, generates an image or video data stream, and uploads the image or video data stream to the load unit.

The second format conversion module converts the first data block to pixel image coding format to generate an image or video data stream, and uploads the image or video data stream to the load unit.

As an optional solution, if the protocol receiving unit recognizes that the ECC check result is not 0 and the ECC check result indicates that there are 1-bit errors and erroneous bits, it corrects the erroneous bits of the second data block, and corrects the error bits of the second data block. The two data blocks are unpacked to generate a first data block, and then, the protocol receiving unit converts the first data block to pixel image coding format to generate an image or video data stream, and uploads the image or video data stream to the load unit.

As another optional solution, if the protocol receiving unit recognizes that the CRC check result is not 0 and/or that the ECC check result is not 0 and the ECC check result indicates that there are more than 2-bit errors, then The second data block is discarded, skipped directly, or retransmitted. In this case, the developer can determine the processing method for the data packet. If it is determined that the second data block is to be retransmitted, step 312 can be continued. At this time, the protocol receiving unit can return an error notification to the protocol sending unit through the auxiliary channel, informing the protocol sending unit that an error occurs in the second data block and needs to be retransmitted. pass.

DP is a digital video interface standard developed by a consortium of PC and chip manufacturers and standardized by the Video Electronics Standards Association (VESA). Figure 14 is a schematic structural diagram of a DP-based data transmission system in the related art. As shown in Figure 14, the difference between the data transmission system in Figure 14 and Figure 10 is: in Figure 14, the TMDS CEC encoding module and the FEC encoding module are located in In the PHY layer sending module, the PHY layer sending module further includes a channel encoding module, the TMDS CEC decoding module and the FEC decoding module are both located in the PHY layer receiving module, and the PHY layer receiving module also includes a channel decoding module.

FIG. 15 is a flowchart of a DP-based data transmission method in the related art. As shown in Figure 15, the difference in the process between the data transmission method in Figure 15 and the data transmission method in Figure 11 is:

After step 310 in FIG. 15, it further includes: step S1, the protocol sending unit performs channel coding on the second data block through the channel coding module to generate the coded second data block, and then in step 312, the coded second data block is divided into for multiple FEC data blocks.

For example, channel coding may include 128b/132b coding or 8b/10b coding.

After step 330 in FIG. 15, the method further includes: step S2, the protocol sending unit performs channel decoding on the first data block through the channel decoding module to generate the decoded first data block.

For example, channel decoding may include 128b/132b decoding or 8b/10b decoding.

Figure 16 is a schematic diagram of the format of a DP-based link layer (Link Layer) data frame, as shown in Figure 16, Figure 16 shows a plurality of data frames, and the plurality of data frames include a data frame (Link Layer Frame) N-1 , data frame (Link Layer Frame) N and data frame (Link Layer Frame) N+1. Each data frame includes a control data packet (Control Packet) and a transmission data packet (Transport Packet). The transport packet in FIG. 16 corresponds to the second data block in FIG. 12 . The transmission data packet has the characteristics of a multi-lane data stream, and both the ECC field and the CRC field insert check bits at the end of the data packet to check and protect the data. The last byte of the data stream is generally mapped to the CRC byte for use. For the CRC check bit with only one byte (the lowest bit), the highest bit must be filled with 0 to generate the CRC value, and other CRCs do not need to be filled. . Each CRC used can have a different number of bytes. The Link Layer data frame of DP will be compressed during the data transmission process, so the check fields such as CRC and ECC are all mapped and checked in the Byte data stream.

Figure 17 is a schematic diagram of the format of a data frame for implementing single-channel FEC at the PHY layer based on DP. As shown in Figure 17, it shows a data frame obtained after channel coding and FEC coding on the second data block. The data frame It can include FEC data block link layer code (LL Codes for FEC Block), FEC data block parity code (FEC Parity Codes for Block), polarity bit code (CD_ADJ Code, CAJ Code for short) and FEC marker (FEC_PM) ). Among them, CAJ is the reserved coding polarity bit, and PM is the marker of the FEC data frame format. The channel decoding module performs the reverse decoding process of the channel encoding module, and performs FEC check and channel decoding on the obtained data frame to generate a second data block. DP implements FEC coding, decoding and error correction at the PHY layer to ensure reliable data transmission.

The scheme of the data transmission method based on HDMI and DP in the above-mentioned related art, because the FEC algorithm is used to perform error detection and correction processing on the image or video data, the error detection and correction of multi-bit error data can be performed on the image or video data, thereby improving the performance of the image or video data. reliability of data transmission. However, in the data transmission process, only the combined algorithm of the FEC algorithm, the CRC algorithm and the ECC algorithm can be used for error detection and correction processing, which leads to large data redundancy, thereby reducing the efficiency of data transmission. In addition, the data transmission method based on HDMI and DP is only suitable for specific display application scenarios, and cannot be extended to the data reliability transmission of other high-speed data transmission systems.

To sum up, there is no data transmission method in the related art that can improve the data transmission efficiency on the basis of ensuring the reliability of the data transmission. In order to solve the technical problem in the above-mentioned related art that it is impossible to improve the data transmission efficiency on the basis of ensuring the reliability of data transmission, the embodiment of the present application provides a data transmission method. The selected error detection and correction algorithm performs error detection and correction processing on the transmission data during the data transmission process, thereby improving the data transmission efficiency on the basis of ensuring the reliability of data transmission. The technical solutions of the embodiments of the present application can be flexibly extended to data reliability transmission of other high-speed data transmission systems.

Fig. 18a is a schematic communication diagram of a data transmission system provided by some embodiments of the present application. As shown in Fig. 18a, the data transmission system includes a first device and a second device, the first device includes a sending device and a first device control interface, and the second The device includes a receiving device and a second device control interface. Among them, a plurality of transmission channels and clock channels are set between the sending device and the receiving device, the transmission channels and the clock channels are both unidirectional channels, and the transmission channel can transmit image data from the first device to the second device; the first device controls An auxiliary channel (eg, I ² C bus) is provided between the interface and the second device control interface, the auxiliary channel is a bidirectional transmission channel, and the auxiliary channel includes a data line SDA and a clock signal line SCL. Wherein, data can be transmitted between the sending device and the receiving device through a high-speed interface, and data can be transmitted between the first device control interface and the second device control interface through a low-speed interface.

In this embodiment of the present application, as an optional solution, the first device and the second device may be different devices, that is, the first device and the second device are two devices that are separate devices. For example, the first device is a camera module, and the second device is a host; for another example, the first device is a host, and the second device is a display screen. Examples of the host include, but are not limited to, devices equipped with iOS, Android, Microsoft or other operating systems, optionally, the host is a mobile phone, a tablet computer, a wearable device, a smart TV, or a personal computer.

In the embodiment of the present application, as another optional solution, the data transmission system is provided in an electronic device, that is, the electronic device includes a first device and a second device. For example, the first device is a camera module, and the second device is a motherboard; in another example, the first device is a motherboard, and the second device is a display screen. Examples of electronic devices include, but are not limited to, devices powered by iOS, Android, Microsoft, or other operating systems, and alternatively, electronic devices include mobile phones, tablet computers, wearable devices, security devices, smart TVs, or personal computers. Wherein, the security equipment may include security camera equipment.

Fig. 18b is a schematic diagram of a board-level connection between a first device and a second device provided by some embodiments of the present application. As shown in Fig. 18b, taking the first device as a camera module and the second device as a mobile phone as an example, the mobile phone Including a mainboard, the mainboard includes an Application Processor (AP), and the mainboard is connected to the camera module through a connector (Band to Board, BTB) and a flexible printed circuit (Flexible Printed Circuit, FPC). Among them, the BTB is mainly used to connect the camera module and the main board. Usually, the BTB includes multiple CSI-2 signal pins; the FPC is full of CSI-2 signal transmission lines to cooperate with the BTB to complete the connection between the camera module and the main board.

Fig. 18c is a schematic diagram of a board-level connection between a first device and a second device provided by other embodiments of the present application. As shown in Fig. 18c, taking the first device as a mobile phone and the second device as a display screen as an example, the mobile phone Including the main board, the main board includes the AP, and the display screen (not shown in the figure) includes the mobile phone display driver IC (Display Driver IC, DDIC for short) module. The main board is connected with the DDIC module through BTB and FPC. Among them, the BTB is mainly used to connect the DDIC module and the main board. Usually, the BTB includes multiple DSI-2 signal pins; the FPC is full of DSI-2 signal transmission lines to cooperate with the BTB to complete the connection between the FFIC module and the main board. Among them, the DSI-2 protocol is a protocol interface developed by MIPI to connect the SoC and the DDIC.

Based on the above data transmission system, an embodiment of the present application provides a data transmission method, the method comprising:

If the environmental parameters of the transmission channel meet the conditions for enabling the first algorithm, the first device encodes the acquired transmission data through the first error detection and correction algorithm, generates first encoded data, and sends the first encoded data to the second device . The second device receives the encoded data; if it is determined that the conditions for enabling the first algorithm are met, the encoded data is verified by the first error detection and correction algorithm to generate transmission data; The error algorithm verifies the encoded data and generates the transmission data.

Wherein, the second error detection and correction algorithm is different from the first error detection and correction algorithm.

As an optional solution, FIG. 18d is a flowchart of a data transmission method provided by an embodiment of the present application. As shown in FIG. 18d , the method includes:

In step 100a, the first device determines that the environmental parameter of the transmission channel meets the first algorithm opening condition or meets the second algorithm opening condition. If the first algorithm opening condition is met, step 100b is executed; if the second algorithm opening condition is met, step 100b is executed. 100c.

In this embodiment of the present application, judging that the environment parameter of the transmission channel complies with the enabling condition of the first algorithm or the enabling condition of the second algorithm may be performed by the first device or the second device. As an optional solution, step 100a is performed by the first device.

If step 100a is performed by the second device, if the second device determines that the environmental parameters of the transmission channel meet the conditions for enabling the first algorithm, it returns the first environmental parameter state to the first device. The first environmental parameter state is, for example, the first error. The code rate state or the first packet loss rate state, and the first environment parameter state is used to indicate that the environment parameter complies with the opening condition of the first algorithm; if the second device determines that the environment parameter of the transmission channel meets the opening condition of the second algorithm, Then, the second environment parameter state is returned to the first device. The second environment parameter state is, for example, the second bit error rate state or the second packet loss rate state. The second environment parameter state is used to indicate that the environment parameter conforms to the first Second algorithm enable condition.

Step 100b: The first device encodes the acquired transmission data through a first error detection and correction algorithm, generates first encoded data, sends the first encoded data to the second device, and proceeds to step 100d.

Step 100c: The first device encodes the acquired transmission data through a second error detection and correction algorithm, generates second encoded data, and sends the second encoded data to the second device.

Step 100d, the second device receives the encoded data.

In step 100e, if the second device determines that the first algorithm enabling condition is met, the encoded data is verified by the first error detection and correction algorithm to generate transmission data; An error correction algorithm verifies the encoded data to generate transmission data.

In this embodiment of the present application, the first device may acquire the environmental parameters of the transmission channel, and determine that the environmental parameters of the transmission channel meet the first algorithm enabling condition or the second algorithm enabling condition.

As an optional solution, if the environmental parameters of the transmission channel include the bit error rate, the first device acquiring the environmental parameters of the transmission channel may include: the first device sends the first sequence and the second sequence to the second device in sequence, for the second device to count the number of bits of the correct second sequence received, and the first sequence is used to implement state machine equalization training; receive the number of bits of the correct second sequence sent by the second device; The bit error rate is calculated according to the correct number of bits of the second sequence sent by the second device and the total number of bits of the second sequence sent by the second device. The first device judging that the environmental parameters of the transmission channel meet the conditions for enabling the first algorithm or the enabling conditions for the second algorithm includes: the first device judging whether the bit error rate is greater than or equal to the first threshold; A threshold value indicates that the environmental parameters of the transmission channel meet the enabling conditions of the first algorithm; if it is determined that the bit error rate is less than the first threshold, it indicates that the environmental parameters of the transmission channel meet the enabling conditions of the second algorithm.

As another optional solution, if the environment parameter of the transmission channel includes the system transmission rate, the first device acquiring the environment parameter of the transmission channel includes: the first device reading the system transmission rate from the speed cut state register. The first device judging that the environmental parameters of the transmission channel meet the conditions for enabling the first algorithm or the enabling conditions for the second algorithm includes: the first device judging whether the system transmission rate is greater than or equal to the second threshold; Two thresholds, indicating that the environmental parameters of the transmission channel meet the opening conditions of the first algorithm; if it is determined that the system transmission rate is less than the second threshold, it indicates that the environmental parameters of the transmission channel meet the opening conditions of the second algorithm. For example, for this case, see step 506 and step 508 in Fig. 23 .

As another optional solution, if the environmental parameter of the transmission channel includes the packet loss rate, the first device acquiring the environmental parameter of the transmission channel includes: the first device sends a test data packet to the second device, and records the sent test data packet The number of data packets; the number of correct test data packets received according to the statistics returned by the second device; the packet loss is calculated according to the number of correct test data packets and the number of sent test data packets Rate. The first device judging that the environmental parameters of the transmission channel meet the conditions for enabling the first algorithm or the enabling conditions for the second algorithm includes: the first device judging whether the packet loss rate is greater than or equal to the third threshold; The three thresholds indicate that the environmental parameters of the transmission channel meet the enabling conditions of the first algorithm; if it is determined that the packet loss rate is less than the third threshold, it indicates that the environmental parameters of the transmission channel meet the enabling conditions of the second algorithm. For example, for this situation, please refer to step 606 and step 612 in FIG. 25 .

In this embodiment of the present application, the second device may also acquire environmental parameters of the transmission channel, and determine that the environmental parameters of the transmission channel meet the first algorithm enabling condition or the second algorithm enabling condition.

As an optional solution, if the environmental parameter of the transmission channel includes the bit error rate, the second device receives the first sequence and the second sequence sent in sequence by the first device, and the first sequence is used to implement state machine equalization training; Calculate the bit error rate according to the received correct number of bits of the second sequence and the total number of bits of the second sequence sent; if the bit error rate meets the first algorithm enabling condition, send the first device to the first device. A bit error rate status, the first bit error rate status is used to indicate that the bit error rate meets the enabling condition of the first algorithm; if the bit error rate meets the enabling condition of the second algorithm, the first bit error rate status is sent to the first The device sends a second bit error rate status, where the second bit error rate status is used to indicate that the bit error rate complies with the condition for enabling the second algorithm. The second device judging that the environmental parameters of the transmission channel meet the conditions for enabling the first algorithm or the enabling conditions for the second algorithm includes: the second device judging whether the bit error rate is greater than or equal to the first threshold; A threshold value indicates that the environmental parameters of the transmission channel meet the enabling conditions of the first algorithm; if it is determined that the bit error rate is less than the first threshold, it indicates that the environmental parameters of the transmission channel meet the enabling conditions of the second algorithm. Wherein, the first device can know that the bit error rate meets the enabling condition of the first algorithm according to the first bit error rate state, and can use the first error detection and correction algorithm to perform encoding; the first device can know the bit error according to the second bit error rate state If the rate meets the enabling condition of the second algorithm, the second error detection and correction algorithm can be used for encoding. For example, for this situation, please refer to steps 406 to 416 and step 446 in FIG. 20 .

As another optional solution, if the environmental parameter of the transmission channel includes the packet loss rate, the second device receives the test data packet sent by the first device; according to the number of received correct test data packets and the sent test data The number of packets, and the packet loss rate is calculated; if the packet loss rate meets the conditions for enabling the first algorithm, the first packet loss rate status is sent to the first device, and the first packet loss rate status is used to indicate The packet loss rate complies with the enabling condition of the first algorithm; if the packet loss rate meets the enabling condition of the second algorithm, a second packet loss rate status is sent to the first device, the first packet loss rate status It is used to indicate that the packet loss rate complies with the condition for enabling the second algorithm. The second device judging that the environmental parameters of the transmission channel meet the conditions for enabling the first algorithm or the enabling conditions for the second algorithm includes: the second device judging whether the packet loss rate is greater than or equal to the third threshold; The three thresholds indicate that the environmental parameters of the transmission channel meet the enabling conditions of the first algorithm; if it is determined that the packet loss rate is less than the third threshold, it indicates that the environmental parameters of the transmission channel meet the enabling conditions of the second algorithm. Wherein, the first device can learn that the packet loss rate conforms to the enabling condition of the first algorithm according to the first packet loss rate state, and can use the first error detection and correction algorithm for encoding; the first device can learn the packet loss rate according to the second packet loss rate state If the rate meets the enabling condition of the second algorithm, the second error detection and correction algorithm can be used for encoding.

In this embodiment, the method further includes: collecting raw data by the first device; converting the encoding format of the raw data to generate the transmission data. The original data includes but is not limited to: image data stream, video data stream, instruction data, storage data or network data, wherein the network data is, for example, 2G/3G/4G/5G data or WLAN data. For example, the first device performing encoding format conversion on the original data to generate the transmission data includes: performing binary encoding format conversion on the original data to generate the transmission data.

As an optional solution, after the first device determines that the environmental parameters of the transmission channel meet the conditions for enabling the first algorithm, the first device executes the step of collecting raw data; or after the first device determines that the environmental parameters of the transmission channel meet the first algorithm enabling conditions; After an algorithm is turned on, the first device performs the step of collecting raw data. For example, in this case, refer to step 510 and step 538 in FIG. 23 . For another example, in this case, refer to step 510 and step 538 in FIG. 23 .

As another optional solution, after the second device determines that the environmental parameter of the transmission channel meets the first algorithm enabling condition, and returns the first bit error rate state to the first device, the first device performs the step of collecting the original data; Or after the second device determines that the environmental parameter of the transmission channel meets the first algorithm enabling condition, and returns the first bit error rate state to the first device, the first device performs the step of collecting the original data. For example, for this situation, please refer to step 418 and step 448 in FIG. 20 .

As another optional solution, before the first device encodes the acquired transmission data by using the first error detection and correction algorithm and before encoding the acquired transmission data by using the second error detection and correction algorithm, the acquisition of the original data is performed. A step of. In this case, the first device does not need to wait for the environmental parameters of the transmission channel to meet the first algorithm enabling condition or the judgment result that meets the second algorithm enabling condition, and can collect raw data in real time. For example, in this case, refer to step 614 and step 650 in FIG. 25 .

In this embodiment of the present application, judging that the environmental channel parameters meet the conditions for enabling the first algorithm may further include: the bit error rate is greater than or equal to a first threshold, the system transmission rate is greater than or equal to a second threshold, and the packet loss rate is greater than or equal to or any combination equal to the third threshold.

In this embodiment of the present application, judging that the transmission channel environment parameters meet the conditions for enabling the second algorithm may further include: the bit error rate is less than a first threshold, the system transmission rate is less than a second threshold, and the packet loss rate is less than a third threshold any combination of .

In an optional embodiment, the first error detection and correction algorithm includes at least two error detection and correction algorithms, the second error detection and correction algorithm includes at least one error detection and correction algorithm, and the first error detection and correction algorithm includes The number of error detection and correction algorithms is greater than the number of error detection and correction algorithms in the second error detection and correction algorithm.

As an optional solution, the first error detection and correction algorithm includes an FEC algorithm, a CRC algorithm and an ECC algorithm (for example, steps 420 to 444 in FIG. 20 and steps 512 to 524 in FIG. 23 ); or , the first error detection and correction algorithm includes an FEC algorithm and a CRC algorithm; or, the first error detection and correction algorithm includes an FEC algorithm and an ECC algorithm. For example, in steps 420 to 444 in FIG. 20 and steps 512 to 524 in FIG. 23 , the transmission data includes the first data block, and the first encoded data includes the fourth data block. It should be noted that the FEC algorithm includes but is not limited to the Reed-Solomon codes (Reed-solomon codes, RS code for short) algorithm.

As another optional solution, the second error detection and correction algorithm includes an FEC algorithm (for example, steps 654 to 666 in FIG. 25 ); or, the second error detection and correction algorithm includes a CRC algorithm; or, The second error detection and correction algorithm includes an ECC algorithm; or, the second error detection and correction algorithm includes a CRC algorithm and an ECC algorithm (for example, steps 450 to 468 in FIG. 20 and steps 540 to 540 in FIG. 23 ) step 558). For example, in steps 654 to 666 in FIG. 25 , the transmission data includes the first data block, and the first encoded data includes the third data block. For another example, in steps 450 to 468 in FIG. 20 and steps 540 to 558 in FIG. 23 , the transmission data includes the first data block, and the first encoded data includes the fifth data block.

In this embodiment of the present application, the first encoded data includes an indication field, and the indication field of the first encoded data is used to indicate that the environment parameter complies with the condition for enabling the first algorithm; and/or the second encoded data The data includes an indication field, and the indication field of the second encoded data is used to indicate that the environmental parameter complies with the condition for enabling the second algorithm.

If only the first encoded data includes an indication field, the indication field is, for example, 1. In this case, determining by the second device that the conditions for enabling the first algorithm are met specifically includes: determining that the encoded data includes an indication field; determining that the enabling conditions for the second algorithm are met by the second device specifically includes: determining that the encoded data contains an indication field; Indication field is not included.

If only the second encoded data includes an indication field, the indication field is, for example, 1. In this case, determining by the second device that the conditions for enabling the first algorithm are met specifically includes: determining by the second device that the encoded data does not include an indication field; determining by the second device that the enabling conditions for the second algorithm are met specifically includes: determining that the second device meets the enabling conditions for the second algorithm. The out-coded data includes an indication field.

If both the first encoded data and the second encoded data include an indication field, the indication field in the first encoded data and the indication field in the second encoded data may be set to different values. The indication field in the first encoded data is a first value, for example, the first value is 1, and the indication field in the second encoded field is a second value, and the second value is, for example, 0. In this case, determining by the second device that the conditions for enabling the first algorithm are met specifically includes: the second device determining that the indication field in the encoded data is 1; and determining by the second device that the conditions for enabling the second algorithm are met may specifically include: the second The device determines that the indication field in the encoded data is 0. Wherein, the first value is used to indicate that the environmental parameter complies with the enabling condition of the first algorithm, and the second value is used to indicate that the environmental parameter complies with the enabling condition of the second algorithm.

The indication fields include reserved fields or newly added fields. When the indication field includes a newly added field, the indication field is, for example, a bit error rate confirmation field (as shown in step 428 in FIG. 20 ), a transmission rate confirmation field (as shown in step 520 in FIG. 23 ), or a packet loss rate confirmation field ( Step 622 in Figure 25).

In the embodiment of the present application, the checking of the encoded data by using the first error detection and correction algorithm includes: if it is determined that the encoded data includes an indication field, performing FEC check on the encoded data, and the indication field is used to indicate The environment parameter conforms to the condition for enabling the first algorithm; CRC check and/or ECC check is performed on the encoded data after the FEC check. For example, for this situation, please refer to step 436 and step 438 in FIG. 20 , and step 528 and step 530 in FIG. 23 .

In the embodiment of the present application, the checking of the encoded data by the first error detection and correction algorithm includes: performing FEC checking on the encoded data; if it is determined that the encoded data includes an indication field, performing FEC checking on the encoded data. CRC check and/or ECC check, the indication field is used to indicate that the environment parameter complies with the enabling condition of the first algorithm. For example, in this case, please refer to step 636 to step 640 in FIG. 25 .

In the technical solution of the data transmission method provided by the embodiment of the present application, the first device selects a first error detection and correction algorithm to encode the transmission data according to the environmental parameters of the transmission channel meeting the conditions for enabling the first algorithm to generate the first encoded data, or the first The device selects the second error detection and correction algorithm to encode the transmission data to generate the second encoded data according to the environmental parameters of the transmission channel that meet the conditions for enabling the second algorithm, and the second device receives the encoded data. The first error detection and correction algorithm verifies the encoded data to generate transmission data. If it is determined that the conditions for enabling the second algorithm are met, the second error detection and correction algorithm is used to verify the encoded data to generate transmission data. The error detection algorithm performs error detection and correction processing on the transmission data in the data transmission process, thereby improving the data transmission efficiency on the basis of ensuring the reliability of the data transmission.

FIG. 19 is a schematic structural diagram of a data transmission system provided by some embodiments of the present application. As shown in FIG. 19 , the data transmission system is, for example, a MIPI CSI-2 D-PHY data transmission system, and the data transmission system adopts CSI-2 Protocol Architecture. As shown in FIG. 19 , the system includes a first device and a second device, the first device includes an image processing unit and a sending device, and the second device includes a main processor unit and a receiving device. Wherein, the first device is a camera module, the image processing unit is a camera sensor (Sensor), and the sending module is an interface circuit; the second device is a motherboard, then the main processor unit is an AP, and the receiving module is an interface circuit. The sending device includes a first format conversion module, a protocol sending unit and a PHY layer sending module. The protocol sending unit includes an ECC encoding module, a CRC encoding module and an FEC encoding module. The receiving device includes a second format conversion module, a protocol receiving unit and a PHY layer receiving module. The protocol receiving unit includes a packet header ECC decoding module, a clean core CRC decoding module and an FEC decoding module, wherein the PHY layer transmitting module and the PHY layer receiving module are between the The communication connection is made through a transmission channel, and a transmission channel is used as an example for description in FIG. 19 . The protocol sending unit includes a CSI-2 sending unit, the protocol receiving unit includes a CSI-2 receiving unit, the PHY layer sending module includes a D-PHY sending module, and the PHY layer receiving module includes a D-PHY receiving module.

FIG. 20 is a flowchart of a data transmission method provided by some embodiments of the present application. As shown in FIG. 20 , the method includes:

Step 402: The second device configures the working parameters of the first device.

As shown in FIG. 19 , the main processor unit of the second device configures the working parameters of the image processing unit.

The user clicks the icon of the camera APP of the second device to open the camera APP, so as to trigger the second device to configure the working parameters of the first device.

Step 404: The first device sends the first sequence to the second device.

FIG. 21 is a schematic diagram of the data format of the training code stream in some embodiments of the present application. As shown in FIG. 21 , when the link is in a high speed (High Speed, HS for short) transmission state, the first device sends the data to the second device through the transmission channel A training stream to complete the training process of the system. The protocol sending unit (as shown in Figure 19) sends the training code stream to the protocol receiving unit through the transmission channel. Specifically, the protocol sending unit sends the training code stream to the PHY layer sending module, the PHY layer sending module sends the training code stream to the PHY layer receiving module through the transmission channel, and then the PHY layer receiving module sends the training code stream to the protocol receiving unit to Implement the CSI-2 state machine equalization training process.

As shown in Figure 21, the training code stream includes a data type sequence, an equalization sequence, a first sequence, a second sequence and a third sequence. In the process of sending the training code stream by the first device, first, the first device sends a data type sequence to the second device, and the data type sequence includes "Control Word", and "Control Word" can indicate that the training code stream is a control packet, For example, the Control Word" may be 0101. Then, the first device sends an equalization (Equalization) sequence to the second device. Next, the first device sends a first sequence to the second device, and the first sequence may include a pseudo-random binary number sequence (Pseudo-Random Binary Sequence, PRBS for short) 15 sequence, for example, the first device can send 1 million PRBS15 sequences to the second device to implement the state machine equalization training process.

Step 406: The first device sends the second sequence to the second device.

As shown in FIG. 21 , during the process of sending the training code stream by the first device, the first device sends a second sequence to the second device, and the second sequence may include a PRBS31 sequence. For example, the first device may send a second sequence to the second device. 1 million PRBS31 sequences.

Step 408: The first device sends the third sequence to the second device.

As shown in FIG. 21 , during the process of sending the training code stream by the first device, the first device sends a third sequence to the second device, and the third sequence may include an idle (IDLE) sequence. The second device can directly discard the IDLE sequence, ignore the IDLE sequence, and keep the link recovery clock locked all the time.

Step 410: The second device counts the received bits of the correct second sequence.

During the time period when the first device sends the IDLE sequence, the second device counts the correct number of bits of the second sequence. The protocol receiving unit (as shown in FIG. 19 ) counts the received bits of the correct second sequence.

Step 412: The second device calculates the bit error rate according to the correct number of bits of the second sequence and the total number of bits of the second sequence sent by the first device.

During the time period when the first device sends the IDLE sequence, the second device calculates the bit error rate. Specifically, the second device calculates the bit error rate by using the formula 1-n/N, where n is the correct number of bits of the second sequence, and N is the total number of bits of the second sequence. The protocol receiving unit (as shown in Figure 19) calculates the bit error rate.

Step 414: The second device determines whether the bit error rate is greater than or equal to the first threshold, and if so, executes step 416; if not, executes step 446.

During the time period when the first device sends the IDLE sequence, the second device determines whether the bit error rate is greater than or equal to the first threshold. The first threshold is for example: 1e-12, 1e-15 or 1e-10. The protocol receiving unit (as shown in FIG. 19 ) judges whether the bit error rate is greater than or equal to the first threshold.

As an optional solution, steps 406 to 416 and step 446 can be replaced by: the first device sends the first sequence and the second sequence to the second device in sequence, so that the second device can count the received correct The number of bits of the second sequence of The bit error rate is calculated from the number of bits of the sequence and the total number of bits of the second sequence sent. The first device determines whether the bit error rate is greater than or equal to the first threshold.

Step 416: The second device returns the first bit error rate status to the first device.

If the second device determines that the bit error rate is greater than or equal to the first threshold, it indicates that the bit error rate is relatively large. At this time, the second device generates the first bit error rate state corresponding to the judgment result that the bit error rate is greater than or equal to the first threshold. (Bit Error Rate State, referred to as BER State), for example, the first bit error rate state may be 1.

Then, before the time period during which the first device sends the IDLE sequence ends, the protocol receiving unit of the second device returns the first bit error rate status to the protocol sending unit of the first device through the auxiliary channel (AUX).

The time period for sending the third sequence can be used for calculating and judging the bit error rate, so that the steps of calculating and judging the bit error rate can be completed in the process of sending the training code stream.

Step 418: The first device collects the image data stream, and converts the encoding format of the image data stream to generate a first data block.

The image processing unit (as shown in Figure 19) collects the image data stream, and sends the collected image data stream to the first format conversion module (as shown in Figure 19), and the first format conversion module performs encoding format conversion on the image data stream .

Step 420: The first device adds a data packet header to the first data block.

FIG. 22 is a schematic diagram of the format of a data block transmitted based on D-PHY in some embodiments of the present application. As shown in FIG. 22 , the first format conversion module (as shown in FIG. 19 ) performs binary encoding format conversion on the image data stream, to form the "Payload". The packet header can include Data ID, 16-bit WC and VCX. The first format conversion module sends the first data block to which the data packet header is added to the protocol sending unit (as shown in FIG. 19 ).

Step 422: The first device performs ECC encoding on the data packet header to generate a first ECC field, and performs CRC encoding on the first data block to generate a CRC field.

As shown in FIG. 22 , the protocol sending unit performs ECC encoding on the data packet header through the packet header ECC encoding module (as shown in FIG. 19 ) to generate the first ECC field. The packet header ECC encoding module performs ECC encoding on the Data ID, WC, and VCX through a 6-bit extended Hamming code to generate a first ECC field, where the ECC field is a 6-bit field. It should be noted that the ECC field shown in FIG. 22 includes the first ECC field.

As shown in Figure 22, the protocol sending unit performs CRC coding on the first data block through the clean core CRC coding module (as shown in Figure 19) to generate a CRC field. The net core CRC encoding module performs CRC encoding on "Payload" through a polynomial to generate a CRC field. The polynomial is, for example, X ¹⁶ +X ¹² +X ⁵ +X ⁰ , and the CRC field is a 16-bit field.

Step 424: The first device inserts the first ECC field and the CRC field into the packet header and the packet trailer of the first data block to generate a second data block.

As shown in Figure 22, the protocol sending unit (as shown in Figure 19) places the first ECC field and the CRC field at the header and end of the "Payload" packet, respectively. At this time, Data ID, WC, and VCX are located in the second data block, respectively. the specified location. It should be noted that: the ECC field shown in FIG. 22 is the first ECC field.

Step 426: The first device performs FEC encoding on different data segments of the second data block, generates an FEC check code corresponding to each data segment, and places each FEC check code at the end of the corresponding data segment.

As shown in FIG. 22 , if the protocol sending unit (as shown in FIG. 19 ) determines that the first bit error rate status is 1, the FEC encoding module divides the second data block into multiple data segments, for example, multiple data segments The segment may include second data blocks Part 0 to Part N-1. The FEC encoding module performs FEC encoding on different data segments of the second data block, generates an FEC parity (FEC Parity) corresponding to each data segment, and places each FEC parity at the end of the corresponding data segment.

Step 428: The first device adds an indication field before the second data block to generate a third data block.

In this embodiment, as an optional solution, the indication field is a newly added field, and the indication field is, for example, a bit error rate confirmation (Bit Error Rate Ensure, BER EN for short) field. The bit error rate confirmation field is used to indicate that the bit error rate is greater than or equal to the first threshold. As shown in Figure 22, the protocol sending unit adds a BER EN field before the second data block through the FEC encoding module (as shown in Figure 19). The value of the bit error rate confirmation field is, for example, 1.

As another optional solution, the indication field is a reserved field. In this case, step 428 may include: the first device sets the value of the reserved field, so that the reserved field is used to indicate that the bit error rate is greater than or equal to the first threshold. . The value of the reserved field is, for example, 1.

Step 430: The first device sets the SoT flag at the start position of the third data block and the EoT flag at the end position of the third data block to form a fourth data block.

As shown in FIG. 22 , the protocol sending unit (as shown in FIG. 19 ) sets the SoT flag at the start position of the third data block and the EoT at the end position of the third data block to form the fourth data block.

Step 432: The first device sends the fourth data block to the second device.

As shown in Figure 22, the protocol sending unit (shown in Figure 19) sends the fourth data block to the PHY layer sending module (shown in Figure 19), and the PHY layer sending module sends the fourth data block to the PHY through the transmission channel Layer receiving module (as shown in Figure 19), the PHY layer receiving module sends the fourth data block to the protocol receiving unit (as shown in Figure 19).

Step 434: The second device removes the SoT and EoT of the fourth data block to generate a third data block.

As shown in FIG. 22, the protocol reception unit (as shown in FIG. 19) removes the SoT and EoT of the fourth data block to generate the third data block.

Step 436: The second device parses the third data block.

The protocol receiving unit (as shown in FIG. 19 ) parses the third data block.

Step 438: If the second device parses the indication field, it performs FEC detection and error correction check on the third data block to generate a second data block.

If the protocol receiving unit (as shown in Figure 19) parses the indication field, the judgment result that the bit error rate is greater than or equal to the first threshold can be obtained through the indication field, and then it is determined that the first error detection and correction algorithm is adopted, and the FEC decoding module ( As shown in FIG. 19 ), the FEC decoding module performs FEC verification on the third data block through the RS code decoding algorithm to generate an FEC verification result. FEC verification results include verification success, correctable error results or uncorrectable error results.

If the protocol receiving unit recognizes that the FEC check result includes a correctable error result, it corrects the erroneous data of the third data block, and unpacks the third data block to generate the second data block.

If the protocol receiving unit recognizes that the FEC verification result includes verification success, indicating that there is no erroneous data in the third data block, it can directly unpack the third data block to generate the second data block.

If the protocol receiving unit recognizes that the FEC check result includes an uncorrectable error result, the third data block will be discarded, skipped directly or retransmitted. In this case, the developer can determine the processing of the third data block. Way.

Step 440: The second device performs CRC check on the CRC field in the second data block to generate a CRC check result.

The protocol receiving unit (as shown in FIG. 19 ) divides the CRC field in the second data block and the polynomial by modulo 2 through the clean core CRC decoding module to obtain the remainder, which is the CRC check result. If the CRC check result is 0, it indicates that the received "Payload" is correct data; if the CRC check result is not 0, it indicates that the received "Payload" is wrong data. Wherein, the polynomial may include X ¹⁶ +X ¹² +X ⁵ +X ⁰ .

Step 442: The second device performs ECC verification on the data packet header in the second data block, and generates an ECC verification result.

As shown in Figure 22, the protocol receiving unit performs ECC encoding on the Data ID, WC and VCX in the packet header through the packet header ECC decoding module (as shown in Figure 19) to generate the second ECC field, and the first ECC field and the second ECC The field is XORed to obtain the ECC check result. If the ECC check result is 0, it indicates that the data packet header is correct; if the ECC check result is not 0 and the ECC check result indicates a 1-bit error and an error bit, it indicates that the error bit of the data packet header needs to be corrected; if If the ECC check result is not 0 and the ECC check result indicates that there are more than 2-bit errors, it indicates that an uncorrectable error has occurred in the data packet header.

Step 444, if the second device recognizes that the verification result is 0 and the verification result is 0, it performs unpacking processing on the second data block to generate the first data block, and performs encoding format conversion on the first data block to generate the image data stream, Process ends.

If the protocol receiving unit (as shown in FIG. 19 ) recognizes that the verification result is 0 and the verification result is 0, the packet header of the second data block is removed to obtain the first data block.

The second format conversion module (as shown in FIG. 19 ) converts the encoding format of the first data block to generate an image data stream, uploads the image data stream to the main processor unit, and uploads the image data stream to the main processor unit. Specifically, the second format conversion module performs pixel image coding format conversion on the first data block to generate an image data stream, and uploads the image data stream to the main processor unit.

Step 446: The second device returns the second bit error rate status to the first device.

If the second device determines that the bit error rate is less than the first threshold, it indicates that the bit error rate is small. At this time, the second device generates a second bit error rate state (Bit Error Rate corresponding to the judgment result that the bit error rate is less than the first threshold). State, referred to as BER State), for example, the second bit error rate state may be 0.

Then, before the time period during which the first device sends the IDLE sequence ends, the protocol receiving unit of the second device returns the second bit error rate status to the protocol sending unit of the first device through the auxiliary channel (AUX).

Step 448: The first device collects the image data stream, and converts the encoding format of the image data stream to generate a first data block.

The image processing unit (as shown in Figure 19) collects the image data stream, and sends the collected image data stream to the first format conversion module (as shown in Figure 19), and the first format conversion module performs encoding format conversion on the image data stream , generate the first data block.

Step 450: The first device adds a data packet header to the first data block.

As shown in FIG. 22 , the first format conversion module (as shown in FIG. 19 ) performs binary encoding format conversion on the image data stream to form “Payload”. The packet header can include Data ID, 16-bit WC and VCX. The first format conversion module sends the first data block to which the data packet header is added to the protocol sending unit (as shown in FIG. 19 ).

Step 452: The first device performs ECC encoding on the data packet header to generate a first ECC field, and performs CRC encoding on the first data block to generate a CRC field.

As shown in FIG. 22 , the protocol sending unit encodes the data packet header through the packet header ECC encoding module (as shown in FIG. 19 ) to generate the first ECC field. The packet header ECC encoding module performs ECC encoding on the Data ID, WC, and VCX through a 6-bit extended Hamming code to generate a first ECC field, where the ECC field is a 6-bit field. It should be noted that the ECC field shown in FIG. 22 includes the first ECC field.

Step 454: The first device inserts the first ECC field and the CRC field into the packet header and the packet trailer of the first data block to generate a second data block.

As shown in Figure 22, the protocol sending unit (as shown in Figure 19) places the first ECC field and the CRC field at the header and end of the "Payload" packet, respectively. At this time, Data ID, WC, and VCX are located in the second data block, respectively. the specified location.

Step 456: The first device sets the SoT flag at the start position of the second data block and the EoT flag at the end position of the second data block to form a fifth data block.

As shown in FIG. 22 , the protocol sending unit (as shown in FIG. 19 ) sets the SoT flag at the beginning of the second data block and the EoT flag at the end of the second data block to form a fifth data block.

Step 458: The first device sends the fifth data block to the second device.

As shown in Figure 22, the protocol sending unit (shown in Figure 19) sends the fifth data block to the PHY layer sending module (shown in Figure 19), and the PHY layer sending module sends the fifth data block to the PHY through the transmission channel Layer receiving module (as shown in Figure 19), the PHY layer receiving module sends the fifth data block to the protocol receiving unit (as shown in Figure 19).

Step 460: The second device removes the SoT and EoT of the fifth data block to generate a second data block.

As shown in FIG. 22, the protocol reception unit (as shown in FIG. 19) removes the SoT and EoT of the fifth data block to generate the second data block.

Step 462: The second device parses the second data block.

The protocol receiving module parses the second data block through the FEC decoding module.

Step 464: If the second device does not parse out the indication field, it performs CRC check on the CRC field in the second data block to generate a CRC check result.

If the protocol receiving unit (as shown in Figure 19) does not parse the indication field, it obtains the judgment result that the bit error rate is less than the first threshold, and then determines that the second error detection and correction algorithm is used, and activates the clean core CRC decoding module (as shown in the figure). 19), CRC check and ECC check are performed by the clean core CRC decoding module. It should be noted that: in this embodiment, if the second device does not parse out the indication field, it can also perform step 466 first, and then perform the CRC check on the CRC field in the second data block in step 464 to generate CRC check result steps.

The protocol receiving unit (as shown in FIG. 19 ) divides the CRC field in the second data block and the polynomial by modulo 2 through the clean core CRC decoding module to obtain the remainder, which is the CRC check result. If the CRC check result is 0, it indicates that the received "Payload" is correct data; if the CRC check result is not 0, it indicates that the received "Payload" is wrong data. The polynomial is, for example: X ¹⁶ +X ¹² +X ⁵ +X ⁰ .

Step 466: The second device performs ECC verification on the data packet header in the second data block, and generates an ECC verification result.

Step 468: If the second device recognizes that the verification result is 0 and the verification result is 0, it unpacks the second data block to generate a first data block, and performs encoding format conversion on the first data block to generate an image data stream.

As shown in FIG. 22 , if the protocol receiving unit (as shown in FIG. 19 ) recognizes that the verification result is 0 and the verification result is 0, the packet header of the second data block is removed to obtain the first data block.

The second format conversion module converts the encoding format of the first data block to generate an image data stream, uploads the image data stream to the main processor unit, and uploads the image data stream to the main processor unit. Specifically, the second format conversion module performs pixel image coding format conversion on the first data block to generate an image data stream, and uploads the image data stream to the main processor unit.

It should be noted that: Steps 420 to 444 in FIG. 20 can be replaced with: the encoding scheme using the FEC algorithm and the CRC algorithm; or the encoding scheme using the FEC algorithm and the ECC algorithm. Steps 450 to 468 in FIG. 20 can be replaced with: a scheme of performing verification through an FEC algorithm; or a scheme of performing verification through a CRC algorithm; or a scheme of performing verification through an ECC algorithm.

In the technical solutions of the embodiments of the present application, the bit error rate is obtained by detecting the transmission channel environment, and when the bit error rate is large, a combination of the FEC algorithm, the CRC algorithm and the ECC algorithm is selected to detect and correct the transmission data in the data transmission process. Error processing realizes error detection and correction of multi-bit error data, thereby improving the reliability of data transmission; when the bit error rate is small, the combination of CRC algorithm and ECC algorithm is selected to detect and correct the transmission data during the data transmission process. , which avoids the situation of large data redundancy during error detection and correction processing, thereby improving the data transmission efficiency. Using the data transmission method of this embodiment improves data transmission efficiency on the basis of ensuring data transmission reliability. In the embodiment of the present application, in the case of ensuring maximum transmission efficiency and minimum power consumption, especially when the bit error rate is relatively large, multi-bit error correction can be implemented, thereby improving the reliability of data transmission.

FIG. 23 is a flowchart of a data transmission method provided by other embodiments of the present application. As shown in FIG. 23 , the difference between FIG. 23 and the data transmission method shown in FIG. 20 is: Error detection and correction algorithm or second error detection and correction algorithm, the difference steps can be as follows:

Step 504: The first device sends the first sequence to the second device.

First, the first device sends a data type sequence to the second device, where the data type sequence includes "Control Word", and "Control Word" may indicate that the training code stream is a control packet, for example, the "Control Word" may be 0101. Then, the first device sends an equalization (Equalization) sequence to the second device. Next, the first device sends a first sequence to the second device, the first sequence may include a PRBS15 sequence, for example, the first device may send 1 million PRBS15 sequences to the second device to implement a state machine equalization training process. Since this embodiment does not need to calculate the bit error rate in the future, it is unnecessary to send the second sequence and the third sequence in the future, thereby improving the training efficiency.

The protocol sending unit (as shown in FIG. 19 ) sends the first sequence to the protocol receiving unit through the transmission channel.

Step 506: The first device reads the system transmission rate from the speed cut state register.

The protocol sending unit (shown in Figure 19) reads the system transfer rate from the speed cut status register.

Step 508: The first device determines whether the system transmission rate is greater than or equal to the second threshold, and if so, executes step 510; if not, executes step 538.

As shown in FIG. 19 , the protocol sending unit determines whether the system transmission rate is greater than or equal to the second threshold. The second threshold is for example: 16Gbps, 32Gbps, 8Gbps, 28Gbps, 56Gbps, 10Gbps or 40Gbps.

In this embodiment, reference may be made to the description in step 402 for step 502 .

In this embodiment, steps 510 to 536 may refer to steps 418 to 444 . The difference is: in this embodiment, the indication field includes a transmission rate confirmation (Transport Rate Ensure, referred to as TR EN) field, and the transmission rate confirmation field is used to indicate that the system transmission rate is greater than or equal to the second threshold, and the transmission rate confirmation field The value is 1, for example. Or, the indication field is a reserved field. In this case, step 520 may include: the first device sets the value of the reserved field, so that the reserved field is used to indicate that the system transmission rate is greater than or equal to the second threshold, and the value of the reserved field is For example, 1. .

In this embodiment, steps 538 to 558 may refer to steps 448 to 448 .

In the technical solution of this embodiment, the first device directly reads the system transmission rate from the speed-cut state register, and selects a suitable error detection and correction algorithm according to the transmission rate, without obtaining the bit error rate by sending the second sequence, reducing the need for The frequent interaction process between the first device and the second device improves the training efficiency of the system.

FIG. 24 is a schematic structural diagram of a data transmission system provided by other embodiments. As shown in FIG. 24 , the data transmission system is, for example, an HDMI data transmission system. The data transmission system may include a first device and a second device. The first device Including a video data processing unit and a sending device, the second device includes a load (sink) unit and a receiving device, the sending device and the receiving device are communicatively connected through a transmission channel, the video data processing unit is communicatively connected with the sending device, and the load unit is communicatively connected with the receiving device. . Wherein, if the first device is a motherboard, the video data processing unit is an AP, and the sending module is an interface circuit; the second device is a display screen, the load unit is a display module, and the receiving device is an interface circuit. Wherein, the sending device includes a first format conversion module, a protocol sending unit and a PHY layer sending module. The protocol sending unit includes a TMDS CEC encoding module, an FEC encoding module and a channel encoding module. The receiving device includes a second format conversion module, a protocol receiving unit and a PHY layer receiving module. The protocol receiving unit includes a TMDS CEC decoding module, an FEC decoding module and a channel decoding module, wherein the PHY layer sending module and the PHY layer receiving module are transmitted through the transmission module. Channel communication connection.

FIG. 25 is a flowchart of a data transmission method provided by other embodiments. As shown in FIG. 25 , the method includes:

Step 602: The first device configures working parameters for the second device.

As shown in FIG. 24 , the video data processing unit of the first device configures working parameters for the load unit of the second device.

Specifically, in all actual use scenarios, the main board can configure the working parameters of the display module, so that the display module can work according to the requirements of the working parameters. The working parameters may include resolution, frame rate, interface rate, and the like.

Step 604: The first device sends the first sequence to the second device.

The protocol sending unit (as shown in Figure 24) sends the first sequence to the protocol receiving unit through the transmission channel.

Step 606: The first device sends a test data packet to the second device, and records the number of the sent test data packets.

As an optional solution, the test data packets may include application layer data packets or control data packets. The protocol sending unit of the first device (as shown in FIG. 24 ) records the number of sent test data packets through the register.

Step 608: The second device counts the number of correct test data packets received, and returns the counted number of correct test data packets to the first device.

The protocol receiving unit of the second device (as shown in FIG. 24 ) counts the number of correct test packets received, and returns the correct number of test packets to the protocol sending unit of the first device through the auxiliary channel.

Step 610: The first device calculates the packet loss rate according to the number of correct test data packets and the number of sent test data packets.

Specifically, the first device calculates the bit error rate by using the formula 1-m/M, where m is the number of correct test data packets, and N is the number of sent test data packets. The protocol sending unit (as shown in Figure 24) calculates the packet loss rate.

Step 612: The first device determines whether the packet loss rate is greater than or equal to the third threshold, and if so, executes step 616; if not, executes step 652.

The protocol sending unit (as shown in Figure 24) determines whether the packet loss rate is greater than or equal to the third threshold.

The packet loss rate is, for example: 0.1% to 1%.

As an optional solution, steps 606 to 612 in this embodiment may be replaced with: the second device receives the test data packet sent by the first device; The number of data packets, and the packet loss rate is calculated; if the packet loss rate meets the conditions for enabling the first algorithm, the first packet loss rate status is sent to the first device, and the first packet loss rate status is used for Indicates that the packet loss rate complies with the enabling condition of the first algorithm; if the packet loss rate meets the enabling condition of the second algorithm, a second packet loss rate status is sent to the first device, and the first packet loss rate The status is used to indicate that the packet loss rate complies with the condition for enabling the second algorithm. The second device judging that the environmental parameters of the transmission channel meet the conditions for enabling the first algorithm or the enabling conditions for the second algorithm includes: the second device judging whether the packet loss rate is greater than or equal to the third threshold; The three thresholds indicate that the environmental parameters of the transmission channel meet the enabling conditions of the first algorithm; if it is determined that the packet loss rate is less than the third threshold, it indicates that the environmental parameters of the transmission channel meet the enabling conditions of the second algorithm.

Step 614: The first device collects an image or video data stream, and performs encoding format conversion on the image data stream to generate a first data block.

The video data processing unit (as shown in FIG. 24 ) collects the image or video data stream, and sends the collected image or video data stream to the first format conversion module (as shown in FIG. 24 ).

As an alternative, step 614 may be performed after step 604 .

Step 616: The first device adds a data packet header to the first data block.

The first format conversion module (as shown in FIG. 24 ) performs binary encoding format conversion on the image or video data stream to form “Payload”.

FIG. 26 is a schematic diagram of the format of a data block transmitted based on HDMI in an embodiment of the present application. As shown in FIG. 26 , the data packet header includes a preamble (Premble), data synchronization information (Sync), and control/data information (C/D) and reserved fields (Rsvd). The protocol sending unit adds a preamble (Premble), data synchronization information (Sync), control/data information (C/D) and Rsvd to the header of the data block (Payload). Among them, the preamble (Premble) is used to indicate that "Payload" is various types of packet information (Data Island) or video pixel data (Video Data), wherein the content of the packet information includes audio data packets or image information packets.

Step 618: The first device performs ECC encoding on the first data block to generate a first ECC field, and performs CRC encoding on the first data block to generate a CRC field.

Specifically, the protocol sending unit uses the 6-bit extended Hamming code to perform ECC encoding on "Payload" through the TMDS CED encoding module to generate the first ECC field and the parity (Parity) field; the TMDS CED encoding module uses a 16-bit CRC pair "Payload" performs CRC encoding to generate a CRC (16-bit CRC) field and a parity (Parity) field. It should be noted that: the ECC field shown in FIG. 26 is the first ECC field.

Step 620: The first device adds the first ECC field and the CRC field to the end of the first data block.

As shown in Fig. 26, the protocol transmission unit (as shown in Fig. 24) adds the first ECC field and the CRC field to the end of "Payload".

Step 622: The first device adds an indication field to the header of the first data block to generate a second data block.

In this embodiment, as an optional solution, the indication field is a newly added field, and the indication field is, for example, a packet loss rate confirmation field (Packet Loss Rate Ensure, PLR EN for short). The packet loss rate confirmation field is used to indicate that the packet loss rate is greater than or equal to the third threshold.

The specific format of the generated second data block can be referred to as shown in FIG. 26 . The value of the packet loss rate confirmation field is, for example, 1. As shown in FIG. 26 , a parity (Parity) field may also be set after the first ECC field and the CRC field in the second data block.

As another optional solution, the indication field is a reserved field. In this case, step 622 may include: the first device sets a value of the reserved field, so that the reserved field is used to indicate that the packet loss rate is greater than or equal to the first threshold. . The value of the reserved field is, for example, 1.

Step 624: The first device performs channel coding on the second data block to generate an encoded second data block.

The protocol sending unit performs channel coding on the second data block through the channel coding module to generate the coded second data block.

Step 626: The first device divides the second data block into multiple FEC data blocks.

As shown in Figure 13, the FEC data block includes a Symbol data block (Super Block Payload). The protocol sending unit divides the second data block into multiple FEC data blocks through the FEC encoding module (as shown in FIG. 24 ).

Step 628: The first device performs FEC encoding on each FEC data block to generate an FEC check code.

As shown in Figure 13, the protocol sending unit uses the RS code encoding algorithm to perform FEC encoding on each FEC data block through the FEC encoding module to generate an FEC check code (RS Block/Parity).

Step 630: The first device adds the FEC check code to the end of the FEC data block to generate a third data block.

Step 632: The first device sends the third data block to the second device.

The protocol sending unit (as shown in Figure 24) sends the third data block to the PHY layer sending module (as shown in Figure 24), and the PHY layer sending module sends the third data block to the PHY layer receiving module through the transmission channel (as shown in Figure 24). 24), the PHY layer receiving module sends the third data block to the protocol receiving unit.

Step 634: The second device performs FEC detection and error correction check on the third data block to generate a second data block.

The protocol receiving unit uses the RS code decoding algorithm to perform FEC check on the third data block through the FEC decoding module (as shown in Figure 24), and generates an FEC check result. FEC verification results include verification success, correctable error results or uncorrectable error results.

If it is identified that the FEC verification result includes verification success, indicating that there is no erroneous data in the third data block, the third data block can be directly unpacked to generate the second data block.

Step 636: The second device parses the second data block.

The protocol receiving unit (as shown in Figure 24) parses the second data block.

Step 638: If the second device parses the indication field, it performs CRC check on the CRC field in the second data block to generate a CRC check result.

If the protocol receiving unit (as shown in Figure 24) parses the indication field, obtains the judgment result that the packet loss rate is greater than or equal to the third threshold, and then determines that the first error detection and correction algorithm is used, and activates the TMDS CEC decoding module (as shown in the figure). 24) by the TMDS CEC decoding module, the CRC field in the second data block and the polynomial are divided by modulo 2 to obtain the remainder, and the remainder is the CRC check result. The CRC check result can be 0 or not. Wherein, the polynomial may include X ¹⁶ +X ¹² +X ⁵ +X ⁰ .

Step 640: If the second device parses out the indication field, it performs ECC check on the first ECC field in the second data block to generate an ECC check result.

The TMDS CEC decoding module (as shown in Figure 24) performs ECC encoding on "Payload" in the second data block to generate a second ECC field, and performs XOR calculation on the first ECC field and the second ECC field to obtain the ECC check result . If the ECC check result is 0, it indicates that the "Payload" is correct; if the ECC check result is not 0 and the ECC check result indicates a 1-bit error and an error bit, it indicates that the error bit of "Payload" needs to be corrected ; If the ECC check result is not 0 and the ECC check result indicates that there are more than 2-bit errors, it means that an uncorrectable error has occurred in the "Payload". Among them, the TMDS CEC decoding module can use the same encoding rules as the TMDS CEC encoding module to perform ECC encoding on "Payload", that is, the TMDS CEC decoding module can perform ECC encoding on "Payload" through 6-bit extended Hamming code to generate a second ECC field.

It should be noted that: in this embodiment, if the second device parses the indication field, step 640 may be performed first, and then step 638 may be performed.

Step 642: The second device determines whether the CRC check result and the ECC check result are both 0, and if so, executes step 644; if it determines retransmission, executes step 626.

The protocol receiving unit (as shown in Figure 24) judges whether the CRC check result and the ECC check result are both 0.

Step 644: The second device unpacks the second data block to generate the first data block.

The protocol receiving unit (as shown in FIG. 24 ) unpacks the second data block to generate the first data block.

Specifically, the protocol protocol receiving unit removes the preamble (Premble), data synchronization information (Sync), control/data information (C/D), reserved field (Rsvd), and packet loss rate confirmation field (PLR) in the second data block EN)), the first ECC field, the CRC field, and the parity (Parity) field, so as to realize the first data block by depacketizing the second data block.

Step 646: The second device performs channel decoding on the first data block to generate the decoded first data block.

The protocol receiving unit performs channel decoding on the first data block through the channel decoding module (as shown in FIG. 24 ) to generate the decoded first data block.

Step 648: The second device converts the encoding format of the first data block to generate an image or video data stream, and the process ends.

The second format conversion module (as shown in FIG. 24 ) performs coding format conversion on the first data block, generates an image or video data stream, and uploads the image or video data stream to the load unit (as shown in FIG. 24 ). Specifically, the second format conversion module performs pixel image coding format conversion on the first data block to generate an image data stream, and uploads the image data stream to the load unit.

As an optional solution, if the second device recognizes that the ECC check result is not 0 and the ECC check result indicates that there are 1-bit errors and erroneous bits, it corrects the erroneous bits of the second data block, and corrects the error bits of the second data block. Two data blocks are unpacked to generate a first data block, then channel decoding is performed on the first data block to generate a decoded first data block, and pixel image coding format conversion is performed on the first data block to generate an image or video data stream.

As another optional solution, if the second device recognizes that the ECC verification result is not 0 and/or that the ECC verification result is not 0 and the verification result indicates that there are more than 2-bit errors, it will The second data block is discarded, skipped directly or retransmitted. In this case, the developer can determine the processing method of the data packet. If it is determined that the second data block is to be retransmitted, step 626 may be continued.

Step 650: The first device collects an image or video data stream, and performs encoding format conversion on the image or video data stream to generate a first data block.

As an alternative, step 650 may be performed after step 604 .

Step 652: The first device performs channel coding on the first data block to generate an encoded first data block.

The protocol sending unit (as shown in FIG. 24 ) performs channel coding on the first data block through the channel coding module to generate the coded first data block.

Step 654: The first device divides the first data block into multiple FEC data blocks.

Step 656: The first device performs FEC encoding on each FEC data block to generate an FEC check code.

Step 658: The first device adds the FEC check code to the end of the FEC data block to generate a fourth data block.

Step 660: The first device sends the fourth data block to the second device.

Step 662: The second device parses the fourth data block.

Step 664: If the second device fails to parse out the indication field, it performs FEC detection and error correction check on the fourth data block to generate the first data block.

If the protocol receiving unit (as shown in Figure 24) does not parse the indication field, obtain the judgment result that the packet loss rate is less than the third threshold, and then determine to use the second error detection and correction algorithm, and use the RS code decoding algorithm through the FEC decoding module. FEC verification is performed on the fourth data block to generate an FEC verification result. FEC verification results include verification success, correctable error results or uncorrectable error results.

If the protocol receiving unit identifies that the FEC check result includes a correctable error result, it corrects the erroneous data of the fourth data block, and unpacks the fourth data block to generate the first data block.

If the protocol receiving unit recognizes that the FEC verification result includes verification success, indicating that there is no erroneous data in the fourth data block, it can directly unpack the third data block to generate the first data block.

If the protocol receiving unit recognizes that the FEC check result includes an uncorrectable error result, the fourth data block will be discarded, skipped directly or retransmitted. In this case, the developer can determine the processing of the fourth data block. Way.

Step 666: The second device unpacks the fourth data block to generate the first data block.

Step 668: The second device performs channel decoding on the first data block to generate a decoded first data block.

Step 670: The second device converts the encoding format of the first data block to generate an image or video data stream.

The protocol receiving unit (as shown in FIG. 24 ) converts the encoding format of the first data block, generates an image or video data stream, and uploads the image or video data stream to the load unit (as shown in FIG. 24 ).

It should be noted that: Steps 616 to 646 in FIG. 25 can be replaced with: the encoding scheme using the FEC algorithm and the CRC algorithm; or the encoding scheme using the FEC algorithm and the ECC algorithm. Steps 654 to 666 in FIG. 25 can be replaced with: a scheme of performing verification by CRC algorithm and ECC algorithm; or, a scheme of performing verification by CRC algorithm; or, a scheme of performing verification by ECC algorithm.

In the technical solutions of the embodiments of the present application, the packet loss rate is obtained by detecting the transmission channel environment, and when the packet loss rate is relatively large, a combination of the FEC algorithm, the CRC algorithm and the ECC algorithm is selected to detect and correct the transmission data in the data transmission process. Error processing realizes error detection and correction of multi-bit error data, thereby improving the reliability of data transmission; when the packet loss rate is small, the FEC algorithm is selected to perform error detection and correction processing on the transmission data during data transmission, avoiding detection and correction. The data redundancy is relatively large during error processing, thereby improving the data transmission efficiency. Using the data transmission method of this embodiment improves data transmission efficiency on the basis of ensuring data transmission reliability.

An embodiment of the present application further provides a first device, where the first device may be a terminal device or a circuit device built in the terminal device. The device may be used to perform the functions/steps in the above method embodiments. The first device is a host, and the host can use an electronic device as shown in Figure 27 below.

The embodiment of the present application further provides a second device, where the second device may be a terminal device or a circuit device built in the terminal device. The device may be used to perform the functions/steps in the above method embodiments. The second device is a host, and the host can use an electronic device as shown in Figure 27 below.

FIG. 27 is a schematic structural diagram of an electronic device according to an embodiment of the present application. As shown in FIG. 27 , the electronic device 900 includes a processor 910 and a transceiver 920 . Optionally, the electronic device 900 may further include a memory 930 . Among them, the processor 910, the transceiver 920 and the memory 930 can communicate with each other through an internal connection path to transmit control and/or data signals. Invoke and run the computer program.

Optionally, the electronic device 900 may further include an antenna 940 for transmitting the wireless signal output by the transceiver 920.

The above-mentioned processor 910 and the memory 930 can be combined into a processing device, and more commonly, they are independent components, and the processor 910 is used to execute the program codes stored in the memory 930 to realize the above-mentioned functions. During specific implementation, the memory 930 may also be integrated in the processor 910 , or be independent of the processor 910 .

In addition, in order to make the functions of the electronic device 900 more complete, the electronic device 900 may further include one or more of an input unit 960, a display unit 970, an audio circuit 980, a camera 990, a sensor 901, etc., the audio The circuit may also include a speaker 982, a microphone 984, and the like. Wherein, the display unit 970 may include a display screen

Optionally, the above electronic device 900 may further include a power supply 950 for providing power to various devices or circuits in the terminal device.

It should be understood that the electronic device 900 shown in FIG. 27 can implement each process of the method embodiment shown in FIG. 20 , FIG. 23 or FIG. 25 . The operations and/or functions of each unit in the electronic device 900 are respectively to implement the corresponding processes in the foregoing method embodiments. For details, reference may be made to the descriptions in the foregoing method embodiments, and to avoid repetition, the detailed descriptions are appropriately omitted here.

It should be understood that the processor 910 in the electronic device 900 shown in FIG. 27 may be a system on a chip (SOC), and the processor 910 may include a central processing unit (CPU), and may further Including other types of processors, the CPU may be referred to as the main CPU. Each part of the processor cooperates to implement the previous method flow, and each part of the processor can selectively execute a part of the software driver.

In a word, each part of the processors or processing units inside the processor 910 can cooperate to implement the previous method process, and the corresponding software programs of each part of the processors or processing units can be stored in the memory 930 .

The present application also provides a computer-readable storage medium, where instructions are stored in the computer-readable storage medium, and when the instructions are executed on a computer, the computer executes the data shown in FIG. 20 , FIG. 23 or FIG. 25 The various steps in the transfer method.

The present application also provides a computer program product containing instructions, when the computer program product is run on a computer or any one of at least one processor, causing the computer to perform data transmission as shown in FIG. 20 , FIG. 23 or FIG. 25 steps in the method.

The present application also provides a chip including a processor. The processor is used to read and run the computer program stored in the memory, so as to execute the corresponding operations and/or processes performed by the data transmission method provided in this application.

Optionally, the chip further includes a memory, the memory and the processor are connected to the memory through a circuit or a wire, and the processor is used for reading and executing the computer program in the memory. Further optionally, the chip further includes a communication interface, and the processor is connected to the communication interface. The communication interface is used to receive data and/or information to be processed, and the processor acquires the data and/or information from the communication interface and processes the data and/or information. The communication interface may be an input-output interface.

In the above embodiments, the involved processor 910 may include, for example, a central processing unit (CPU), a microprocessor, a microcontroller or a digital signal processor, and may also include a GPU, an NPU, and an ISP. Necessary hardware accelerators or logic processing hardware circuits may also be included, such as application-specific integrated circuits (ASICs), or one or more integrated circuits used to control the execution of the programs of the technical solution of the present application. In addition, the processor may have the functionality to operate one or more software programs, which may be stored in the memory.

The memory can be read-only memory (ROM), other types of static storage devices that can store static information and instructions, random access memory (RAM), or other types of storage devices that can store information and instructions The dynamic storage device can also be electrically erasable programmable read-only memory (electrically erasable programmable read-only memory, EEPROM), compact disc read-only memory (CD-ROM) or other optical disk storage, optical disk storage ( including compact discs, laser discs, compact discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media, or other magnetic storage devices, or may also be capable of carrying or storing desired program code in the form of instructions or data structures and capable of Any other medium accessed by a computer, etc.

In the embodiments of the present application, "at least one" refers to one or more, and "multiple" refers to two or more. "And/or", which describes the association relationship of the associated objects, means that there can be three kinds of relationships, for example, A and/or B, which can indicate the existence of A alone, the existence of A and B at the same time, and the existence of B alone. where A and B can be singular or plural. The character "/" generally indicates that the associated objects are an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c may be single or multiple.

Those of ordinary skill in the art can realize that the units and algorithm steps described in the embodiments disclosed herein can be implemented by a combination of electronic hardware, computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each particular application, but such implementations should not be considered beyond the scope of this application.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described systems, devices and units may refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

In the several embodiments provided in this application, if any function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be embodied in the form of a software product in essence, or the part that contributes to the prior art or the part of the technical solution, and the computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk and other media that can store program codes .

The above are only specific embodiments of the present application. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be covered by the protection scope of the present application. The protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A data transmission method, characterized in that, applied to a first device, the method comprising:

If the environmental parameters of the transmission channel meet the conditions for enabling the first algorithm, encode the acquired transmission data through the first error detection and correction algorithm, generate first encoded data, and send the first encoded data to the second device;

If the environmental parameters of the transmission channel meet the conditions for enabling the second algorithm, the acquired transmission data is encoded by the second error detection and correction algorithm, second encoded data is generated, and the second encoded data is sent to the second device. The second error detection and correction algorithm is different from the first error detection and correction algorithm.
The method of claim 1, further comprising:

Get the environment parameters of the transport channel.
The method according to claim 2, wherein the environmental parameter of the transmission channel comprises a bit error rate; the acquiring the environmental parameter of the transmission channel comprises: sequentially sending the first sequence and the second sequence to the second device , for the second device to count the number of bits of the correct second sequence received, and the first sequence is used to implement state machine equalization training; to receive the number of bits of the correct second sequence sent by the second device ; Calculate the bit error rate according to the number of bits of the correct second sequence sent by the second device and the total number of bits of the second sequence sent; or,

The transmission channel environment parameter includes a system transmission rate; the acquiring the transmission channel environment parameter includes: reading the system transmission rate from a speed cut state register.
The method according to claim 1 or 3, characterized in that, if the environmental parameters of the transmission channel meet the conditions for enabling the first algorithm, the method further comprises: collecting raw data; converting the raw data into an encoding format, generating said transmission data; or,

If the environmental parameters of the transmission channel meet the conditions for enabling the second algorithm, the method further includes: collecting original data; converting the encoding format of the original data to generate the transmission data.
The method according to claim 2, wherein the environmental parameter of the transmission channel comprises a packet loss rate; the obtaining the environmental parameter of the transmission channel comprises:

Send a test data packet to the second device, and record the number of the sent test data packet;

Receive the number of correct test data packets received according to statistics returned by the second device;

Calculate the packet loss rate according to the number of correct test packets and the number of sent test packets.
The method according to claim 1 or 5, wherein before encoding the acquired transmission data by the first error detection and correction algorithm, the method further comprises: collecting original data; converting the encoding format of the original data, generating the transmission data; or, before encoding the acquired transmission data by using the second error detection and correction algorithm, the method further includes: collecting original data; converting the encoding format of the original data to generate the transmission data.
The method according to any one of claims 1-6, wherein the transmission channel environment parameter comprises one of a bit error rate, a system transmission rate and the packet loss rate or any combination thereof;

The transmission channel environment parameter meeting the first algorithm enabling condition includes: the bit error rate is greater than or equal to a first threshold, the system transmission rate is greater than or equal to a second threshold, and the packet loss rate is greater than or equal to a third threshold one or any combination thereof;

The transmission channel environment parameter meeting the condition for enabling the second algorithm includes: the bit error rate is less than the first threshold, the system transmission rate is less than the second threshold, and the packet loss rate is less than one of the third threshold or any combination thereof .
The method according to any one of claims 1-7, wherein the first error detection and correction algorithm includes at least two error detection and correction algorithms, and the second error detection and correction algorithm includes at least one error detection and correction algorithm; or,

The number of error detection and correction algorithms in the first error detection and correction algorithm is greater than the number of error detection and correction algorithms in the second error detection and correction algorithm.
The method according to claim 1 or 8, wherein the first error detection and correction algorithm comprises a forward error correction (FEC) algorithm, a clean core cyclic redundancy check (CRC) algorithm, and a packet header error correction code (ECC) algorithm; or The first error detection and correction algorithm includes the FEC algorithm and the CRC algorithm; or the first error detection and correction algorithm includes the FEC algorithm and the ECC algorithm; or,

The second error detection and correction algorithm includes an FEC algorithm; or the second error detection and correction algorithm includes a CRC algorithm; or the second error detection and correction algorithm includes an ECC algorithm; or the second error detection and correction algorithm includes a CRC algorithm and ECC algorithm.
The method according to any one of claims 1-9, wherein the first encoded data includes an indication field, and the indication field of the first encoded data is used to indicate that the environment parameter is enabled in accordance with the first algorithm conditions; and/or,

The second encoded data includes an indication field, and the indication field of the second encoded data is used to indicate that the environment parameter complies with the condition for enabling the second algorithm.
The method according to any one of claims 1-10, wherein the first device is a camera module, and the second device is a motherboard; or

The first device is a camera module, and the second device is a host; or

The first device is a motherboard, and the second device is a display screen; or

The first device is a host, and the second device is a display screen.
A data transmission method, characterized in that, applied to a second device, the method comprising:

received encoded data;

If it is determined that the conditions for enabling the first algorithm are met, the encoded data is checked by the first error detection and correction algorithm to generate transmission data;

If it is determined that the conditions for enabling the second algorithm are met, the encoded data is verified by the second error detection and correction algorithm to generate transmission data.
The method of claim 12, wherein the method further comprises:

receiving a first sequence and a second sequence sequentially sent by the first device, where the first sequence is used to implement state machine equalization training;

Calculate the bit error rate according to the number of bits of the correct second sequence received and the total number of bits of the second sequence sent;

If the bit error rate complies with the enabling condition of the first algorithm, a first bit error rate status is sent to the first device, where the first bit error rate status is used to indicate that the bit error rate conforms to the first algorithm open condition;

If the bit error rate complies with the enabling condition of the second algorithm, send a second bit error rate status to the first device, where the second bit error rate status is used to indicate that the bit error rate conforms to the second algorithm Turn on condition.
The method of claim 14, wherein the method further comprises:

receiving a test data packet sent by the first device;

Calculate the packet loss rate according to the number of correct test packets received and the number of test packets sent;

If the packet loss rate complies with the enabling condition of the first algorithm, a first packet loss rate status is sent to the first device, where the first packet loss rate status is used to indicate that the packet loss rate complies with the first algorithm open condition;

If the packet loss rate complies with the enabling condition of the second algorithm, a second packet loss rate status is sent to the first device, where the first packet loss rate status is used to indicate that the packet loss rate complies with the second algorithm Turn on condition.
The method according to claim 14, wherein the first error detection and correction algorithm includes at least two error detection and correction algorithms, the second error detection and correction algorithm includes at least one error detection and correction algorithm, and the first error detection and correction algorithm includes at least one error detection and correction algorithm. The number of error detection and correction algorithms in the error detection algorithm is greater than the number of error detection and correction algorithms in the second error detection and correction algorithm.
The method according to claim 14 or 17, wherein the first error detection and correction algorithm comprises an FEC algorithm, a CRC algorithm and an ECC algorithm; or

The first error detection and correction algorithm includes an FEC algorithm and a CRC algorithm; or

The first error detection and correction algorithm includes an FEC algorithm and an ECC algorithm; or

The second error detection and correction algorithm includes an FEC algorithm; or

The second error detection and correction algorithm includes a CRC algorithm; or

The second error detection and correction algorithm includes an ECC algorithm; or

The second error detection and correction algorithm includes a CRC algorithm and an ECC algorithm.
The method according to claim 14, wherein the determining that the condition for enabling the first algorithm is met comprises: determining that the encoded data includes an indication field; the determining that the condition for enabling the second algorithm is met comprises: determining out that the encoded data does not include an indication field; or,

The determining that the condition for enabling the first algorithm is met includes: determining that the encoded data does not include an indication field; the determining that the condition for enabling the second algorithm is met includes: determining that the second encoding data includes an indication field; or ,

The determining that the condition for enabling the first algorithm is met includes: determining that the indication field in the first encoded data is the first value; the determining that the condition for enabling the second algorithm is met includes: determining that the second The indication field in the encoded data is the second value.
A first device, characterized in that it includes:

one or more processors; a memory; and one or more computer programs, wherein the one or more computer programs are stored in the memory, the one or more computer programs including instructions, when the instructions are When the device executes, the device is caused to execute the data transmission method described in any one of claims 1 to 11.
A second device, comprising:

one or more processors; a memory; and one or more computer programs, wherein the one or more computer programs are stored in the memory, the one or more computer programs including instructions, when the instructions are When the device executes, the device is caused to execute the data transmission method described in any one of claims 12 to 17 .
A data transmission system, comprising: a first device and a second device, wherein the first device and the second device are communicatively connected through a transmission channel;

The first device is configured to encode the acquired transmission data through a first error detection and correction algorithm if the environmental parameters of the transmission channel meet the conditions for enabling the first algorithm, generate first encoded data, and convert the first encoded data to the first device. Send to the second device; if the environmental parameters of the transmission channel meet the conditions for enabling the second algorithm, encode the acquired transmission data through the second error detection and correction algorithm, generate second encoded data, and send the second encoded data to a second device, wherein the second error detection and correction algorithm is different from the first error detection and correction algorithm;

The second device is configured to, if receiving the first encoded data sent by the first device, verify the first encoded data through a first error detection and correction algorithm, and generate transmission data; if receiving the first encoded data sent by the first device The second encoded data is checked by a second error detection and correction algorithm to generate transmission data.
The system of claim 20, wherein the first device is a camera module, and the second device is a motherboard; or

The first device is a camera module, and the second device is a host; or

The first device is a motherboard, and the second device is a display screen; or

The first device is a host, and the second device is a display screen.
A computer-readable storage medium, characterized in that the computer-readable storage medium comprises a stored program, wherein when the program is run, a device where the computer-readable storage medium is located is controlled to execute any one of claims 1 to 11 One of the data transmission methods, or, when the program is running, the device where the computer-readable storage medium is located is controlled to execute the data transmission method according to any one of claims 12 to 17.
A computer program product comprising instructions, characterized in that, when the computer program product is run on a computer or any one of at least one processor, the computer is made to perform the execution of any one of claims 1 to 11. or, causing the computer to execute the data transmission method according to any one of claims 12 to 17.