CN204669384U

CN204669384U - For the bus interface of multichannel MIL-STD-1553B

Info

Publication number: CN204669384U
Application number: CN201520414970.6U
Authority: CN
Inventors: 王小宁; 呼曦; 魏明昊; 张鹏; 杨帅妮
Original assignee: Shaanxi Baocheng Aviation Instrument Co Ltd
Current assignee: Shaanxi Baocheng Aviation Instrument Co Ltd
Priority date: 2015-06-16
Filing date: 2015-06-16
Publication date: 2015-09-23
Anticipated expiration: 2025-06-16

Abstract

A kind of bus interface for multichannel MIL-STD-1553B is provided, comprises multichannel MIL-STD-1553B bus, isolation drive combinational circuit and FPGA; Multichannel MIL-STD-1553B bus is electrically connected with FPGA by many group isolation drive combinational circuits, and FPGA is electrically connected with outer CPU; Isolation drive combinational circuit comprises buffer circuit and 1553B drive circuit, FPGA adopts the combinational circuit of many group buffer circuits and 1553B drive circuit receive and send the multichannel data of multichannel MIL-STD-1553B bus, multichannel data carries out decoding/encoding, sequencing control, protocol processes, data buffer storage and data access by FPGA, and FPGA carries out exchanges data by one group of communication interface and outer CPU.The utility model is lightweight, and volume is little, and cost is low, and data processing performance is high, safe and reliable.

Description

For the bus interface of multichannel MIL-STD-1553B

Technical field

The utility model belongs to bus interface technology field, is specifically related to a kind of bus interface for multichannel MIL-STD-1553B.

Background technology

Multichannel MIL-STD-1553B bus is the military standard serial communication bus of U.S.'s definition, there is higher reliability and real-time, be widely used in the data network communication system in the field such as Aeronautics and Astronautics, military affairs, its principal character is: transmission speed 1Mbit/s, word length 20bit, data effective length 16bit, amount of information maximum length 32 words.MIL-STD-1553B adopts typical two redundant fault fault-tolerant way, and communication message is modulated into Manchester code and transmits in bus.In actual applications, the MIL-STD-1553B bus interface of each equipment adopts protocol chip both domestic and external to realize mostly, the chip of current this agreement of support has the HI-61XX series of HOLT company, BU-6517X, BU-615XX series etc. of DDC company, but this protocol chip is expensive, and configuration is complicated, procurement cycle is long, particularly when with multichannel MIL-STD-1553B bus transfer/monitoring, need multiple protocol chip, cost is high, volume is large, data-handling efficiency is low, data buffer storage is little.Therefore be necessary to propose to improve.

Utility model content

The technical problem that the utility model solves: a kind of bus interface for multichannel MIL-STD-1553B is provided, the many groups combinational circuit be made up of buffer circuit and 1553B drive circuit is adopted to receive and send the multichannel data of multichannel MIL-STD-1553B bus, and by FPGA, decoding/encoding is carried out to multichannel data, sequencing control, protocol processes, data buffer storage and data access, FPGA carries out exchanges data by one group of communication interface and outer CPU again, solve the volume existed in prior art large, the problem such as the high and data buffer storage of cost is little, improve efficiency and the reliability of data processing, save hardware resource.

The technical solution adopted in the utility model: for the bus interface of multichannel MIL-STD-1553B, comprises multichannel MIL-STD-1553B bus, isolation drive combinational circuit and FPGA;

Wherein, described multichannel MIL-STD-1553B bus is electrically connected with FPGA by many group isolation drive combinational circuits, and described FPGA is electrically connected with outer CPU;

Described isolation drive combinational circuit comprises buffer circuit and 1553B drive circuit, described FPGA adopts the combinational circuit of many group buffer circuits and 1553B drive circuit receive and send the multichannel data of multichannel MIL-STD-1553B bus, described multichannel data carries out decoding/encoding, sequencing control, protocol processes, data buffer storage and data access by FPGA, and described FPGA carries out exchanges data by one group of communication interface and outer CPU.

Further, the described combinational circuit often organizing buffer circuit and 1553B drive circuit is made up of 2 isolating transformers, 1 transceiver and protective resistance.

Further, the in-line coding of described FPGA comprises two redundancy Manchester II encoding and decoding and serioparallel exchange module, bus transfer logic module, terminal protocol and message processing module, internal memory and controller module, terminal address generation and correction verification module.

The utility model advantage compared with prior art:

1, the combinational circuit often organizing buffer circuit and 1553B drive circuit is made up of 2 isolating transformers, 1 transceiver and protective resistance, realizes two redundancy designs of hardware, makes data processing safe and reliable;

2, the object adopting 2 isolating transformers to achieve interface circuit and data/address bus to isolate, and level translation is carried out to data, make it to mate with the operating voltage of transceiver;

3, achieved the mutual conversion of MIL-STD-1553B differential signal and Transistor-Transistor Logic level by transceiver, complete and FPGA exchanges data;

4, protective resistance is for the protection of isolating transformer and transceiver;

5, the utility model is lightweight, and volume is little, and cost is low, and data processing performance is high, safe and reliable.

Accompanying drawing explanation

Fig. 1 is theory diagram of the present utility model;

Fig. 2 is circuit diagram of the present utility model.

Embodiment

Below in conjunction with accompanying drawing 1-2, embodiment of the present utility model is described.

For the bus interface of multichannel MIL-STD-1553B, comprise multichannel MIL-STD-1553B bus, isolation drive combinational circuit and FPGA; As shown in Figure 1, described multichannel MIL-STD-1553B bus is electrically connected with FPGA by many group isolation drive combinational circuits, and described FPGA is electrically connected with outer CPU; Described isolation drive combinational circuit comprises buffer circuit and 1553B drive circuit, described FPGA adopts the combinational circuit of many group buffer circuits and 1553B drive circuit receive and send the multichannel data of multichannel MIL-STD-1553B bus, described multichannel data carries out decoding/encoding, sequencing control, protocol processes, data buffer storage and data access by FPGA, and described FPGA carries out exchanges data by one group of communication interface and outer CPU.Concrete, the described combinational circuit often organizing buffer circuit and 1553B drive circuit is made up of 2 isolating transformers, 1 transceiver and protective resistance, and this structure realizes two redundancy designs of hardware, makes data processing safe and reliable; Wherein (as shown in Figure 2), 2 isolating transformers preferably adopt HOLT company PM-DB2725 chip, for realizing the object that interface circuit and data/address bus are isolated, level translation is carried out to data, make it to mate with the operating voltage of transceiver, transceiver preferably adopts the HI-1570PSI chip of HOLT company, for realizing the mutual conversion of MIL-STD-1553B differential signal and Transistor-Transistor Logic level, completes and FPGA exchanges data; Protective resistance R1, R2, R3, R4 are used for protective separation transformer and transceiver.

The chip of FPGA preferably adopts the EP2C20Q240C6 chip of altera corp, the Y1 in Fig. 2 to be active crystal oscillator, for providing clock for FPGA.When receiving data, the signal that FPGA receives remains Manchester II type code, therefore need through decoding, complete the comprehensive, synchronous of data word simultaneously, data and Manchester code Error detection, odd even detects and position/word count etc., only to after the correct data word serioparallel exchange of reception stored in internal memory, again to the protocol processes that it is correlated with, be sent to outer CPU; When sending data, the data temporary storage of the outer CPU that terminal receives by FPGA is in internal memory, by related protocol decoding, determine that namely data attribute transmits data/order, send data by carrying out Manchester's code after parallel-serial conversion and being sent in the bus of MIL-STD-1553B after modulation /demodulation.Concrete, FPGA hardware description language adopts Verilog, development environment adopts QuartusII, for realizing MIL-STD-1553B bus interface function, the in-line coding of described FPGA comprises two redundancy Manchester II encoding and decoding and serioparallel exchange module, bus transfer logic module, internal memory and controller module, terminal protocol and message processing module, terminal address generation and correction verification module, wherein, the II encoding and decoding of two redundancy Manchester and serioparallel exchange module achieve the Code And Decode of Manchester code, and communicate with bus transfer logic module; Bus transfer logic module is carried out comprehensively MIL-STD-1553B bus, store and process; Internal memory and controller module are used as system register and carry out the data storage area of exchanges data with microprocessor, to respond the register access and data access that other each module may exist; Terminal protocol and message processing module are resolved the order that receives and are notified that bus transfer logic module makes corresponding response; Terminal address generation and correction verification module, by microprocessor setting terminal address, are stored in the terminal address register of internal memory after producing corresponding address odd parity bit, and init state word.

The utility model efficiently solves that the volume existed in prior art is large, cost is high and the problem such as data buffer storage is little, improves efficiency and the reliability of data processing, has saved hardware resource.

Above-described embodiment, just preferred embodiment of the present utility model, is not used for limiting the utility model practical range, therefore all equivalence changes done with content described in the utility model claim, all should be included within the utility model right.

Claims

1. for the bus interface of multichannel MIL-STD-1553B, it is characterized in that: comprise multichannel MIL-STD-1553B bus, isolation drive combinational circuit and FPGA;

Described multichannel MIL-STD-1553B bus is electrically connected with FPGA by many group isolation drive combinational circuits, and described FPGA is electrically connected with outer CPU;

Described isolation drive combinational circuit comprises buffer circuit and 1553B drive circuit, described FPGA adopts the combinational circuit of many group buffer circuits and 1553B drive circuit, receive and send the multichannel data of multichannel MIL-STD-1553B bus, described multichannel data carries out decoding/encoding, sequencing control, protocol processes, data buffer storage and data access by FPGA, and described FPGA carries out exchanges data by one group of communication interface and outer CPU.

2. the bus interface for multichannel MIL-STD-1553B according to claim 1, is characterized in that: the described combinational circuit often organizing buffer circuit and 1553B drive circuit is made up of 2 isolating transformers, 1 transceiver and protective resistance.

3. the bus interface for multichannel MIL-STD-1553B according to claim 1, is characterized in that: the in-line coding of described FPGA comprises two redundancy Manchester II encoding and decoding and serioparallel exchange module, bus transfer logic module, terminal protocol and message processing module, internal memory and controller module, terminal address produce and correction verification module.