CN101431339A - RS encoding apparatus and encoding method based on FPGA - Google Patents

Abstract

A RS encoding device based on FPGA and an encoding method belong to the technical field of numerical coding. The encoding device comprises a pc machine and a development board, and is characterized in that a parallel port of the pc machine is connected with the development board by a JATG connecting line, and the development board is equipped with an FPGA chip which includes a Galois Field (GF) adder unit, a GF multiplier unit, a register and a selector. The RS encoding device and the encoding method can simplify a hardware circuit to reduce the spending of the system and save the cost, thus realizing the RS encoding device and the encoding method which have high speed and low complexity.

Description

RS code device and coding method based on FPGA

One, technical field

The present invention relates to a kind of RS code device and coding method, belong to the digital coding field based on FPGA.

Two, background technology

Reed-solomn (Reed-Solomon) sign indicating number is the very strong error correction energy sign indicating number of a class, belongs to a kind of of BCH code, also is a kind of typical Algorithms of Algebraic Geometric Codes.It is used the MS polynomial construction by Reed (Reed) and Suo Luomeng (Solomn) in nineteen sixty and comes out, and is the good linear error correction sign indicating number of a class.The RS coding has very strong application space, is widely used in communication system, Digital Television and the computer memory system.

Traditional RS encryption algorithm complexity, the hardware resource that takies is many, the cost height.In the RS coding, the core devices of using is a constant coefficient Jia Lehua territory multiplier, common implementation method has Berlekamp and Massey-Omura bit serial multiplier, Mastrovito bit parallel multiplier, hardware configuration was simpler when particularly Berlekamp bit serial multiplier was applied to the RS sign indicating number, but when data throughput is higher, because Berlekamp bit serial multiplier relates to two bases, the computing of bit serial is difficult to reach designing requirement.

Three, summary of the invention

Be defective and the deficiency that overcomes prior art, the invention provides a kind of RS code device and coding method based on FPGA.

A kind of RS code device based on FPGA comprises a pc machine, and a development board is characterized in that the parallel port of pc machine is connected with development board by a JATG connecting line, and device has fpga chip on the development board.

Comprise galois field adder unit, Galois field multiplying unit unit, register and selector after the described fpga chip configuration.

FPGA is a field programmable gate array.

A kind of RS code device of above-mentioned FPGA that utilizes carries out Methods for Coding, and step is as follows:

(1) all register D after detecting packet synchronization signal ₀D ₁D ₁₅Zero clearing;

(2) for preceding 188 bytes of each frame, K2 beats on b, and K1 closure meanwhile shifts out 188 inputs data, Shu Ru each data and D simultaneously in proper order at the rising edge of data clock ₁₅As the multiplier of 16 multipliers, for improving the throughput of data, we adopt pipelining to carry out multiplying at the rising edge of data behind the register XOR, and trailing edge carries out XOR;

After (3) 188 bytes were passed through, K2 beat on a, and K1 disconnects simultaneously, and feedback loop zero setting, passes through D in ensuing 16 clocks ₁₅Order shifts out 16 check byte, thereby finishes the coding to a bag, when detecting the packet synchronization signal of next bag, carries out same operation again.

Coding staff ratio juris of the present invention is:

1.RS the formation of coding

The RS sign indicating number is the corresponding to BCH code of the rhizosphere of symbol territory and code polynomial, to (t) implication of the n in the RS sign indicating number is not a binary bits and be symbolic number for n, k.

The sign indicating number generator polynomial

According to the regulation of national standard, after the energy dissipation randomization, adopt the RS coding of T=8, brachymemma, and it is added to each randomized MPEG-2 transmits and wrap.Promptly each is transmitted Bao Eryan, can correct 8 error bytes.This process transmits in the bag at MPEG-2 has increased by 16 check byte, and code word is (204,188).The RS coding equally also acts on the bag sync byte, no matter be (being 47hex) or (B8hex) of paraphase of not paraphase.

The sign indicating number generator polynomial is:

G (x)=(x+ λ ⁰) (x+ λ ¹) (x+ λ ²) ... (x+ λ ¹⁵) λ=02H here.

The territory generator polynomial is: p (x)=x ⁸+ x ⁴+ x ³+ x ²+ 1, the implementation method of the RS sign indicating number of brachymemma herein is before (255,239) code device input input information byte, adds 51 bytes, and is set to complete zero.Behind the coding, again these null bytes are abandoned.

3. based on the finite field bit parallel multiplier of weak reciproccal basis

By the regulation of standard, the sign indicating number generator polynomial of cable digital TV broadcast channel coding is:

g(x)＝(x+λ ⁰)(x+λ ¹)(x+λ ²)…(x+λ ¹⁵)

G (x)=x ¹⁶+ λ ¹²¹x ¹⁵+ λ ¹⁰⁶x ¹⁴+ λ ¹¹⁰x ¹³+ λ ¹¹³x ¹²+ λ ¹⁰⁷x ¹¹+ λ ¹⁶⁷x ¹⁰+ λ ⁸³x ⁹+ λ ¹¹x ⁸+ λ ¹⁰⁰x ⁷+ λ ²⁰¹x ⁶+ λ ¹⁵⁸x ⁵+ λ ¹⁸¹x ⁴+ λ ¹⁹⁵x ³+ λ ²⁰⁸x ²+ λ ²⁴¹X+ λ ¹³⁶λ=02H is brought into, use the galois field multiplication rule, calculating can get:

g(x)＝x ¹⁶+59x ¹⁵+13x ¹⁴+104x ¹³+189x ¹²+68x ¹¹+209x ¹⁰+30x ⁹+8x ⁸+163x ⁷+65x ⁶+41x ⁵+229x ⁴+98x ³+50x ²+36x+59

Is weak reciproccal basis coefficient with the coefficient of following formula according to aforementioned theoretical conversion, and this weak reciproccal basis coefficient can be described with 16 system numbers of 4 of 15 bit wides, is described below with VHDL language:

a1.CONST＝15’h0ce7，

a2.CONST＝15’h7f21，

a3.CONST＝15’h7062，

a4.CONST＝15’h2b32，

a5.CONST＝15’h5fbc，

a6.CONST＝15’h72a5，

a7.CONST＝15’h0315，

a8.CONST＝15’h0baf，

a9.CONST＝15’h3880，

a10.CONST＝15’h37c3，

a11.CONST＝15’h3cdd，

a12.CONST＝15’h3611，

a13.CONST＝15’h3c6c，

a14.CONST＝15’h71b0，

a15.CONST＝15’h0d84，

a16.CONST＝15’h0ce7，

Can see that a16.CONST and a1.CONST are consistent, only need a multiplexing multiplier just passable, so this design need be used 15 Galois field multiplying units.

Emulation and testing authentication

Simulation result

On the software platform of the ISE9.2 of Xilinx company, adopt Hardware Description Language VHDL to finish design, carry out emulation with ModelSim SE6.2i.The input requirement of input analog D VB-C standard, 204 bytes of every frame, preceding 188 bytes are from 1 to 188, back 16 bytes are any.16 check byte of output contrast with the software emulation result, and the result is entirely true.

The hardware testing checking

The present invention adopts the XC3S500E of Xilinx company chip, by a kind of new constant coefficient Jia Lehua territory multiplier algorithm, finishes the design of RS (204,188) coding, has reduced the expense of system.The code device work clock reaches 200Mhz.ChipScope Pro 9.2 logic analyzers are adopted in checking on the sheet.Its basic principle is to utilize untapped BlockRam among the FPGA, and the trigger condition of setting according to the user is saved in signal among these BlockRam in real time, passes to computer by JATG then, demonstrates real-time waveform at last on computer screen.Triggering mode selects the rising edge of clk_gex (the dominant frequency 200Mhz of system) clock to trigger, and 2048 points of sampling are in full accord with simulation result, thereby has further verified the correctness of system design.

Advantage of the present invention and beneficial effect are as follows:

The present invention adopts the method for bit parallel multiplier to design.This scheme is used for the optimum reciproccal basis of RS code Design by calculating, and adopt this optimum reciproccal basis to constitute bit parallel finite field element multiplier, the RS code device complexity that is made of such multiplier is low, and can reach the higher system data throughput.

RS code device of the present invention and coding method can be simplified hardware circuit, thereby reduce the expense of system, save cost, to realize the RS code device and the coding method of high speed, low complex degree.

Four, description of drawings

Fig. 1 is the schematic diagram of code device of the present invention.

Wherein: 1, pc machine, 2, the JATG connecting line, 3, development board, 4, the Fpga chip.

Fig. 2 is the chip schematic diagram of code device of the present invention, and wherein g0-g15 is the galois field adder unit, and D1-D16 is a register, and K1, K2 are selector.

Five, embodiment

Following examples are to further specify of the present invention, but are not limited thereto.

Embodiment 1:

A kind of RS code device based on FPGA comprises 1, one development board 3 of a pc machine, it is characterized in that the parallel port of pc machine 1 is connected with development board 3 by a JATG connecting line 2, and device has fpga chip 4 on the development board 3.

Described configuration back fpga chip 4 comprises galois field adder unit, Galois field multiplying unit unit, register and selector.

Embodiment 2:

A kind of RS code device of above-mentioned FPGA that utilizes carries out Methods for Coding, and step is as follows:

(1) all register D after detecting packet synchronization signal ₀D ₁D ₁₅Zero clearing;

(2) for preceding 188 bytes of each frame, K2 beats on b, and K1 closure meanwhile shifts out 188 inputs data, Shu Ru each data and D simultaneously in proper order at the rising edge of data clock ₁₅As the multiplier of 16 multipliers, for improving the throughput of data, we adopt pipelining to carry out multiplying at the rising edge of data behind the register XOR, and trailing edge carries out XOR;

After (3) 188 bytes were passed through, K2 beat on a, and K1 disconnects simultaneously, and feedback loop zero setting, passes through D in ensuing 16 clocks ₁₅Order shifts out 16 check byte, thereby finishes the coding to a bag, when detecting the packet synchronization signal of next bag, carries out same operation again.

Claims (3)

1, a kind of RS code device based on FPGA comprises 1, one development board 3 of a pc machine, it is characterized in that the parallel port of pc machine 1 is connected with development board 3 by a JATG connecting line 2, and device has fpga chip 4 on the development board 3.

2, a kind of RS code device based on FPGA as claimed in claim 1 is characterized in that described fpga chip

Comprise galois field adder unit, Galois field multiplying unit unit, register and selector.

3, a kind of RS code device of the described FPGA of claim 1 that utilizes carries out Methods for Coding, and step is as follows:

(1) all register D after detecting packet synchronization signal ₀D ₁D ₁₅Zero clearing;

(2) for preceding 188 bytes of each frame, K2 beats on b, and K1 closure meanwhile shifts out 188 inputs data, Shu Ru each data and D simultaneously in proper order at the rising edge of data clock ₁₅As the multiplier of 16 multipliers, for improving the throughput of data, we adopt pipelining to carry out multiplying at the rising edge of data behind the register XOR, and trailing edge carries out XOR;

After (3) 188 bytes were passed through, K2 beat on a, and K1 disconnects simultaneously, and feedback loop zero setting, passes through D in ensuing 16 clocks ₁₅Order shifts out 16 check byte, thereby finishes the coding to a bag, when detecting the packet synchronization signal of next bag, carries out same operation again.

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