CN204347817U - The pseudorandom number generator of integrated CRC check circuit - Google Patents
The pseudorandom number generator of integrated CRC check circuit Download PDFInfo
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- CN204347817U CN204347817U CN201420550401.XU CN201420550401U CN204347817U CN 204347817 U CN204347817 U CN 204347817U CN 201420550401 U CN201420550401 U CN 201420550401U CN 204347817 U CN204347817 U CN 204347817U
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Abstract
The utility model discloses a kind of pseudorandom number generator of integrated CRC check circuit, belong to pseudorandom number generator technical field, the pseudorandom number generator of the integrated CRC check circuit that the utility model provides is by the basis of CRC check circuit, increase interference module, state temporary storage module, mapping circuit and sampling circuit, thus ensure that the pseudorandom number generator of this integrated CRC check circuit can export pseudo random number comparatively reliably, for the circuit exploitation of pseudo random number provides the foundation, the normal execution that CRC verifies can be made again, do not affect its original function, meanwhile, the hardware resource of increase is considerably less, thus on the basis of minimum cost, has accomplished function maximization, and then improves the product benefit of pseudorandom number generator of this integrated CRC check circuit.
Description
Technical field
The utility model relates to a kind of pseudorandom number generator, particularly relates to a kind of pseudorandom number generator of integrated CRC check circuit.
Background technology
CRC identifying code and cyclic redundancy check (CRC) code, be extensively present in data communication field, and its effect is for checking data.The essence that CRC identifying code produces is the polynomial division of mould 2, and the check code of generation is the remainder of division.The generation of its check code constantly can carry out subtraction and displacement to a generator polynomial by data.In actual applications, multiple choices mode has been chosen for generator polynomial.Specifically select which kind of polynomial expression, depend on the regulation of agreement.Such as, in USB3.0 communication protocol, just there are 3 kinds of CRC check codes, for the CRC-16 in packet header, for the CRC-5 of link control word, and for the CRC-32 of data division, this polynomial expression is respectively 100Bh, 00101b and 04C11DB7h.Such as 00101b, represents the coefficient that polynomial expression is every from high to low respectively, and corresponding polynomial expression is x
5+ x
2+ 1.
The subtraction of mould 2 is xor operation, can use circuit realiration very easily like this.In actual applications, serial or parallel implementation is had.Serial mode processes a bit of data at every turn, usually uses linear feedback shift register (Linear Feedback Shift Registers, LFSR).As shown in Figure 1, Fig. 1 is the electrical block diagram of CRC-5 shift register to CRC-5 shift-register circuit in USB3.0.USB 3.0 agreement defines the create-rule of CRC, and when verify calculation starts, register initial value is set as complete 1, and data calculate from low level, and is inverted high-low-position by after result negate, thus obtains terminal check code.
Pseudorandom number generator for generation of pseudo random number adopts LFSR to produce usually has macrocyclic random number.This LFSR comprises multiple series connection register and an XOR circuit, and wherein, the output data of predetermined register are fed back to first register by this XOR circuit.Owing to providing XOR circuit in feedback path, thus linear feedback shift register is made to produce the random number with longer cycle.
Produce in the encrypted circuit etc. of password using pseudo random number, if display pseudo-random number sequence or pseudorandom logic, the ciphertext that then can obtain from one reduces an original plaintext, thus it is extremely important to make effectively to produce uncertain random number sequence.
It can thus be appreciated that pseudorandom number generator of the prior art can not provide pseudo random number relatively reliably, thus is unfavorable for the circuit exploitation etc. of pseudorandom number generator.
Utility model content
For above-mentioned Problems existing, the utility model provides a kind of pseudorandom number generator of integrated CRC check circuit, to overcome the problem that pseudorandom number generator of the prior art can not provide pseudo random number comparatively reliably, thus both provided pseudo random number comparatively reliably, for the circuit exploitation of pseudorandom number generator provides the foundation, in turn ensure that the normal execution that CRC verifies, simultaneously, employing hardware resource is few, on the basis of minimum cost, accomplish function maximization, improve product benefit.
To achieve these goals, the technical scheme that the utility model is taked is:
A pseudorandom number generator for integrated CRC check circuit, wherein, comprising:
Load module, it is configured to input data to be verified;
CRC check circuit, it is connected to described load module and is configured to verify described data to be verified;
Interference module, it is configured to input nonlinearities data;
Mapping circuit, it is connected to described interference module and described CRC check circuit, and the state being configured to map described CRC check circuit then carries out XOR computing with described interfering data;
State temporary storage module, it is connected to described mapping circuit and described CRC check circuit, and is loaded into described CRC check circuit after being configured to obtain described XOR operation result;
Sampling circuit, it is connected to described mapping circuit and exports after being configured to extract described XOR operation result.
The pseudorandom number generator of above-mentioned integrated CRC check circuit, wherein, described CRC check circuit is linear feedback shift register.
The pseudorandom number generator of above-mentioned integrated CRC check circuit, wherein, described linear feedback shift register comprises multiple register and multiple logical operation door.
The pseudorandom number generator of above-mentioned integrated CRC check circuit, wherein, described logical operation door is exclusive or logic gate.
The pseudorandom number generator of above-mentioned integrated CRC check circuit, wherein, described mapping circuit is made up of one or more exclusive or logic gate.
The pseudorandom number generator of above-mentioned integrated CRC check circuit, wherein, described state temporary storage module is formed of registers.
The pseudorandom number generator of above-mentioned integrated CRC check circuit, wherein, described sampling circuit is a register.
The pseudorandom number generator of above-mentioned integrated CRC check circuit, wherein, the clock frequency of described mapping circuit is r times of the clock frequency of described sampling circuit, and r > 1.
Technique scheme tool has the following advantages or beneficial effect:
The pseudorandom number generator of a kind of integrated CRC check circuit that the utility model provides, by on the basis of CRC check circuit, increase interference module, state temporary storage module, mapping circuit and sampling circuit, thus ensure that the pseudorandom number generator of this integrated CRC check circuit can export pseudo random number comparatively reliably, for the circuit exploitation of pseudorandom number generator provides the foundation, the normal execution that CRC can be made again to verify, does not affect its original function; Meanwhile, the hardware resource of increase is considerably less, thus on the basis of minimum cost, has accomplished function maximization, and then improves the product benefit of pseudorandom number generator of this integrated CRC check circuit.
Accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, the utility model and feature, profile and advantage will become more apparent.Mark identical in whole accompanying drawing indicates identical part.Deliberately proportionally do not draw accompanying drawing, focus on purport of the present utility model is shown.
Fig. 1 is the electrical block diagram of CRC-5 shift register in prior art;
Fig. 2 is the structural representation of the pseudorandom number generator of the integrated CRC check circuit that the utility model embodiment 1 provides;
Fig. 3 is the effect schematic diagram of the pseudorandom number generator output random number of the integrated CRC check circuit that application the utility model embodiment 1 provides.
Embodiment
Embodiment 1:
Fig. 2 is the structural representation of the pseudorandom number generator of the integrated CRC check circuit that the utility model embodiment 1 provides, as shown in the figure, the pseudorandom number generator of the integrated CRC check circuit that the utility model embodiment 1 provides comprises: in order to input the load module of data to be verified, be connected with load module and CRC check circuit in order to verify the data to be verified inputted, in order to the interference module of input nonlinearities data, the mapping circuit be all connected with interference module and CRC check circuit, and this mapping circuit then carries out XOR computing with interfering data in order to the state mapping CRC check circuit, the state temporary storage module be all connected with mapping circuit and CRC check circuit, this state temporary storage module is loaded into CRC check circuit after obtaining XOR operation result, be connected with mapping circuit and sampling circuit in order to export after extracting XOR operation result.
In the pseudorandom number generator of the integrated CRC check circuit provided in the utility model embodiment 1,
CRC check circuit is linear feedback shift register, this linear feedback shift register comprises multiple register and multiple logical operation door, and this logical operation door is exclusive or logic gate, this linear feedback shift register is adopted to be CRC check circuit, can ensure that the data inputted obtain precise verification, thus ensure that the normal execution that CRC verifies.
In the pseudorandom number generator of the integrated CRC check circuit provided in the utility model embodiment 1, mapping circuit is made up of one or more exclusive or logic gate, introduce mapping circuit, the state of CRC check circuit is mapped, simultaneously together with interference module, the pseudorandom obtaining a single-bit exports, and the meaning of interference module is to introduce extra enchancement factor, plays perturbation action to output.
In the pseudorandom number generator of the integrated CRC check circuit provided in the utility model embodiment 1, state temporary storage module is formed of registers, sampling circuit is a register, and the clock frequency of mapping circuit is r times of the clock frequency of sampling circuit, and r > 1, if r is 1.5,2.5,4,7.5,8 etc.; In the non-checking data stage, state temporary storage module obtains the XOR operation result exported from mapping circuit, and send this XOR operation result to CRC check circuit, mapping circuit is sent to after the displacement of CRC check circuit, simultaneously, mapping circuit also obtains interfering data from interference module, exported by sampling circuit after carrying out logic XOR, thus obtain pseudo random number, and pseudo random number comparatively reliably can be exported, for the circuit exploitation of pseudorandom number generator provides the foundation.
When the pseudorandom number generator of the integrated CRC check circuit that application the utility model embodiment 1 provides carries out work, needing the data time section of verification, CRC check circuit carries out work in a normal way, when data time section starts, according to protocol requirement, linear shift register is set to complete 1, then carries out CRC computing, completes the work of verification; And in other data segment of non-verification or the free time of countless certificate, and the external control module of the pseudorandom number generator of whole integrated CRC check circuit enable signal effective time, this CRC check circuit works on, data are moved into from state temporary storage module of the present utility model, and input to mapping circuit with the interfering data that interference module exports, mapping circuit carries out with lasting generation random number after corresponding computing, thus provides reliable pseudo random number.
Below elaborate, the principle of work of the pseudorandom number generator of the integrated CRC check circuit that the utility model embodiment 1 provides.
Containing m register in the linear shift register of CRC-m, its state is designated as Sti (i=1,2, ..., m), and the vector of 1 of m bit is designated as Fm, the state transition function of CRC-m is designated as fcrc, state in state temporary storage module is Ss, Ss is m position, and the temporary choice function of state temporary storage module is fs, is m position, wherein, i-th is that 1 expression selects the data of position corresponding in Ss to be loaded into linear shift register.Small part position is only had to be 1 in the Ss of m position, so only corresponding 1 position need be provided with register, to save hardware resource when Ss realizes.
Then the computing of the n-th state is designated as,
(1) multiplication in formula represents logical and, addition presentation logic XOR.
Mapping circuit is then map the state of CRC check circuit, and simultaneously together with the interfering data of interference module, the pseudorandom obtaining a single-bit exports.The meaning of interference module is to introduce extra enchancement factor, plays perturbation action to output.The interfering data of interference module is obtained by other and the incoherent node of CRC computing of circuit, is single-bit, is designated as Dn.Mapping function f produces single-bit from the state of shift register and interference module and exports, and comprises m bit, be designated as fi (i=1,2 ... m).In order to keep the harmony of sequence unaffected, mapping circuit adopts XOR computing, thus obtains XOR operation result.It exports expression formula,
(2) multiplication in formula represents logical and, addition presentation logic XOR.
The effect of state temporary storage module is that the register in the state temporary storage module that its Ss represents when non-checking data section is initial is loaded into shift register by formula (1), moves into data to Ss in non-other moment of checking data section from the output of mapping circuit.In checking data section, the data of state temporary storage module are locked, and namely do not change.
So, according to formula (1), non-checking data section, the initial value of the state of CRC check circuit is determined jointly by the final value of last checking data and the final value of last time non-checking data section.Doing so avoids non-checking data section directly by the impact of checking data, because checking data is communication data, its value is normally completely predictable, and is loaded into the data of non-verification section last time, just can ensure the continuity of different non-checking data section, increase unpredictability.
The output of sampling circuit to mapping circuit is sampled, and with the rate-adaptive pacemaker random number of sampling clock.The sampling clock of sampling circuit is set to the clock being slower than mapping circuit, interference module, state temporary storage module, CRC check circuit, these modules of load module, the clock of mapping circuit, interference module, state temporary storage module, CRC check circuit, these modules of load module is consistent, and between the sampling circuit module consistent with these be r doubly.Then export kth position random number can be expressed as,
O(k)＝B(r×k) (3)
From the above, load module, interference module, CRC check circuit, mapping circuit and state temporary storage module work in the master clock frequency of CRC check; Sampling circuit then works in sampling clock frequency.
The utility model is applicable to the various occasions of CRC serial circuit, and the mode that the selection of m can be any agreement defined for any number or CRC-m works.But, in order to the change making random number is larger, suitably select that m value is larger, the interfering data change of data and interference module greatly, the quality of enhancing random number can be conducive to.
The pseudorandom number generator of the integrated CRC check circuit that the utility model embodiment 1 provides, based on CRC check circuit, increase a small amount of logic gate, namely can be applied to and absolute requirement is not had to unpredictability, do not need the occasion of true random number, as filler required when supply embedded software, hardware algorithm needs, transmission data in SoC (SOC (system on a chip)) etc.
Fig. 3 is the effect schematic diagram of the pseudorandom number generator output random number of the integrated CRC check circuit that application the utility model embodiment 1 provides; As shown in the figure, the CRC-32 selecting USB3.0 agreement to specify.The following f=1010 0,000 0,000 1,000 0,000 0,000 1000 of each Selecting parameter 0000, fs=0000 0,000 0,000 1,111 0,000 0,000 0,000 1111, r=4, selection check data segment 72 bit, free segment 128 bit.
Draw the Two dimensional Distribution of continuous 16 bit random i lumber, as shown in the figure.A () is for directly obtaining the result of 40000 Bit datas from CRC check circuit and mapping circuit; B () is for adding the result after state temporary storage module; (c) for add state temporary storage module and load module by 0.05 the result that changes of probability; (d) for adding state temporary storage module, load module and interference module with 0.05 probability change, and the result after sampling.
Simultaneously we calculate design export the entropy of data with the quality of quantitative analysis random number, its computing formula is,
Wherein i represents that unit of account is i bit, so have 2
iindividual symbol, n is total number of symbols, n
jfor the number of a jth symbol, H
iresult of calculation more represents unreasonable close to 1 and thinks.
Result when obtaining i=1-6 is 0.9999,0.9988,0.9993,0.9983,0.9953,0.9966.The quality of visible sequence is very good, can meet application requirement.
Can also see by Fig. 3, when without any process and introducing enchancement factor, data are fixing; The introducing of state temporary storage module makes data become many in the redirect of state space; As long as and in load module and interference module, introduce very small changing factor, the random number that the pseudorandom number generator of the integrated CRC check circuit that the utility model embodiment 1 provides exports can reach very high quality.
The data obtained in figure are more conservative, and in practical application, the change probability of load module and interference module is generally greater than 0.05, so result of practical application than better in figure, can should meet the demands completely.
So, the pseudorandom number generator of the integrated CRC check circuit that the utility model embodiment 1 provides, by on the basis of CRC check circuit, increase interference module, state temporary storage module, mapping circuit and sampling circuit, thus ensure that the pseudorandom number generator of this integrated CRC check circuit can export pseudo random number comparatively reliably, for the circuit exploitation of pseudorandom number generator provides the foundation, the normal execution that CRC verifies can be made again, do not affect its original function; Meanwhile, the hardware resource of increase is considerably less, thus on the basis of minimum cost, has accomplished function maximization, and then improves the product benefit of pseudorandom number generator of this integrated CRC check circuit.
It should be appreciated by those skilled in the art that those skilled in the art can realize described change case in conjunction with prior art and above-described embodiment, do not repeat them here.Such change case does not affect flesh and blood of the present utility model, does not repeat them here.
Above preferred embodiment of the present utility model is described.It is to be appreciated that the utility model is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, make many possible variations and modification not departing from technical solutions of the utility model, or be revised as the Equivalent embodiments of equivalent variations, this does not affect flesh and blood of the present utility model.Therefore, every content not departing from technical solutions of the utility model, according to technical spirit of the present utility model to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solutions of the utility model protection.
Claims (8)
1. a pseudorandom number generator for integrated CRC check circuit, is characterized in that, comprising:
Load module, it is configured to input data to be verified;
CRC check circuit, it is connected to described load module and is configured to verify described data to be verified;
Interference module, it is configured to input nonlinearities data;
Mapping circuit, it is connected to described interference module and described CRC check circuit, and the state being configured to map described CRC check circuit then carries out XOR computing with described interfering data;
State temporary storage module, it is connected to described mapping circuit and described CRC check circuit, and is loaded into described CRC check circuit after being configured to obtain described XOR operation result;
Sampling circuit, it is connected to described mapping circuit and exports after being configured to extract described XOR operation result.
2. the pseudorandom number generator of integrated CRC check circuit as claimed in claim 1, is characterized in that, described CRC check circuit is linear feedback shift register.
3. the pseudorandom number generator of integrated CRC check circuit as claimed in claim 2, is characterized in that, described linear feedback shift register comprises multiple register and multiple logical operation door.
4. the pseudorandom number generator of integrated CRC check circuit as claimed in claim 3, is characterized in that, described logical operation door is exclusive or logic gate.
5. the pseudorandom number generator of integrated CRC check circuit as claimed in claim 1, it is characterized in that, described mapping circuit is made up of one or more exclusive or logic gate.
6. the pseudorandom number generator of integrated CRC check circuit as claimed in claim 1, is characterized in that, described state temporary storage module is formed of registers.
7. the pseudorandom number generator of integrated CRC check circuit as claimed in claim 1, is characterized in that, described sampling circuit is a register.
8. the pseudorandom number generator of integrated CRC check circuit as claimed in claim 1, is characterized in that, the clock frequency of described mapping circuit is r times of the clock frequency of described sampling circuit, and r > 1.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104199635A (en) * | 2014-09-23 | 2014-12-10 | 无锡华大国奇科技有限公司 | Pseudo-random number generator integrating CRC (cyclic redundancy check) circuit |
| CN109245883A (en) * | 2018-09-21 | 2019-01-18 | 深圳市德名利电子有限公司 | A kind of randomizer and production methods are counted at any time |
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2014
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104199635A (en) * | 2014-09-23 | 2014-12-10 | 无锡华大国奇科技有限公司 | Pseudo-random number generator integrating CRC (cyclic redundancy check) circuit |
| CN104199635B (en) * | 2014-09-23 | 2017-11-07 | 无锡华大国奇科技有限公司 | The pseudorandom number generator of integrated CRC check circuit |
| CN109245883A (en) * | 2018-09-21 | 2019-01-18 | 深圳市德名利电子有限公司 | A kind of randomizer and production methods are counted at any time |
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