CN104199635B - The pseudorandom number generator of integrated CRC check circuit - Google Patents
The pseudorandom number generator of integrated CRC check circuit Download PDFInfo
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- CN104199635B CN104199635B CN201410491887.9A CN201410491887A CN104199635B CN 104199635 B CN104199635 B CN 104199635B CN 201410491887 A CN201410491887 A CN 201410491887A CN 104199635 B CN104199635 B CN 104199635B
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Abstract
The invention discloses a kind of pseudorandom number generator of integrated CRC check circuit, belong to pseudorandom number generator technical field, the pseudorandom number generator for the integrated CRC check circuit that the present invention is provided passes through on the basis of CRC check circuit, increase interference module, state temporary storage module, mapping circuit and sampling circuit, so as to ensure that the pseudorandom number generator of the integrated CRC check circuit can export more reliable pseudo random number, provided the foundation for the circuit exploitation of pseudo random number, the normal execution of CRC validation can be caused again, its original function is not influenceed；Meanwhile, increased hardware resource is considerably less, so as on the basis of minimum cost, accomplish function maximization, and then improve the product benefit of the pseudorandom number generator of the integrated CRC check circuit.
Description
Technical field
The present invention relates to the pseudo random number hair of a kind of pseudorandom number generator, more particularly to a kind of integrated CRC check circuit
Raw device.
Background technology
CRC validation code is CRC, is widely present in data communication field, and it is to be used for check number that it, which is acted on,
According to.The essence that CRC validation code is produced is the polynomial division of mould 2, and the check code of generation is the remainder of division.The production of its check code
Life constantly can carry out subtraction and displacement with data to a generator polynomial.In actual applications, for generator polynomial
Selection have multiple choices mode.Which kind of multinomial is specifically selected, depending on the regulation of agreement.Such as, in USB3.0 communication protocols
In view, 3 kinds of CRC check codes are there is, for the CRC-16 in packet header, for the CRC-5 of link control word, and for counting
According to the CRC-32 of part, the multinomial is respectively 100Bh, 00101b and 04C11DB7h.Such as 00101b, is represented multinomial respectively
Formula everybody coefficient from high to low, corresponding multinomial is x5+x2+1。
The subtraction of mould 2 is xor operation, so can very easily use circuit realiration.In actual applications, have serial
Or parallel implementation.One bit of serial mode data per treatment, usually using linear feedback shift register
(Linear Feedback Shift Registers,LFSR).CRC-5 shift-register circuits such as Fig. 1 institutes in USB3.0
Show, Fig. 1 is the electrical block diagram of CRC-5 shift registers.USB3.0 agreements define CRC create-rule, master gage
Calculate register initial value when starting and be set as complete 1, data are calculated since low level, and are inverted high-low-position after result is negated, from
And obtain terminal check code.
Pseudorandom number generator for producing pseudo random number is generally produced with macrocyclic random number using LFSR.
The LFSR includes multiple series connection registers and an XOR circuit, wherein, the output data of predetermined register is different by this
Or logic circuit is fed back to first register.Due to providing XOR circuit in feedback path, so that linearly
Feedback shift register produces the random number with longer cycle.
In encrypted circuit of password etc. is produced using pseudo random number, if display pseudo-random number sequence or pseudorandom are patrolled
Volume, then can reduce an original plaintext from ciphertext obtained so that effectively produce it is uncertain with
Machine Number Sequence is extremely important.
It follows that pseudorandom number generator of the prior art can not provide relatively reliable pseudo random number, so that
It is unfavorable for circuit exploitation of pseudorandom number generator etc..
The content of the invention
For above-mentioned problem, the present invention provides a kind of pseudorandom number generator of integrated CRC check circuit, with gram
The problem of pseudorandom number generator of the prior art can not provide comparatively reliable pseudo random number is taken, so as to both provide
More reliable pseudo random number, is that the circuit exploitation of pseudorandom number generator provides the foundation, in turn ensure that the normal of CRC validation
Perform, meanwhile, it is few using hardware resource, on the basis of minimum cost, accomplish function maximization, improve product benefit.
To achieve these goals, the technical scheme taken of the present invention is：
A kind of pseudorandom number generator of integrated CRC check circuit, wherein, including：
Input module, it is configured to input data to be verified；
CRC check circuit, it is connected to the input module and is configured to the verification data to be tested；
Interference module, it is configured to input nonlinearities data；
Mapping circuit, it is connected to the interference module and the CRC check circuit, and is configured to map the CRC schools
The state on electrical verification road then carries out XOR computing with the interference data；
State temporary storage module, it is connected to the mapping circuit and the CRC check circuit, and is configured to obtain described different
Or the CRC check circuit is loaded into after logic operation result；
Sampling circuit, it is connected to the mapping circuit and is configured to extract after the XOR operation result and exports.
The pseudorandom number generator of above-mentioned integrated CRC check circuit, wherein, the CRC check circuit is linear feedback
Shift register.
The pseudorandom number generator of above-mentioned integrated CRC check circuit, wherein, the linear feedback shift register includes
Multiple registers and multiple logical operations door.
The pseudorandom number generator of above-mentioned integrated CRC check circuit, wherein, the logical operation door is XOR
Door.
The pseudorandom number generator of above-mentioned integrated CRC check circuit, wherein, the mapping circuit is by one or more different
Or gate composition.
The pseudorandom number generator of above-mentioned integrated CRC check circuit, wherein, the state temporary storage module is by multiple deposits
Device is constituted.
The pseudorandom number generator of above-mentioned integrated CRC check circuit, wherein, the sampling circuit is a register.
The pseudorandom number generator of above-mentioned integrated CRC check circuit, wherein, the clock frequency of the mapping circuit is institute
State the clock frequency of sampling circuit r times, and r ＞ 1.
Above-mentioned technical proposal has the following advantages that or beneficial effect：
A kind of pseudorandom number generator for integrated CRC check circuit that the present invention is provided, passes through the base in CRC check circuit
On plinth, increase interference module, state temporary storage module, mapping circuit and sampling circuit, so as to ensure that the integrated CRC check circuit
Pseudorandom number generator can export more reliable pseudo random number, for pseudorandom number generator circuit exploitation provide base
Plinth, and the normal execution of CRC validation can be caused, its original function is not influenceed；Meanwhile, increased hardware resource is considerably less, so that
On the basis of minimum cost, function maximization is accomplished, and then has improved the pseudo random number of the integrated CRC check circuit occur
The product benefit of device.
Brief description of the drawings
By reading the detailed description made with reference to the following drawings to non-limiting example, the present invention and its feature, outside
Shape and advantage will become more apparent.Identical mark indicates identical part in whole accompanying drawings.Not deliberately according to than
Example draws accompanying drawing, it is preferred that emphasis is show the purport of the present invention.
Fig. 1 is the electrical block diagram of CRC-5 shift registers in the prior art；
Fig. 2 is the structural representation of the pseudorandom number generator for the integrated CRC check circuit that the embodiment of the present invention 1 is provided；
Fig. 3 is the pseudorandom number generator output random number of the integrated CRC check circuit provided using the embodiment of the present invention 1
Effect diagram.
Embodiment
Embodiment 1：
Fig. 2 is the structural representation of the pseudorandom number generator for the integrated CRC check circuit that the embodiment of the present invention 1 is provided；
As illustrated, the pseudorandom number generator for the integrated CRC check circuit that the embodiment of the present invention 1 is provided includes：School is treated to input
The input module of data is tested, is connected with input module and to the CRC check circuit for the data to be tested for verifying input, to defeated
Enter to disturb the interference module of data, the mapping circuit being all connected with interference module and CRC check circuit, and the mapping circuit is used to
The state for mapping CRC check circuit then carries out XOR computing with interference data, equal with mapping circuit and CRC check circuit
The state temporary storage module of connection, the state temporary storage module to be loaded into CRC check circuit after obtaining XOR operation result, with
Mapping circuit is connected and to extract the sampling circuit exported after XOR operation result.
In the pseudorandom number generator for the integrated CRC check circuit that the embodiment of the present invention 1 is provided, CRC check circuit is
Linear feedback shift register, the linear feedback shift register includes multiple registers and multiple logical operations door, and this is patrolled
It is exclusive or logic gate to collect computing door, uses the linear feedback shift register for CRC check circuit, ensure that the data of input
Precise verification is obtained, so as to ensure that the normal execution of CRC validation.
In the pseudorandom number generator for the integrated CRC check circuit that the embodiment of the present invention 1 is provided, mapping circuit is by one
Or multiple exclusive or logic gate compositions, mapping circuit is introduced, the state to CRC check circuit maps, while and interference module
Together, the pseudo random output of a single-bit is obtained, the meaning of interference module is to introduce extra enchancement factor, to output
Play perturbation action.
The embodiment of the present invention 1 provide integrated CRC check circuit pseudorandom number generator in, state temporary storage module by
Multiple register compositions, sampling circuit is a register, and the clock frequency of mapping circuit is the clock frequency of sampling circuit
R times, and r ＞ 1, such as r be 1.5,2.5,4,7.5,8；In the non-verification data stage, state temporary storage module is obtained from mapping circuit
The XOR operation result of output is taken, and sends the XOR operation result to CRC check circuit, by CRC check
Mapping circuit is sent to after the displacement of circuit, meanwhile, mapping circuit also obtains disturbing data from interference module, carries out logic different
Or exported after computing by sampling circuit, so as to obtain pseudo random number, and more reliable pseudo random number can be exported,
Provided the foundation for the circuit exploitation of pseudorandom number generator.
When the pseudorandom number generator of the integrated CRC check circuit provided using the embodiment of the present invention 1 is operated, needing
The data time to be verified section, CRC check circuit is operated in a normal way, when data time section starts, according to association
View requires that linear shift register is set to complete 1, then carries out CRC operation, completes the work of verification；And non-verification its
The free time of its data segment or no data, and the outside control of the pseudorandom number generator of whole integrated CRC check circuit
When the enable signal of module is effective, the CRC check circuit is worked on, and number is moved into from the state temporary storage module of the present invention
According to, and the interference data input exported with interference module, to mapping circuit, mapping circuit is carried out after corresponding computing with lasting production
Raw random number, so as to provide reliable pseudo random number.
It is detailed below, the work of the pseudorandom number generator for the integrated CRC check circuit that the embodiment of the present invention 1 is provided
Principle.
Containing m register in CRC-m linear shift register, its state is designated as Sti (i=1,2 ..., m), and general
1 vector of m bit is designated as Fm, and the state that CRC-m state transition function is designated as in fcrc, state temporary storage module is Ss,
Ss is m, and the temporary selection function of state temporary storage module is fs, is m, wherein, i-th bit is 1 expression selection correspondence in Ss
The data of position are loaded into linear shift register.It is 1 there was only small part position in the Ss of m, so only need to be 1 correspondence when Ss is realized
Register is installed, to save hardware resource.
Then the computing of n-th of state is designated as,
(1) multiplication in formula represents logical AND, and addition represents logic XOR.
Mapping circuit is then that the state of CRC check circuit is mapped, while together with the interference data of interference module,
Obtain the pseudo random output of a single-bit.The meaning of interference module is to introduce extra enchancement factor, output is played and disturbed
Action is used.The interference data of interference module are obtained by the incoherent node of other and CRC operation of circuit, are single-bit, are designated as
Dn.Mapping function f produces single-bit output from the state and interference module of shift register, comprising m bit, is designated as fi (i=
1,2,...m).In order to keep the harmonious unaffected of sequence, mapping circuit uses XOR computing, so as to obtain XOR
Logic operation result.It exports expression formula,
(2) multiplication in formula represents logical AND, and addition represents logic XOR.
The effect of state temporary storage module is posting in the state temporary storage module that its Ss is represented when non-verification data section is initial
Storage is loaded into shift register by formula (1), non-verification data section other moment from the output of mapping circuit move into data to
Ss.In verification data section, the data of state temporary storage module are locked, i.e., not changed.
So, according to formula (1), non-verification data section, the initial value of the state of CRC check circuit is by last school
The final value of the final value and last non-verification data section of testing data is together decided on.Doing so avoids non-verification data section directly by
The influence of verification data, because verification data is communication data, its value is typically entirely predictable, and is loaded into last time non-verification
The data of section, it is ensured that the continuity of different non-verification data sections, increases unpredictability.
Output of the sampling circuit to mapping circuit is sampled, and with the rate-adaptive pacemaker random number of sampling clock.Sampling electricity
The sampling clock on road be set to be slower than mapping circuit, interference module, state temporary storage module, CRC check circuit, input module these
The clock of module, mapping circuit, interference module, state temporary storage module, CRC check circuit, the clock of input module these modules
It is consistent, and between the sampling circuit module consistent with these is r times.Then output kth position random number is represented by,
O (k)=B (r × k) (3)
From the foregoing, input module, interference module, CRC check circuit, mapping circuit and state temporary storage module are worked in
The master clock frequency of CRC check；And sampling circuit then works in sampling clock frequency.
The present invention is applied to the various occasions of CRC serial circuits, and m selection can be any number or CRC-m is any
The mode of agreement defined works.But, it is appropriate to select m values bigger, data and dry in order that the change for obtaining random number is bigger
The interference data variation for disturbing module is big, can be conducive to strengthening the quality of random number.
The pseudorandom number generator for the integrated CRC check circuit that the embodiment of the present invention 1 is provided, based on CRC check circuit, increases
Plus a small amount of gate, you can definitely not required applied to unpredictability, it is not necessary to the occasion of true random number, such as SoC
Supply embedded software, hardware algorithm need, send filler required during data etc. in (on-chip system).
Fig. 3 is the pseudorandom number generator output random number of the integrated CRC check circuit provided using the embodiment of the present invention 1
Effect diagram；As illustrated, CRC-32 as defined in selection USB3.0 agreements.Each parameter selects following f=1010 0000
0000 1,000 0,000 0,000 1,000 0000, fs=0000 0,000 0,000 1,111 0,000 0,000 0,000 1111, r=
4, the bit of selection check data segment 72, the bit of free segment 128.
The Two dimensional Distribution of continuous 16 bit random i lumber is drawn, as shown in the figure.(a) for directly from CRC check circuit and mapping
Circuit obtains the result of 40000 bit datas；(b) it is plus the result after state temporary storage module；(c) it is to keep in mould plus state
The result that block and input module are changed by 0.05 probability；(d) it is plus state temporary storage module, input module and interference
Module is changed with 0.05 probability, and the result after being sampled.
We calculate the entropy of design institute output data with the quality of quantitative analysis random number simultaneously, and its calculation formula is,
Wherein i represents that unit of account is i bit, so having 2iIndividual symbol, n is total number of symbols, njFor j-th
The number of symbol, HiResult of calculation represents more preferable closer to 1.
Result when obtaining i=1-6 is 0.9999,0.9988,0.9993,0.9983,0.9953,0.9966.It can be seen that sequence
The quality of row is very good, can meet application requirement.
It can further be seen that when not any processing and introducing enchancement factor, data are fixed in Fig. 3；State is temporary
The introducing of storing module causes data to become many in redirecting for state space；As long as and introducing very micro- in input module and interference module
Small changing factor, the random number of the pseudorandom number generator output for the integrated CRC check circuit that the embodiment of the present invention 1 is provided can
Reach very high quality.
The data obtained in figure are than more conservative, and in practical application, the change probability of input module and interference module is typically big
In 0.05, so result of practical application should be than that more preferably, can meet requirement completely in figure.
So, the pseudorandom number generator for the integrated CRC check circuit that the embodiment of the present invention 1 is provided, by CRC check
On the basis of circuit, increase interference module, state temporary storage module, mapping circuit and sampling circuit, so as to ensure that the integrated CRC
The pseudorandom number generator of checking circuit can export more reliable pseudo random number, be the circuit exploitation of pseudorandom number generator
Provide the foundation, and the normal execution of CRC validation can be caused, its original function is not influenceed；Meanwhile, increased hardware resource is very
It is few so that on the basis of minimum cost, accomplished function maximization, and then improve the integrated CRC check circuit it is pseudo- with
The product benefit of machine number generator.
It should be appreciated by those skilled in the art that those skilled in the art combine prior art and above-described embodiment can be real
The existing change case, will not be described here.Such change case has no effect on the substantive content of the present invention, will not be described here.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, wherein the equipment and structure be not described in detail to the greatest extent are construed as giving reality with the common mode in this area
Apply；Any those skilled in the art, many possible variations and modification are made not departing from technical solution of the present invention, or
The equivalent embodiment of equivalent variations is revised as, this has no effect on the substantive content of the present invention.Therefore, it is every without departing from skill of the present invention
The content of art scheme, according to technical spirit of the invention is to any simple modification made for any of the above embodiments, equivalent variations and repaiies
Decorations, still fall within technical solution of the present invention protection in the range of.
Claims (6)
1. a kind of pseudorandom number generator of integrated CRC check circuit, it is characterised in that including：
Input module, it is configured to input data to be verified；
CRC check circuit, it is connected to the input module and is configured to the verification data to be verified；
Interference module, it is configured to input nonlinearities data；
Mapping circuit, it is connected to the interference module and the CRC check circuit, and is configured to map the CRC check electricity
The state on road then carries out XOR computing with the interference data；
State temporary storage module, it is connected to the mapping circuit and the CRC check circuit, and is configured to obtain the XOR and patrols
The CRC check circuit is loaded into after collecting operation result；
Sampling circuit, it is connected to the mapping circuit and is configured to extract after the XOR operation result and exports
Wherein, the CRC check circuit is linear feedback shift register；The clock frequency of the mapping circuit is the sampling
R times of the clock frequency of circuit, and r ＞ 1.
2. the pseudorandom number generator of integrated CRC check circuit as claimed in claim 1, it is characterised in that described linear anti-
Presenting shift register includes multiple registers and multiple logical operations door.
3. the pseudorandom number generator of integrated CRC check circuit as claimed in claim 2, it is characterised in that the logic fortune
Calculation door is exclusive or logic gate.
4. the pseudorandom number generator of integrated CRC check circuit as claimed in claim 1, it is characterised in that the mapping electricity
It route one or more exclusive or logic gate compositions.
5. the pseudorandom number generator of integrated CRC check circuit as claimed in claim 1, it is characterised in that the state is temporary
Storing module is formed of registers.
6. the pseudorandom number generator of integrated CRC check circuit as claimed in claim 1, it is characterised in that the sampling electricity
Lu Weiyi register.
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| CN109474379B (en) * | 2017-09-08 | 2022-05-06 | 华为技术有限公司 | Encoding method and device |
| CN110502209B (en) * | 2019-08-16 | 2021-05-25 | 兆讯恒达科技股份有限公司 | Method for preventing random number generator from injection attack |
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