JPH0237458A - Bus control system for redundant bus constitution - Google Patents

Abstract

PURPOSE:To reduce the load on software by excluding the attribute management for current system/stand-by system of higher-order busses or the like of the processing program in each processing module. CONSTITUTION:Attributes of plural higher-order busses are determined by the control of one master processing module 10 out of processing modules of system elements and access address attributes of bus controllers 24 and 25 viewed from a central processing unit 21 of respective processing modules 20 are determined by higher-order bus attributes from the master processing module 10, thus performing the bus control. Consequently, access address attributes of bus controllers 24 and 25 viewed from the central processing device 21 in processing modules 20 are determined by attributes of higher-order busses connected to bus controllers 24 and 25. That is, for example higher-order bus attributes of current system/stand-by system are determined under the control of a control program in the processing module 20 to be the master processing module 10. Thus, the load on higher-order bus management of the processing program is reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a bus control system with a redundant bus configuration, and in particular,
Central processing unit, memo i eight people output device.

A multiprocessor system in which a plurality of processing modules in which a line control controller and a bus controller are commonly connected via a lower-level bus are connected to a common upper-level bus via the bus controller, each processing module having a plurality of bus controllers, The present invention relates to a bus control system with a redundant bus configuration in which a plurality of high-level buses commonly connecting processing modules are configured to correspond to bus controllers.

[Conventional technology]

2. Description of the Related Art Conventionally, one method for configuring a multiprocessor system is a flexibly coupled multiprocessor system in which the system is configured by connecting each processor module to a common bus. In such a flexibly coupled multiprocessor system, each processor module can be connected to any number of processor modules, so the system configuration is highly flexible. However, in such a multiprocessor system, the bus controller, which mediates the bus connecting each processor module, requires fixed address assignment from the perspective of the processor of each processor module.

In addition, as a known document regarding such a flexible coupling multiprocessor system, for example, Japanese Patent Application Laid-Open No. 1634-1983
Publication No. 60 is mentioned.

[Problem to be solved by the invention]

By the way, in the above-mentioned flexible coupling multiprocessor system, in order to improve the reliability of the system, the system is configured in such a manner that the common bus connecting each processor module is duplicated. In this way, when the common bus (upper bus) that connects processor modules has a redundant configuration of the active system and standby system, each processor module has a Correspondingly, an active bus controller and a standby path controller are provided. Furthermore, access addresses for the active bus controller and standby bus controller are determined to be different from the processors in each processor module, and each bus controller is controlled individually. ing.

The attributes such as access address of this bus controller are as follows.
This is provided in the bus controller itself, and does not change even if the attribute of the higher-level bus changes to active or standby. Therefore, in programs that control communication between processor modules included in each bus controller, as well as failure processing programs in the event of a failure in a higher-level bus, attributes such as the access address of the bus controller and the It is necessary to manage attributes such as the active system or standby system of the upper-level bus, which places a heavy load on each program process. Also, if one bus controller fails,
If the entire upper bus is adversely affected, it is difficult to isolate the fault from the outside and pinpoint the fault. However, there is a problem in that it may sometimes lead to situations that are unfavorable for maintenance and operation.

The present invention has been made to solve the above problems.

An object of the present invention is to dynamically change the access address attribute of the bus controller connected to the upper bus in accordance with changes in the attributes such as the active system or standby system of the upper bus, thereby eliminating errors in the program. An object of the present invention is to provide a bus control method that reduces the management load of a higher-level bus.

Another object of the present invention is to perform bus control that obtains results equivalent to replacing the bus controller hardware itself by changing the connection of the upper level bus for each processing module, thereby helping to identify faulty parts. The aim is to do this more appropriately.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

In order to achieve the above object, the present invention connects a plurality of processing modules in which a central processing unit, a memory, an input/output device two-line controller, and a bus controller are commonly connected via a lower bus to a common controller via the bus controller. A redundant bus configuration in which, in a multiprocessor system connected to a higher-level bus, each processing module has multiple bus controllers, and the higher-level bus that commonly connects the levers of each processing module has multiple buses corresponding to the bus controllers. Under the control of one master processing module among the processing modules, the attributes of multiple upper-level buses are determined, and the access address attributes of the bus controller seen from the central processing unit of each processing module are determined by the upper-level bus attributes from the master processing module. It is characterized by performing bus control determined by bus attributes.

[Effect]

According to the above means, a plurality of processing modules in which a central processing unit, a memory, an input/output device two-line controller, and a bus controller are commonly connected via a lower bus are connected to a common upper bus through the bus controller. In a processor system, each processing module is equipped with a plurality of bus controllers, and the system is configured with a redundant bus configuration in which the upper bus that commonly connects each processing module is configured with multiple buses corresponding to the bus controllers. Ru. Then, under the control of one master processing module among the processing modules of the system elements, the attributes of multiple upper-level buses are determined, and the access address attribute of the bus controller seen from the central processing unit of each processing module is determined by the master processing module. Performs bus control determined by upper-level bus attributes from.

Therefore, the access address attribute of the bus controller viewed from the central processing unit in the processing module is determined by the attribute of the upper level bus connected to the bus controller. That is, the attribute of the upper bus, ie, the attribute 5, eg, active system or standby system, is determined under the control of the control program in the processing module serving as the master processing module. Therefore, in the program processing of the central processing unit in each processing module.

There is no need to be particularly aware of the access address attribute of the upper bus.

Also, within each module, the access address of the active bus controller connected to the active host bus and the access address of the standby bus controller connected to the standby host bus are the access addresses of the active bus controller connected to the active host bus or Determined by the standby attribute. That is, an operation equivalent to replacing the hardware itself of a plurality of bus controllers in each module can be performed under the control of the control program in the master processing module. Therefore, by changing the connection of the upper-level bus for each processing module, it is possible to perform bus control that achieves the same result as replacing the bus controller hardware itself, and to more appropriately identify faulty parts. can.

〔Example〕

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

FIG. 1 is a block diagram of a multiprocessor system according to an embodiment of the present invention. In FIG. 1, 10 is a master processing module, 20 is a processing module, 40 is a first upper level bus, and 50 is a second upper level bus. The multiprocessor system has a redundant bus configuration with two buses, a first upper bus 40 and a second upper bus 50, to which a plurality of processing modules 20 and one master processing module 10 are commonly connected. The system configuration is as follows.

The master processing module 10 includes central processing modules [(CPU) 11. Memory (MS)12. First bus controller (BCI)
14° Second bus controller (BC2) 15. Console control unit 16. A bus control circuit 17 is provided,
It is a master processing unit that performs master processing for bus control. An operation terminal 19 is connected to the console control unit 16 for receiving operation input from the outside. Each processing module 20 also includes a central processing unit 21 and a memory 22 . 1st
bus controller 24. Second bus controller 25
．． A line control section 26 is provided, and serves as a line control processing unit that controls each line. The line control unit 26 is connected to a line group 27 that is subject to line control, and performs communication control on data input and output from one line group 27.

In the multiprocessor system configured in this way, the bus control circuit 17 of the master processing module 10 is
Upon receiving instructions from the central processing unit 11.

Control is performed to determine the bus address attributes of the first higher-level path 40 and the second higher-level bus 50. Note that a plurality of each of the processing modules 20 are commonly connected by an upper-level bus and incorporated into the system, but here, for example, a processing module 20a having the same configuration as the processing module 20 is used as a standby for one line control processing unit. As a system processing module,
Commonly connected to the upper bus.

FIG. 2 is a diagram illustrating the configuration of the signal lines of the upper bus of the main part of the system according to an embodiment of the present invention. As shown in FIG. 2, the signal lines of the upper bus include data lines 41 as many as the bit width to be transmitted, control lines 42 as many as required for transmission control, and as attributes of the upper bus. It consists of a single signal line ACT/SBY display line 43 that indicates whether the bus is an active system (ACT) or a standby system (SBY).

FIG. 3 is a block diagram showing the configuration of a bus control circuit that determines the attributes of an upper-level bus. As shown in FIG. 3, the bus control circuit 17 is the central processing unit in the master processing module! (CPU) 11; a decoder 17a that decodes instructions from the decoder 11; a flip-flop 17b that inverts according to the decoding output result of the decoder 17a; and an inverter 1
7c, an output driver 17d that drives the output of the flip-flop 17b and outputs it to the bus, and an output driver 17e that drives the inverted output from the flip-flop 17b and outputs it to the bus. This bus control circuit 17 operates on the first upper bus 40 (7) ACT/SBY display line 43 in response to an instruction command of a predetermined code from the central processing unit W (CPU) 11 in the master processing module.
The bus attribute signals sent to the ACT/SBY display line 53 of the second upper bus 50 are complementarily inverted and output. In addition, in FIG. 3, 14 is a first bus controller, and 15 is a second bus controller.

FIG. 4 is a block diagram showing the configuration of main parts of the bus controller. In FIG. 4, 14a is a microprocessor, 14b is a host bus interface control circuit, and 14
C is a lower bus interface control circuit, and 14d is a transmitting/receiving buffer memory.

In the bus controller 14, when the upper bus interface control circuit 14b receives a signal of "1" or rOJ from the AC:T/SBY display line 43 of the first upper bus, it registers it in the upper bus ACT/SBY display flag storage section 31. . This upper bus ACT/S B Y display flag storage unit 3
The flag 1 is read by the microprocessor 14a, and the value of the read flag in the upper bus ACT/SBY display flag storage section 31 is read by the microprocessor 14a.
In order to reflect it on the lower bus side, it is registered in the lower bus side bus ACT/SBY display flag storage section 32 of the lower bus interface control circuit 14c. The lower bus interface control circuit 14c also includes a DMA address register 33 that sets an access address when the bus controller 14 accesses the memory 12, and a reception address register that holds an instruction address when an instruction is issued from the CPU II. 34, a bus controller self-address register 35 having an address, and a comparison that compares the value of the received address register 34 with the value of the bus controller self-address register 35. The main components include a lower bus command reception display flag storage section 37 for registering comparison results.

FIG. 5 is a diagram showing a main part of an address space map showing the allocation of address spaces within a processing module. As shown in FIG. 5, the address space of the master processing module 10 includes an ACT bus controller command address space 1
2a, SBY system bus controller instruction address space 12
b, ACT-related command code area 12c, and ACT-related report area 12d.

An SBY-related command code area 12e and an SBY-related report area 12f are allocated. The ACT bus controller instruction address space 12a has an address (70000
0)1. ~(7OFFFF)t, 2 assigned, AC
This is the address space when issuing commands to the T-system bus controller. In addition, the SBY bus controller instruction address space 12b has addresses (710000), a to (71
FFFF)zi, and serves as the address space when issuing commands to the SBY bus controller. Address (800000)□6~(BFFFFF)1. is the address space of the memory 12. Furthermore, address (800000) 1. ~(8OF
FFF)8. An ACT system command code area 12c, which is a command area for the ACT system bus controller, and an ACT system report area 12d, which is a command execution result report area for the ACT system bus controller, are allocated. Also.

Address (810000), ~(81FFFF),,
, the SBY command code area 12e in the command area for the SBY bus controller, and the SB in the command execution result report area for the SBY bus controller.
A Y-type report area 12f is allocated.

FIG. 6 is a diagram illustrating the operational concept of bus address conversion in which a bus address is converted from a bus attribute signal by a bus control circuit. In FIG. 6, 33 is a DMA address register, and 35 is a bus controller self-address register. Here, the address code of the DMA address register 33 and the address code of the bus controller self-address register 35 are connected to the lower bus side bus ACT/
Based on the output value of the SBY display flag storage unit 32, (80XXXX)1. and (70X
XXX), G, or (81XXXX)1G and (71XXXX)0. It shows the concept of operation.

Next, the bus control operation of this embodiment will be explained.

Here, we will focus on the operation of the bus controller and
An example will be described in which bus control is performed by a processing operation according to a control procedure of a bus controller of a processing program running on U.

First, the initial state of the system is as follows.

The output value of the flip-flop 17b in the bus control circuit 17, which determines the bus attribute of the upper bus, is "0", and the first upper bus 40 is the ACT system, and the second upper bus 50 is the SBY system. As a result, within each processing module,
The first bus controller 14 (24) connected to the first higher-level bus 40 turns on the flag in the higher-level bus ACT/SBY display flag storage unit 31 by the microprocessor 14a in the bus controller (=ACT system: active system). ).

As a result, the flag in the lower bus side ACT/SBY display flag storage section 32 is set (output value "1"). Therefore, the address value of the self-address register 35 is (70)□6.

On the other hand, the second bus controller 15 (25) connected to the second higher-level bus 50 turns off the flag in the upper-level bus ACT/SBY display flag storage section (=SBY system: standby system) by the microprocessor in the bus controller. ), and as a result, the lower bus side ACT/SB
The Y display flag has been reset (output value "O").

Therefore, the address value of the self address register is (71
)1-There is a lot of yelling.

In such a system state, the operation of transferring data on the memory 22 in a certain processing module 20 to the memory 22 in another processing module 20 will be explained step by step. In addition, in the following explanation, when referring to each element of the processing module, in particular, when referring to the transmitting side, S is added after the reference number, and when referring to the receiving side, R is appended after the reference number. shall be indicated.

First, the processing program running on the CPU 21S in the processing module 20S starts at address (800000), ...
8OFFFF) □ The ACT system command code area 12c that sets the command for the determined ACT system bus controller in 6 contains the transfer destination bus controller upper bus address indicating the transfer destination processing module 20R, and the transfer data on the memory 22S. The start address, the number of transferred bytes, and various parameter values added to the transferred data are written and set as a command code.

Then, the processing program sends A on the lower bus 23S.
Command issue code to CT bus controller (70XX
XX)8. Send out. As a result, processing module 2
A first bus controller 24S, a second bus controller 25 . lEr, and line controller 26S
is (70)4. of the upper 1 byte of the address data value taken into the reception address register 34S. and the value of the self-address register 353 to determine whether the instruction is addressed to itself.6 As a result, the first path controller 24
If the comparison results match in S, the flag in the lower bus command reception display flag storage section 37S is turned on.

When the flag in the lower bus command reception display flag storage section 37S is turned on, the microprocessor (14a) in the first bus controller 24S causes the flag in the lower bus command reception display flag storage section 37S to be turned on. I know that. Next, the microprocessor (14a) sets an access address in the DMA access register 33S to read the command code set in a predetermined command code area on the memory 22S, and executes the DMA.
to access. Through this DMA access, the microprocessor (14a) knows the location of the transfer data and the processing content (data content to be transferred to other processing module 2OR, etc.)
The first upper bus 40 transfers the data via the upper bus interface control circuit (14b) according to the processing contents.As a result, the other processing module 2OR on the receiving side transfers the received transfer data to the first upper bus 40. Receive buffer memory (14c) in 1 bus controller 24R
is stored in Then, the microprocessor (14a) in the first bus controller 24R further transfers it to the received data storage area on the memory 22R in the processing module 2OR. On the other hand, the processing module 2 on the sending side
At O8, the transfer result on the upper bus 40 (the first bus controller 24 of the processing module 2OR on the destination side)
Result information such as whether the data was successfully sent to R without any trouble) is set in the ACT system report area (12d) on the memory 22S, and is reported to the processing program running on the CPU 2iS.

In such a data transfer process between processing modules, as is clear from the above description, when the processing program running on the CPU 21S executes the process of transmitting data via the ACT-based first upper bus 40, (70XXX
X)8. The fixed bus address information is only used, but it does not specify whether it is the first higher-order bus 40 of the ACT system or the second higher-order bus 50 of the SBY system. That is, the command is issued without determining whether to issue the command to the first bus controller 24 or the second bus controller 25. In this way, the access address attribute of the upper bus is not particularly considered in the program processing of the central processing unit in each processing module.

Next, an explanation will be given of the operation when a failure occurs in the active first upper-level bus 40 and switching to the standby second bus 50 is performed.

When a fault occurs on the first higher level bus 40, which is an ACT system, the processing program running on the CPU 2i in the processing module 20 detects the occurrence of this fault based on report information from the first bus controller 24, for example. Therefore, C
The processing program running on the PU 21 notifies the master processing module 10 of the occurrence of the failure and the details of the failure. In this case, notification processing is performed via the SBY-based second upper-level bus 50. Processing of this notification can be carried out, for example, by using the above-mentioned ACT
In the explanation of data transfer performed via the first upper bus 40 of the system, the upper bus for data transfer is referred to as SB.
This is done via the second upper level bus 50 of the Y system. That is, in this case, the command code area on the memory 22 is at address (810000).

~(81FFFF)0. The data transfer is performed under the control of the second bus controller 25 and the second bus controller 15, and the instruction code issued from the CPU 21 is (71XXXX)16.

CPU in the master processing module 10 that received the failure notification
II issues a command to the bus control circuit 17 that determines the upper bus attribute, and inverts the flip-flop 17b. As a result, the output value of the flip-flop 17b is r
QJ is reversed to “1” and ACT in the first upper bus 40
/SBY display line 43 is changed from "1" to "O", and ACT
system is switched to SBC system. In addition, the 2nd upper bus 5
ACT/SBY display tJA 53 in o is from “O” to “
1", and the SBY system is switched to the ACT system.

When the states of the (7) ACT/SBY display line 43 in the first upper bus 40 and the ACT/SBY display line 53 in the second upper bus 50 are switched, the first
Upper bus ACT/SB in bus controller 14.24
The Y display flag (31) changes from on to off, and the microphone in the first bus controller. The processor turns off the lower bus ACT/SBY display flag (32). Similarly, each bus ACT in the second bus controller 15.25 connected to the second higher level bus 50
Conversely, the /SBY display flag switches from off to on.

Switching between the ACT system and SBY system of the upper-level bus by switching the bus ACT/SBY display flag is managed by a program running on the CPU II in the master processing module 10, and this switching process is performed by the master processing module 10. This is done by a program running on the CPU II. Therefore, you do not need to know anything about each program running on the CPU 2i of other processing modules 20, and even when data is transferred later via the upper-level bus, the programs running on the CPU of each processing module are When transferring via the ACT system upper bus, (70XXXX) 4. All you have to do is to be aware of only this instruction code when performing the data transfer process. In this case, the data is actually transmitted and received via the second bus controller 25 connected to the second higher level bus 50, but the processing program of each processing module is specially designed to control the bus for data transfer. You don't have to do it.

As described above, according to the present embodiment, according to changes in the attributes such as active/standby of the upper level bus.

Attributes such as the access address of the bus controller connected to the bus controller also change dynamically without the control program being aware of it, and the management load on the control program can be reduced.

Furthermore, since the upper bus connection can be changed on a module-by-module basis, a result equivalent to replacing the bus controller hardware itself can be obtained. Therefore, when a failure occurs, the faulty part can be identified more appropriately.

The present invention has been specifically described above based on examples, but 1.
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

As described above, according to the present invention, the software load is reduced by eliminating the attribute management of the active/standby system of the upper bus by the processing program in each processing module. This is reflected in performance, etc.

[Brief explanation of the drawing]

1 is a block diagram of a multiprocessor system according to an embodiment of the present invention; FIG. 2 is a diagram illustrating the configuration of the signal lines of the upper bus of the main part of the system according to an embodiment of the present invention; FIG. 3 is a block diagram showing the configuration of a bus control circuit that determines the attributes of an upper-level bus. FIG. 4 is a block diagram showing the configuration of the main parts of the bus controller, FIG. 5 is a diagram showing the main parts of an address space map showing the allocation of address spaces within the processing module, and FIG. 6 is the bus control circuit. FIG. 3 is a diagram illustrating the operational concept of bus address conversion in which a bus address is converted from a bus attribute signal by using the following. In the figure, 10... master processing module, 11.21.
... Central processing unit, 12.22 ... Memory, 13.2
3...Lower bus. 14, 24... first bus controller, 15.25.
...Second bus controller, 16...Console control unit, 17...Bus control circuit, 19...Operation terminal, 2
0... Processing module, 20a... Standby processing module, 26... Line control unit, 27... Line group, 3
1... Upper bus ACT/SBY display flag storage section, 3
2... Lower bus side bus ACT/SBY display flag storage section, 33... DMA address register, 34...
Reception address register, 35...Bus controller self-address register, 36...Comparator, 37...Lower bus command reception display flag storage section, 40...First upper bus, 50...Second upper bus Bus, 43.53...AC
T/SBY display line, 14a... microprocessor,
14b... Upper bus interface control circuit, 14c
...lower bus interface control circuit, 14d...
Send/receive buffer memory. Arithmetic 4th time Goe 2 □□□ 3rd time 5th side 6th concave

Claims (1)

[Claims] 1. In a multiprocessor system in which a plurality of processing modules each including a central processing unit, memory, input/output device, line control controller, and bus controller commonly connected via a lower bus are connected to a common upper bus via the bus controller, Each processing module is equipped with a plurality of bus controllers, and the upper bus that commonly connects each processing module has a redundant bus configuration in which there are multiple buses corresponding to the bus controller. Performing bus control by determining the attributes of a plurality of upper-level buses under the control of a master processing module, and determining the access address attribute of the bus controller as seen from the central processing unit of each processing module based on the upper-level bus attributes from the master processing module. A bus control method with a redundant bus configuration characterized by: