WO2015029185A1 - Information processing system and information processing method - Google Patents

Information processing system and information processing method Download PDF

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Publication number
WO2015029185A1
WO2015029185A1 PCT/JP2013/073162 JP2013073162W WO2015029185A1 WO 2015029185 A1 WO2015029185 A1 WO 2015029185A1 JP 2013073162 W JP2013073162 W JP 2013073162W WO 2015029185 A1 WO2015029185 A1 WO 2015029185A1
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data
data storage
storage unit
processing unit
unit
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PCT/JP2013/073162
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French (fr)
Japanese (ja)
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石川　忠明
亮太 鴨志田
有田　節男
佳彦 石井
昌基 金田
健一 上遠野
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株式会社日立製作所
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Priority to PCT/JP2013/073162 priority Critical patent/WO2015029185A1/en
Publication of WO2015029185A1 publication Critical patent/WO2015029185A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0635—Configuration or reconfiguration of storage systems by changing the path, e.g. traffic rerouting, path reconfiguration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B17/00—Systems involving the use of models or simulators of said systems
    • G05B17/02—Systems involving the use of models or simulators of said systems electric
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B23/00—Testing or monitoring of control systems or parts thereof
    • G05B23/02—Electric testing or monitoring
    • G05B23/0205—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults
    • G05B23/0218—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterised by the fault detection method dealing with either existing or incipient faults
    • G05B23/0243—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterised by the fault detection method dealing with either existing or incipient faults model based detection method, e.g. first-principles knowledge model

Definitions

  • the present invention relates to an information processing system and an information processing method such as an operation support system for a plant that sequentially compares a prediction result obtained by analysis with an actual phenomenon to determine an event and predict its progress.
  • Patent Document 1 there is a driving support system that simulates the behavior of the entire plant by specifying specific conditions and compares the analytical solution with a sensor value to determine an event and sensor health.
  • Such a driving support system requires a large calculation capacity for analysis, and also requires a high processing capacity for matching of sensor data and analysis values input as needed.
  • the driving support system also requires real-time capability.
  • plant behavior analysis and sensor data matching are performed on independent processors, and large-scale data such as analysis results are often exchanged by file transfer via shared memory or HDD.
  • the object of the present invention is to provide a highly efficient transmission / reception of data between systems even when there are a plurality of systems each having a CPU, the processing performed in each system is different, and the time required for the processing is not constant. It is to realize an information processing system and an information processing method capable of performing the above.
  • the present invention is configured as follows.
  • each of the plurality of data processing units having different functions, the plurality of data storage units, and the plurality of data processing units writes data in the plurality of data storage units in a predetermined order.
  • An operation or a data reading operation is performed, and each of the plurality of data processing units is connected to a different data storage unit, and a data writing operation or a data reading operation of the plurality of data storage units is performed in parallel.
  • a switching processing unit that switches connection between the plurality of data processing units and the plurality of data storage units is provided.
  • each of the plurality of data processing units having different functions performs a data write operation or a data read operation on the plurality of data storage units in a predetermined order
  • Each of the data processing units is connected to the data storage units different from each other, and the plurality of data processing units and the plurality of data are performed in parallel so as to perform a write operation or a read operation on the data of the plurality of data storage units in parallel. Switches the connection with the storage unit.
  • An information processing system that has a plurality of systems each having a CPU, can perform data exchange between these systems even when the processing performed in each system is different from each other and the time required for the processing is not constant And an information processing method can be realized.
  • Example 1 of this invention It is a schematic block diagram which shows Example 1 of this invention. It is a figure for demonstrating the variable arrangement
  • FIG. 1 is a schematic configuration diagram of an information processing apparatus that is a driving support system (information processing system) according to a first embodiment of the present invention.
  • FIG. 2 is a diagram for explaining the arrangement of variables in the memory block according to the first embodiment.
  • FIG. 2 is a simplified representation of the configuration of the example shown in FIG.
  • the information processing apparatus roughly matches a data output processing system including a CPU 1 (first data processing unit), which is an analysis system in charge of analysis processing, with analysis results and sensor data, and performs evaluation.
  • a data input processing system including a CPU 2 (second data processing unit) which is a matching system to output, and a storage process including a storage device control unit 3 (third data processing unit) for storing the analysis result in the storage device 16 System.
  • Each processing system is driven by the same common clock (CLK) circuit 7, and the address / control signal buses 17 and 18 and the data buses 28-1 and 28-2 of each processing system are electrically disconnected or separated.
  • CLK common clock
  • the block 4 as the memory block 1 (first memory block) and the memory block 2 (first memory block) 2 blocks) and a block 6 which is a memory block 3 (third memory block) are connected.
  • the storage device control unit 3 is connected to the block 4, the block 5 and the block 6 through the gates 15-1, 15-2 and 15-3.
  • the sensor unit and the display unit are connected to the data bus 28-2, but these are omitted in FIG. 1 and shown in FIG.
  • the CPU 1 is connected to the memory 21, SSD 22, DPM 9, and switching circuit 8.
  • the CPU 2 is connected to the memory 19, SSD 20, DPM 9, and switching circuit 8. These memories 19 and 21, SSDs 20 and 22, and DPM 9 are used for the processing of the CPUs 1 and 2.
  • the gates 10-1, 10-2, 10-3, 14-1, 14-2, 14-3, 15-1, 15-2, and 15-3 have directionality in connection.
  • the analysis system CPU 1 can only write to the memory blocks 4, 5, and 6, and the matching system CPU 2 and the storage system controller 3 of the storage system can only read from the memory blocks 4, 5, and 6. ing.
  • These memory blocks 4, 5, and 6 are constituted by a single or a plurality of memory devices, but the memory blocks 4, 5, and 6 are assigned to the same address in the address space of each processing system.
  • gates 10-1, 10-2, 10-3 (first one-way gate, second one-way gate, third one-way gate), 14-1, 14-2, 14-3 (fourth unidirectional gate, fifth unidirectional gate, sixth unidirectional gate), 15-1, 15-2, 15-3 (seventh unidirectional gate, 8 unidirectional gates and ninth unidirectional gates) are controlled so that one of the memory blocks is electrically connected to each processing system, and a plurality of memory blocks 4, 5, 6 is never connected.
  • the CPU 2 of the matching system reads the data from the sensors installed on the analysis target such as plant piping and equipment via the sensor unit.
  • the CPU 2 determines whether or not analysis is necessary according to the sensor value from the sensor unit, and writes the condition data for analysis and the start signal in the DPM 9 when necessary.
  • the CPU 1 of the analysis system starts analysis according to the analysis start signal and the analysis condition data received via the DPM 9, and the analysis result is determined in advance for the first memory block 4 to which the CPU 1 of the analysis system is connected. Write in order (eg, time series).
  • the first memory block 4 is controlled by the gates 14-1 to 14-3 and 15-1 to 15-3 controlled by the switching circuit 8 from the CPU 2 of the matching system and the storage device controller 3 of the storage system.
  • the CPU 1 of the analysis system can write the first memory block 4 as a dedicated memory of the CPU 1 at a free timing.
  • the CPU 1 of the analysis system When the CPU 1 of the analysis system finishes writing to the first memory block 4 (end of one analysis process), it sends a switchable signal to the switching circuit 8, and the switching circuit 8 determines the state of each processing system and can switch. If it is determined that there is, the connection is switched and the first memory block 4 is electrically connected to the CPU 2 of the matching system. That is, in the switching circuit 8, when the data processing unit (CPU1, CPU2, storage device control unit 3) processes the next memory block, the data processing of the other data processing unit is completed for the memory block. Whether access to the memory block is permitted.
  • the data processing unit CPU1, CPU2, storage device control unit 3
  • the CPU 2 of the matching system uses the first memory block 4 as its own memory and reads data at any timing. Then, the CPU 2 compares the sensor data read sequentially with the data read from the first memory block 4 to determine the state.
  • the second memory block 5 is electrically connected to the CPU 1 of the analysis system, and the next analysis result is written.
  • the CPU 2 of the matching system sends a switchable signal to the switching circuit 8 when the data reading operation on the first memory block 4 is completed.
  • the CPU 1 of the analysis system also sends a switchable signal to the switching circuit 8 after the writing operation is completed.
  • the switching circuit 8 determines the state of the entire system, and if it is determined that the switching is possible, the connection is switched, and the first memory block 4 is electrically connected to the storage device control unit 3 of the storage system. Connecting. During the connection between the first memory block 4 and the storage device control unit 3, the storage device control unit 3 uses the first memory block 4 as its own memory, can be read at any timing, and stores the analysis result in the storage device 16. Process. At this time, the third memory block 6 is electrically connected to the CPU 1 of the analysis system, and the next analysis result writing process is performed as described above.
  • the second memory block 5 is electrically connected to the CPU 2 of the matching system, and the analysis result is read out from the second memory block 5 and compared with the sensor data as described above.
  • the storage device control unit 3 of the storage system finishes the analysis result storage processing on the first memory block 4, it sends a switchable signal to the switching circuit 8.
  • the CPU 1 of the analysis system and the CPU 2 of the matching system also send a switchable signal to the switching circuit 8 after the processing is completed.
  • the switching circuit 8 determines the state of each processing system based on the switching signal, and switches the connection when determining that switching is possible.
  • the CPU 1 of the analysis system is the first memory block 4 in which the content storage processing has been completed
  • the CPU 2 of the matching system is the third memory block 6, and the storage device controller 3 of the storage system is electrically connected to the second memory block 5. Connect to and perform each process.
  • the CPU 1 of the analysis system has the second memory block 5 in which the content storage processing has been completed
  • the CPU 2 of the matching system has the first memory block 4
  • the storage device controller 3 of the storage system has the third memory block 6. Connect each other in electrical signal and perform each processing. Thereafter, the same operation as described above is repeated.
  • FIG. 2 shows an example of variable arrangement in the memory.
  • the switch notation is changed to express the switching unit including the gates 10-1 to 10-3, 14-1 to 14-3, and 15-1 to 15-3 in an easy-to-understand manner.
  • FIG. 2 shows an example in which arrays T (0: n) and A (0: n) are declared in an address space indicating a memory block.
  • a memory block having new data is placed in a fixed memory space. Therefore, a variable or array area on the processing program is secured and secured in this memory space. By doing so, it becomes the same as the latest value is assigned to these variables and arrays at each switching, and there is no program execution process of reading and assignment, and the program execution speed can be increased.
  • a pressure sensor 24, a temperature sensor 25, a flow sensor 26, a valve opening / closing sensor 27, and a display unit 23 are connected to the CPU 2 of the matching system.
  • the display unit 23 displays the result of matching performed by the CPU 2 of the matching system.
  • the analysis result data stored in the storage device 16 is used for data analysis at a later date.
  • the analysis system CPU 1, the matching system CPU 2, the storage device control unit 3, and the plurality of memory blocks 4, 5, 6 each performing different processes.
  • a first data storage unit, a second data storage unit, and a third data storage unit) and the CPU 1 writes analysis data into the first memory block 4.
  • the CPU 2 reads the data stored in the first memory block 4 and performs the matching process.
  • the CPU 1 writes analysis data to the second memory block 5.
  • the CPU 1 performs analysis data write processing to the third memory block 6, and at the same time, the CPU 2 reads data stored in the second memory block 5 and performs matching processing. I do.
  • the storage device control unit 3 performs processing for storing the data stored in the first memory block 4 in the storage device 16.
  • the CPU 1 executes the writing of analysis data in the order of the first memory block 4, the second memory block 5, and the third memory block 6, and the CPU 2 follows the first memory block after the analysis data is written by the CPU 1.
  • the analysis data is read in the order of the second memory block 5 and the third memory block 6, and the storage device control unit 3 follows the end of reading the analysis data by the CPU 2, and then the first memory block 4 and the second memory block 5.
  • Analytical data is read in the order of the third memory block 6 and stored in the storage device 16.
  • the switching circuit 8 has another data processing unit for the memory block. It is determined whether or not the data processing is completed, and access to the memory block is permitted.
  • FIG. 3 is a schematic configuration diagram of an information processing apparatus which is a driving support system according to the second embodiment of the present invention.
  • the gates 10-1, 10-2, and 10-3 are unidirectional gates.
  • the data bus 28-1 and the memory blocks 4, 5 on the CPU 1 side of the analysis system are used.
  • 6 become bidirectional gates 12-1, 12-2, 12-3, and the address on the CPU 1 side of the analysis system and the READ signal from the control signal bus 18 are supplied to each memory block 4, 5, 6 Is different.
  • the CPU 1 side of the analysis system can perform not only the writing process but also the reading process for the memory blocks 4, 5, and 6.
  • the work area can be stored on the memory blocks 4, 5, and 6, and the final analysis is performed. It is not necessary to copy or move the result from another memory 21 or SSD 22.
  • the writing time can be omitted and the processing speed can be increased.
  • Example 2 since the other structure of Example 2 is the same as that of Example 1, illustration and the detailed description are abbreviate
  • Example 2 the same effect as Example 1 can be achieved.
  • FIG. 4 is a schematic block diagram of an information processing apparatus which is a driving support system (information processing system) according to the third embodiment of the present invention.
  • a driving support system information processing system
  • FIG. 4 only a schematic block diagram is shown for simplification of illustration.
  • FIG. 4 in the fourth embodiment of the present invention, there are three CPUs of the analysis system on the output side, CPU 2 of the matching system on the input side, and the storage device control unit 3, whereas the memory block is the first. There are four memory blocks, a second memory block 5, a third memory block 6, and a fourth memory block 13 (fourth data storage unit), and the number of memory blocks is one more than the number of processing systems.
  • the fourth memory block 13 is connected to the CPU 1 of the analysis system via the gate 10-4, and is connected to the CPU 2 of the matching system via the gate 14-4. Further, it is connected to the heat insulation device control unit 3 through the gate 15-4.
  • Example 3 the same effect as Example 1 can be produced.
  • the present invention is an information processing system that is an operation support system that assists in grasping the state of a plant for efficient operation of a large-scale plant such as a power plant such as nuclear power or thermal power, or a chemical plant such as petrochemical or for coping with an accident. Applicable to the device.
  • DESCRIPTION OF SYMBOLS 1 ... CPU of analysis system, 2 ... CPU of matching system, 3 ... Storage device control part, 4 ... 1st memory block 1, 5 ... 2nd memory block, 6 ... 3rd memory block, 7 ... CLK generating circuit, 8 ... switching circuit, 9 ... DPM (Dual Port Memory), 10-1, 10-2, 10-3, 10-4 ... single One-way gate, 12-1, 12-2, 12-3 ... Bidirectional gate, 13 ... Fourth memory block, 14-1, 14-2, 14-3, 14-4, 15-1 , 15-2, 15-3, 15-4 ... unidirectional gate, 16 ... storage device, 17, 18 ... address control bus, 19, 21 ... memory, 20, 22, ... -SSD, 23 ... display part, 24 ... pressure sensor, 25 ... temperature Capacitors, 26 ... flow sensor 27 ... valve opening and closing sensor, 28-1, 28-2 ... data bus

Abstract

　A CPU (1) writes analysis data to, in sequence, a first memory block (4), a second memory block (5), and a third memory block (6). After completion of the analysis data writing by the CPU (1), a CPU (2) performs an analysis data read process on, in sequence, the first memory block (4), the second memory block (5), and the third memory block (6). After completion of the analysis data read by the CPU (2), a preservation device control unit (3) reads the analysis data of, in sequence, the first memory block (4), the second memory block (5), and the third memory block (6), and performs a storage process to a storage device (16). Different processes are sequentially performed on the plurality of memory blocks (4, 5, 6) by the CPU (1), the CPU (2), and the preservation device control unit (3), and processing operations are executed in parallel on each of the memory blocks (4, 5, 6).

Description

情報処理システムおよび情報処理方法Information processing system and information processing method
　本発明は、解析による予測結果を実現象と逐次比較し、事象の判定とその進展予測を行うプラントの運転支援システムなどの情報処理システムおよび情報処理方法に関する。 The present invention relates to an information processing system and an information processing method such as an operation support system for a plant that sequentially compares a prediction result obtained by analysis with an actual phenomenon to determine an event and predict its progress.
　原子力や火力などの発電プラント、あるいは石油化学などの化学プラントなどの大規模プラントの効率的運転あるいは事故時対処のためにプラント状態把握を補助する運転支援システムがある。この運転支援システムにおいて、正確な状態把握には数多くのセンサが必要であるが、プラント全体にセンサを配置することは費用や設置可能場所の問題から難しい。 There is an operation support system that assists in grasping the state of a plant for efficient operation of a large-scale plant such as a power plant such as nuclear power or thermal power, or a chemical plant such as petrochemical, or for dealing with an accident. In this driving support system, a large number of sensors are required for accurate grasping of the state, but it is difficult to arrange the sensors in the entire plant due to problems of cost and installation location.
　また、センサ故障や事故発生時など、センサデータそのものの信頼性が問題となる場合もある。そのため、特定の条件を規定してプラント全体挙動をシミュレーションし、その解析解をセンサ値と比較することで事象判断やセンサ健全性の判定を行う運転支援システムがある（特許文献１）。 Also, the reliability of the sensor data itself may be a problem, such as when a sensor failure or accident occurs. For this reason, there is a driving support system that simulates the behavior of the entire plant by specifying specific conditions and compares the analytical solution with a sensor value to determine an event and sensor health (Patent Document 1).
　このような運転支援システムでは、解析に大きな計算能力が必要であり、かつ、随時入力されるセンサデータと解析値とのマッチングにも高い処理能力が必要である。特に、運転支援の必要性が増すと思われる事故時などの異常時には、プラント状態の変化も激しく、早い対応が要求されるため、運転支援システムにはリアルタイム性も必要とされる。 Such a driving support system requires a large calculation capacity for analysis, and also requires a high processing capacity for matching of sensor data and analysis values input as needed. In particular, in the event of an abnormality such as an accident where the need for driving assistance is likely to increase, the plant state changes drastically and prompt response is required, so the driving support system also requires real-time capability.
　従って、プラント挙動解析と、センサデータ・マッチングとは各々独立したプロセッサー上で行い、解析結果等の大規模データのやり取りは共有メモリやＨＤＤを介したファイル転送で行うことが多い。 Therefore, plant behavior analysis and sensor data matching are performed on independent processors, and large-scale data such as analysis results are often exchanged by file transfer via shared memory or HDD.
　しかし、プラント挙動解析及びセンサデータ・マッチングの双方で取り扱うデータ量は大きく、通常のＤＰＭ（デュアルポートメモリ）等による共有メモリシステムでは、入力及び出力の双方からのアクセスを調節する為のｗａｉｔ時間（アクセス待機時間）が大きくなってしまう。 However, the amount of data handled in both plant behavior analysis and sensor data matching is large, and in a shared memory system such as a normal DPM (dual port memory), a wait time for adjusting access from both input and output ( (Access waiting time) becomes longer.
　これは、ＨＤＤやＳＳＤ（Solid State Drive）といった記憶装置を利用して、ファイルとしてデータのやり取りする場合でも一般的には同様である。 This is generally the same even when data is exchanged as a file using a storage device such as an HDD or SSD (Solid State Drive).
　そこで、特許文献２に示されるような専用の演算装置においては、専用演算器とメモリ部（特許文献２中ではデータ記憶部）を二つずつ設け、各々の演算器が異なるメモリにアクセスするように制御部でセレクト信号やメモリのリード、ライト信号を同時実行する様に制御し、待ち時間を減らす、といった方法が考えられている。 Therefore, in a dedicated arithmetic unit as shown in Patent Document 2, two dedicated arithmetic units and two memory units (data storage units in Patent Document 2) are provided so that each arithmetic unit accesses a different memory. In addition, a method is conceived in which the control unit controls the selection signal, the memory read, and the write signal to be executed simultaneously to reduce the waiting time.
特開２００６－３４４００４号公報JP 2006-344004 A 特開２０１２－２２５００号公報JP 2012-22500 A
　しかしながら、上記特許文献２に記載された方法では、各々の演算器の演算に要する時間がほぼ等しく定まっていれば、異なる演算をする演算器間でも有効であるが、演算に要する時間が一定でない場合は、調停用の信号が別途必要であり、そのための処理時間も必要となってしまい、データ処理時間の短縮が困難であった。 However, in the method described in Patent Document 2, it is effective even between the arithmetic units performing different calculations if the time required for the calculation of each arithmetic unit is determined to be approximately equal, but the time required for the calculation is not constant. In this case, an arbitration signal is separately required, and a processing time for that is required, and it is difficult to shorten the data processing time.
　本発明の目的は、それぞれＣＰＵを有するシステムが複数あり、各システムで行う処理が互いに異なり、処理に要する時間も一定でない場合であっても、それらシステム間でデータの授受を高効率に行うことが可能な情報処理システムおよび情報処理方法を実現することである。 The object of the present invention is to provide a highly efficient transmission / reception of data between systems even when there are a plurality of systems each having a CPU, the processing performed in each system is different, and the time required for the processing is not constant. It is to realize an information processing system and an information processing method capable of performing the above.
　上記目的を達成するため、本発明は次のように構成される。 In order to achieve the above object, the present invention is configured as follows.
　本発明の情報処理システムは、互いに機能が異なる複数のデータ処理部と、複数のデータ記憶部と、上記複数のデータ処理部のそれぞれが、上記複数のデータ記憶部に所定の順序で、データ書き込み動作又はデータ読み込み動作を行い、かつ、上記複数のデータ処理部のそれぞれが、互いに異なる上記データ記憶部に接続され、上記複数のデータ記憶部のデータへの書き込み動作又は読み込み動作を並列して行うように上記複数のデータ処理部と上記複数のデータ記憶部との接続を切り替える切替処理部とを備える。 According to the information processing system of the present invention, each of the plurality of data processing units having different functions, the plurality of data storage units, and the plurality of data processing units writes data in the plurality of data storage units in a predetermined order. An operation or a data reading operation is performed, and each of the plurality of data processing units is connected to a different data storage unit, and a data writing operation or a data reading operation of the plurality of data storage units is performed in parallel. As described above, a switching processing unit that switches connection between the plurality of data processing units and the plurality of data storage units is provided.
　また、本発明の情報処理方法は、互いに機能が異なる複数のデータ処理部のそれぞれが、上記複数のデータ記憶部に所定の順序で、データ書き込み動作又はデータ読み込み動作を行い、かつ、上記複数のデータ処理部のそれぞれが、互いに異なる上記データ記憶部に接続され、上記複数のデータ記憶部のデータへの書き込み動作又は読み込み動作を並列して行うように上記複数のデータ処理部と上記複数のデータ記憶部との接続を切り替える。 Further, according to the information processing method of the present invention, each of the plurality of data processing units having different functions performs a data write operation or a data read operation on the plurality of data storage units in a predetermined order, and Each of the data processing units is connected to the data storage units different from each other, and the plurality of data processing units and the plurality of data are performed in parallel so as to perform a write operation or a read operation on the data of the plurality of data storage units in parallel. Switches the connection with the storage unit.
　それぞれＣＰＵを有するシステムが複数あり、各システムで行う処理が互いに異なり、処理に要する時間も一定でない場合であっても、それらシステム間でデータの授受を高効率に行うことが可能な情報処理システムおよび情報処理方法を実現することができる。 An information processing system that has a plurality of systems each having a CPU, can perform data exchange between these systems even when the processing performed in each system is different from each other and the time required for the processing is not constant And an information processing method can be realized.
本発明の実施例１を示す概略構成図である。It is a schematic block diagram which shows Example 1 of this invention. 本発明の実施例１におけるメモリブロック内の変数並びを説明するための図であり、図１の例の構成を簡素化して表現した図である。It is a figure for demonstrating the variable arrangement | sequence in the memory block in Example 1 of this invention, and is the figure which simplified and expressed the structure of the example of FIG. 本発明の実施例２を示す概略構成図である。It is a schematic block diagram which shows Example 2 of this invention. 本発明の実施例３を示す概略ブロック図である。It is a schematic block diagram which shows Example 3 of this invention.
　以下、本発明の実施形態について、添付図面を参照して説明する。 Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
　（実施例１）
　図１は、本発明の実施例１における運転支援システム（情報処理システム）である情報処理装置の概略構成図であり、図２は、実施例１のメモリブロック内の変数並び説明のため、図１に示した例の構成を簡素化して表現した図である。 Example 1
FIG. 1 is a schematic configuration diagram of an information processing apparatus that is a driving support system (information processing system) according to a first embodiment of the present invention. FIG. 2 is a diagram for explaining the arrangement of variables in the memory block according to the first embodiment. FIG. 2 is a simplified representation of the configuration of the example shown in FIG.
　図１において、情報処理装置は、大まかに、解析処理を担当する解析システムであるＣＰＵ１（第１データ処理部）を備えたデータ出力処理システムと、解析結果とセンサデータのマッチングを行い、評価を出力するマッチングシステムであるＣＰＵ２（第２データ処理部）備えたデータ入力処理システムと、解析結果を記憶装置１６に保存する為の保存装置制御部３（第３データ処理部）を備えた保存処理システムとを備えている。 In FIG. 1, the information processing apparatus roughly matches a data output processing system including a CPU 1 (first data processing unit), which is an analysis system in charge of analysis processing, with analysis results and sensor data, and performs evaluation. A data input processing system including a CPU 2 (second data processing unit) which is a matching system to output, and a storage process including a storage device control unit 3 (third data processing unit) for storing the analysis result in the storage device 16 System.
　各処理システムは共通する同一のクロック（ＣＬＫ）回路７で駆動されており、それぞれの処理システムのアドレス・制御信号バス１７、１８、データバス２８－１、２８－２には電気信号的切り離しあるいは接続を行うゲート１０－１、１０－２、１０－３、１４－１、１４－２、１４－３を介して、メモリブロック１（第１メモリブロック）であるブロック４、メモリブロック２（第２メモリブロック）であるブロック５、メモリブロック３（第３メモリブロック）であるブロック６が接続されている。 Each processing system is driven by the same common clock (CLK) circuit 7, and the address / control signal buses 17 and 18 and the data buses 28-1 and 28-2 of each processing system are electrically disconnected or separated. Through the gates 10-1, 10-2, 10-3, 14-1, 14-2, and 14-3 for connection, the block 4 as the memory block 1 (first memory block) and the memory block 2 (first memory block) 2 blocks) and a block 6 which is a memory block 3 (third memory block) are connected.
　また、保存装置制御部３は、ゲート１５－１、１５－２、１５－３を介して、ブロック４、ブロック５、ブロック６に接続されている。 Further, the storage device control unit 3 is connected to the block 4, the block 5 and the block 6 through the gates 15-1, 15-2 and 15-3.
　データバス２８－２にはセンサ部、表示部が接続されているが、図１ではこれらを省略し、図２に示すこととする。 The sensor unit and the display unit are connected to the data bus 28-2, but these are omitted in FIG. 1 and shown in FIG.
　また、ＣＰＵ１は、メモリ２１、ＳＳＤ２２、ＤＰＭ９、切替回路８に接続されている。また、ＣＰＵ２は、メモリ１９、ＳＳＤ２０、ＤＰＭ９、切替回路８に接続されている。これらメモリ１９、２１、ＳＳＤ２０、２２、ＤＰＭ９は、ＣＰＵ１、２の処理に際して使用される。 The CPU 1 is connected to the memory 21, SSD 22, DPM 9, and switching circuit 8. The CPU 2 is connected to the memory 19, SSD 20, DPM 9, and switching circuit 8. These memories 19 and 21, SSDs 20 and 22, and DPM 9 are used for the processing of the CPUs 1 and 2.
　ゲート１０－１、１０－２、１０－３、１４－１、１４－２、１４－３、１５－１、１５－２、１５－３は接続に方向性を持っており、本例においては、解析システムのＣＰＵ１からはメモリブロック４、５、６に対して書き込みのみ、マッチングシステムのＣＰＵ２及び保存システムの保存装置制御部３からはメモリブロック４、５、６からの読み出しだけが可能となっている。 The gates 10-1, 10-2, 10-3, 14-1, 14-2, 14-3, 15-1, 15-2, and 15-3 have directionality in connection. The analysis system CPU 1 can only write to the memory blocks 4, 5, and 6, and the matching system CPU 2 and the storage system controller 3 of the storage system can only read from the memory blocks 4, 5, and 6. ing.
　これらメモリブロック４、５、６は、単体あるいは複数のメモリデバイスで構成されるが、メモリブロック４、５、６同士は、それぞれの処理システムのアドレス空間において同じアドレスに割り当てられている。 These memory blocks 4, 5, and 6 are constituted by a single or a plurality of memory devices, but the memory blocks 4, 5, and 6 are assigned to the same address in the address space of each processing system.
　ただし、切替回路（切替処理部）８によりゲート１０－１、１０－２、１０－３（第１の一方向ゲート、第２の一方向ゲート、第３の一方向ゲート）、１４－１、１４－２、１４－３（第４の一方向ゲート、第５の一方向ゲート、第６の一方向ゲート）、１５－１、１５－２、１５－３（第７の一方向ゲート、第８の一方向ゲート、第９の一方向ゲート）が制御されることで、各処理システムに電気信号的に接続するのはいずれか一つのメモリブロックであり、同時に複数のメモリブロック４、５、６が接続されることはない。 However, gates 10-1, 10-2, 10-3 (first one-way gate, second one-way gate, third one-way gate), 14-1, 14-2, 14-3 (fourth unidirectional gate, fifth unidirectional gate, sixth unidirectional gate), 15-1, 15-2, 15-3 (seventh unidirectional gate, 8 unidirectional gates and ninth unidirectional gates) are controlled so that one of the memory blocks is electrically connected to each processing system, and a plurality of memory blocks 4, 5, 6 is never connected.
　図１において、ディスプレイやキーボード、ＬＡＮといった一般的な入出力部は割愛して表記している。以下動作手順を説明する。 In FIG. 1, general input / output units such as a display, a keyboard, and a LAN are omitted. The operation procedure will be described below.
　マッチングシステムのＣＰＵ２には、プラント配管や機器等の解析対象に設置されたセンサからのデータを、センサ部を介して読み込む。ＣＰＵ２は、センサ部からのセンサ値に従って、解析が必要か否かを判断し、必要が生じた場合、解析用条件データと開始信号とをＤＰＭ９に書き込む。 The CPU 2 of the matching system reads the data from the sensors installed on the analysis target such as plant piping and equipment via the sensor unit. The CPU 2 determines whether or not analysis is necessary according to the sensor value from the sensor unit, and writes the condition data for analysis and the start signal in the DPM 9 when necessary.
　解析システムのＣＰＵ１は、ＤＰＭ９を介して受け取った解析開始信号と解析用条件データとに従って解析を開始し、解析結果を解析システムのＣＰＵ１が接続している第１メモリブロック４に対し、あらかじめ決めた順序（例えば、時系列）で書き込む。 The CPU 1 of the analysis system starts analysis according to the analysis start signal and the analysis condition data received via the DPM 9, and the analysis result is determined in advance for the first memory block 4 to which the CPU 1 of the analysis system is connected. Write in order (eg, time series).
　データ書き込み中は、第１メモリブロック４は、マッチングシステムのＣＰＵ２及び保存システムの保存装置制御部３から切替回路８により制御されたゲート１４－１～１４－３、１５－１～１５－３により、電気信号的に切り離されており、解析システムのＣＰＵ１は第１メモリブロック４をＣＰＵ１自身の専用のメモリとして自由なタイミングで書き込むことができる。 During data writing, the first memory block 4 is controlled by the gates 14-1 to 14-3 and 15-1 to 15-3 controlled by the switching circuit 8 from the CPU 2 of the matching system and the storage device controller 3 of the storage system. The CPU 1 of the analysis system can write the first memory block 4 as a dedicated memory of the CPU 1 at a free timing.
　解析システムのＣＰＵ１は、第１メモリブロック４に対する書き込みを終了すると（一解析処理の終了）、切替回路８に切り替え可能信号を送り、切替回路８が各処理システムの状態を判断し、切替可能であると判断したら、接続の切り替えを行い、第１メモリブロック４はマッチングシステムのＣＰＵ２と電気信号的に接続される。つまり、切替回路８は、データ処理部（ＣＰＵ１、ＣＰＵ２、保存装置制御部３）が、次のメモリブロックについて処理を行うに際して、そのメモリブロックに対して他のデータ処理部のデータ処理が終了したか否かを判断して、メモリブロックへのアクセスを許可している。 When the CPU 1 of the analysis system finishes writing to the first memory block 4 (end of one analysis process), it sends a switchable signal to the switching circuit 8, and the switching circuit 8 determines the state of each processing system and can switch. If it is determined that there is, the connection is switched and the first memory block 4 is electrically connected to the CPU 2 of the matching system. That is, in the switching circuit 8, when the data processing unit (CPU1, CPU2, storage device control unit 3) processes the next memory block, the data processing of the other data processing unit is completed for the memory block. Whether access to the memory block is permitted.
　第１メモリ４との接続中、マッチングシステムのＣＰＵ２は第１メモリブロック４を自分のメモリとし、自由なタイミングでデータを読出す。そして、ＣＰＵ２は逐次読み込むセンサデータと第１メモリブロック４から読み込んだデータとを比較し、状態判断を行う。 During the connection with the first memory 4, the CPU 2 of the matching system uses the first memory block 4 as its own memory and reads data at any timing. Then, the CPU 2 compares the sensor data read sequentially with the data read from the first memory block 4 to determine the state.
　読出し方向にのみ第１メモリブロック４とＣＰＵ２とを接続することで、マッチング処理プログラムにバグがあり、異常動作しても、続く処理に引き継ぐまでに、第１メモリブロック４中のデータを書き換えてしまう心配がない。 By connecting the first memory block 4 and the CPU 2 only in the reading direction, there is a bug in the matching processing program, and even if an abnormal operation occurs, the data in the first memory block 4 can be rewritten before taking over to the subsequent processing. There is no worry about it.
　この時、解析システムのＣＰＵ１には第２メモリブロック５が電気的に接続され、次の解析結果の書き込み処理を行う。 At this time, the second memory block 5 is electrically connected to the CPU 1 of the analysis system, and the next analysis result is written.
　マッチングシステムのＣＰＵ２は第１メモリブロック４上のデータ読みだし作業を終了すると、切替回路８に切り替え可能信号を送る。同様に、解析システムのＣＰＵ１も書き込み作業終了後に切替回路８に切り替え可能信号を送る。 The CPU 2 of the matching system sends a switchable signal to the switching circuit 8 when the data reading operation on the first memory block 4 is completed. Similarly, the CPU 1 of the analysis system also sends a switchable signal to the switching circuit 8 after the writing operation is completed.
　ＣＰＵ１とＣＰＵ２との処理に違いがあるので、書き込み作業終了タイミングと読みだし作業終了タイミングとが同じとなるとは限らない。 Since there is a difference in processing between the CPU 1 and the CPU 2, the writing work end timing and the reading work end timing are not always the same.
　前述と同様に、切替回路８は全システムの状態を判断し、切替可能であると判断したら、接続の切り替えを行い、第１メモリブロック４は保存システムの保存装置制御部３と電気信号的に接続する。第１メモリブロック４と保存装置制御部３との接続中、保存装置制御部３は第１メモリブロック４を自身の占有メモリとし、自由なタイミングで読出しでき、解析結果を記憶装置１６に格納する処理を行う。この時、解析システムのＣＰＵ１には第３メモリブロック６が電気的に接続され、前記と同様に次の解析結果書き込み処理を行う。 As described above, the switching circuit 8 determines the state of the entire system, and if it is determined that the switching is possible, the connection is switched, and the first memory block 4 is electrically connected to the storage device control unit 3 of the storage system. Connecting. During the connection between the first memory block 4 and the storage device control unit 3, the storage device control unit 3 uses the first memory block 4 as its own memory, can be read at any timing, and stores the analysis result in the storage device 16. Process. At this time, the third memory block 6 is electrically connected to the CPU 1 of the analysis system, and the next analysis result writing process is performed as described above.
　また、マッチングシステムのＣＰＵ２には第２メモリブロック５が電気的に接続され、前述と同様に、第２メモリブロック５から解析結果を読み出し、センサデータとの比較処理を行う。保存存システムの保存装置制御部３が第１メモリブロック４上の解析結果保存処理を終了すると、切替回路８に切り替え可能信号を送る。 Further, the second memory block 5 is electrically connected to the CPU 2 of the matching system, and the analysis result is read out from the second memory block 5 and compared with the sensor data as described above. When the storage device control unit 3 of the storage system finishes the analysis result storage processing on the first memory block 4, it sends a switchable signal to the switching circuit 8.
　同様に、解析システムのＣＰＵ１、マッチングシステムのＣＰＵ２も処理終了後に切替回路８に対し、切替可能信号を送る。切替回路８は、切替信号により各処理システムの状態を判断し、切替可能であると判断したら、接続の切り替えを行う。解析システムのＣＰＵ１は内容の保存処理が終了した第１メモリブロック４と、マッチングシステムのＣＰＵ２は第３のメモリブロック６と、保存システムの保存装置制御部３は第２メモリブロック５と電気信号的に接続し、それぞれの処理を行う。 Similarly, the CPU 1 of the analysis system and the CPU 2 of the matching system also send a switchable signal to the switching circuit 8 after the processing is completed. The switching circuit 8 determines the state of each processing system based on the switching signal, and switches the connection when determining that switching is possible. The CPU 1 of the analysis system is the first memory block 4 in which the content storage processing has been completed, the CPU 2 of the matching system is the third memory block 6, and the storage device controller 3 of the storage system is electrically connected to the second memory block 5. Connect to and perform each process.
　同様に、解析システムのＣＰＵ１は内容の保存処理が終了した第２メモリブロック５と、マッチングシステムのＣＰＵ２は第１のメモリブロック４と、保存システムの保存装置制御部３は第３メモリブロック６と電気信号的に接続し、それぞれの処理を行う。以降、前述と同様な動作を繰り返す。 Similarly, the CPU 1 of the analysis system has the second memory block 5 in which the content storage processing has been completed, the CPU 2 of the matching system has the first memory block 4, and the storage device controller 3 of the storage system has the third memory block 6. Connect each other in electrical signal and perform each processing. Thereafter, the same operation as described above is repeated.
　１つの処理システムがメモリブロック４、５、６のうちのいずれか１つと接続している間は、他のシステムは、そのメモリブロックにアクセスできないため、その処理システムは接続しているメモリブロックに対し、その処理システムが許す最大限のアクセス速度を発揮できる。また、その間、他のシステムはそれぞれ接続されたメモリブロックに対し、処理を行っているので作業の並列化が図られ、効率的である。 While one processing system is connected to any one of the memory blocks 4, 5, 6, the other system cannot access the memory block, so that the processing system is connected to the connected memory block. On the other hand, the maximum access speed allowed by the processing system can be exhibited. In the meantime, the other systems are processing the connected memory blocks, so that the work is parallelized and efficient.
　図２は、メモリ内での変数配置の例を示している。この図２ではゲート１０－１～１０－３、１４－１～１４－３、１５－１～１５－３からなる切替部をわかりやすく表現する為にスイッチ表記に変更している。 FIG. 2 shows an example of variable arrangement in the memory. In FIG. 2, the switch notation is changed to express the switching unit including the gates 10-1 to 10-3, 14-1 to 14-3, and 15-1 to 15-3 in an easy-to-understand manner.
　ここで、各メモリブロック４、５、６を示すアドレスに、固定して変数や配列の領域を確保することで、各々のメモリブロック４、５、６上には、同じ変数や配列が存在し、メモリブロック４、５、６ごとに解析された時間及び付随する条件が異なる解析結果が値として入る。 Here, by fixing the area of the variable or the array at the address indicating each memory block 4, 5, or 6, the same variable or array exists on each of the memory blocks 4, 5, or 6. The analysis results differing in time and accompanying conditions analyzed for each of the memory blocks 4, 5, and 6 are entered as values.
　図２においては、例としてメモリブロックを示すアドレス空間に配列Ｔ（０：ｎ）、Ａ（０：ｎ）を宣言した場合を示している。各システムにおいては、メモリブロックの切替ごとに、それぞれ固定したメモリ空間に新たなデータを持ったメモリブロックが配置されるため、このメモリ空間に処理プログラム上の変数や配列の領域を固定確保しておくことで、切替ごとに最新の値がそれら変数や配列に代入されるのと同じことになり、読み込みと代入というプログラム実行上のプロセスもなくなり、プログラム実行の高速化も図れる。 FIG. 2 shows an example in which arrays T (0: n) and A (0: n) are declared in an address space indicating a memory block. In each system, each time a memory block is switched, a memory block having new data is placed in a fixed memory space. Therefore, a variable or array area on the processing program is secured and secured in this memory space. By doing so, it becomes the same as the latest value is assigned to these variables and arrays at each switching, and there is no program execution process of reading and assignment, and the program execution speed can be increased.
　図２において、マチングシステムのＣＰＵ２には、圧力センサ２４、温度センサ２５、流量センサ２６、バルブ開閉センサ２７、表示部２３が接続される。この表示部２３に、マッチングシステムのＣＰＵ２がマッチングを行った結果が表示される。 2, a pressure sensor 24, a temperature sensor 25, a flow sensor 26, a valve opening / closing sensor 27, and a display unit 23 are connected to the CPU 2 of the matching system. The display unit 23 displays the result of matching performed by the CPU 2 of the matching system.
　また、記憶装置１６に記憶された解析結果データは、後日のデータ解析に使用される。 The analysis result data stored in the storage device 16 is used for data analysis at a later date.
　以上のように、本発明の実施例１によれば、それぞれ異なる処理を行う、解析システムのＣＰＵ１と、マッチングシステムのＣＰＵ２と、保存装置制御部３と、複数のメモリブロック４、５、６（第１データ記憶部、第２データ記憶部、第３データ記憶部）とを備え、ＣＰＵ１が第１メモリブロック４に解析データの書き込み処理を行う。ＣＰＵ１の第１メモリブロック４への書き込み処理が終了すると、ＣＰＵ２が第１メモリブロック４に格納されたデータを読み込んで、マッチング処理を行う。この間、ＣＰＵ１は第２メモリブロック５に解析データの書き込み処理を行う。ＣＰＵ１、２の処理が終了すると、ＣＰＵ１が、第３メモリブロック６に解析データの書き込み処理を行い、それと並行して、ＣＰＵ２が、第２メモリブロック５に格納されたデータを読み込んで、マッチング処理を行う。この間、保存装置制御部３は、第１メモリブロック４に格納されたデータの記憶装置１６への格納処理を行う。 As described above, according to the first embodiment of the present invention, the analysis system CPU 1, the matching system CPU 2, the storage device control unit 3, and the plurality of memory blocks 4, 5, 6 (each performing different processes). A first data storage unit, a second data storage unit, and a third data storage unit), and the CPU 1 writes analysis data into the first memory block 4. When the writing process to the first memory block 4 by the CPU 1 is completed, the CPU 2 reads the data stored in the first memory block 4 and performs the matching process. During this time, the CPU 1 writes analysis data to the second memory block 5. When the processing of the CPUs 1 and 2 is completed, the CPU 1 performs analysis data write processing to the third memory block 6, and at the same time, the CPU 2 reads data stored in the second memory block 5 and performs matching processing. I do. During this time, the storage device control unit 3 performs processing for storing the data stored in the first memory block 4 in the storage device 16.
　つまり、ＣＰＵ１は、解析データの書き込みを、第１メモリブロック４、第２メモリブロック５、第３メモリブロック６の順に実行し、ＣＰＵ２は、ＣＰＵ１の解析データ書き込み終了に続いて、第１メモリブロック４、第２メモリブロック５、第３メモリブロック６の順に解析データの読み込み処理を行い、保存装置制御部３は、ＣＰＵ２の解析データ読み込み終了に続いて、第１メモリブロック４、第２メモリブロック５、第３メモリブロック６の順に解析データを読み込み、記憶装置１６への格納処理を行う。 That is, the CPU 1 executes the writing of analysis data in the order of the first memory block 4, the second memory block 5, and the third memory block 6, and the CPU 2 follows the first memory block after the analysis data is written by the CPU 1. 4, the analysis data is read in the order of the second memory block 5 and the third memory block 6, and the storage device control unit 3 follows the end of reading the analysis data by the CPU 2, and then the first memory block 4 and the second memory block 5. Analytical data is read in the order of the third memory block 6 and stored in the storage device 16.
　したがって、ＣＰＵ１、ＣＰＵ２及び保存装置制御部３により、複数のメモリブロック４、５、６に対して、異なる処理が順次行われと共に、各メモリブロック４、５、６は、並行して処理動作が実行される。 Therefore, different processing is sequentially performed on the plurality of memory blocks 4, 5, 6 by the CPU 1, CPU 2, and the storage device control unit 3, and each memory block 4, 5, 6 performs processing operations in parallel. Executed.
　この場合、切替回路８は、互いに機能が異なるデータ処理部（ＣＰＵ１、ＣＰＵ２、保存装置制御部３）が、次のメモリブロックについて処理を行うに際して、そのメモリブロックに対して他のデータ処理部のデータ処理が終了したか否かを判断して、メモリブロックへのアクセスを許可している。 In this case, when the data processing units (CPU1, CPU2, and storage device control unit 3) having different functions perform processing on the next memory block, the switching circuit 8 has another data processing unit for the memory block. It is determined whether or not the data processing is completed, and access to the memory block is permitted.
　よって、複数の処理部（演算器）の演算に行う処理が互いに異なり、処理に要する時間も一定でない場合であっても、それらシステム間でデータの授受を高効率に行うことが可能な情報処理システムおよび情報処理方法を実現することができる。 Therefore, even when the processing performed by the plurality of processing units (arithmetic units) is different from each other and the time required for the processing is not constant, the information processing that can exchange data between these systems with high efficiency. A system and an information processing method can be realized.
　（実施例２）
　次に、本発明の実施例２について説明する。 (Example 2)
Next, a second embodiment of the present invention will be described.
　図３は、本発明の実施例２による運転支援システムである情報処理装置の概略構成図である。実施例１では、ゲート１０－１、１０－２、１０－３は単一方向ゲートであったが、実施例２においては、解析システムのＣＰＵ１側のデータバス２８－１とメモリブロック４、５、６との接続が、双方向ゲート１２－１、１２－２、１２－３となり、解析システムのＣＰＵ１側のアドレス及び制御信号バス１８からのＲＥＡＤ信号が各メモリブロック４、５、６に供給される点が異なっている。 FIG. 3 is a schematic configuration diagram of an information processing apparatus which is a driving support system according to the second embodiment of the present invention. In the first embodiment, the gates 10-1, 10-2, and 10-3 are unidirectional gates. However, in the second embodiment, the data bus 28-1 and the memory blocks 4, 5 on the CPU 1 side of the analysis system are used. , 6 become bidirectional gates 12-1, 12-2, 12-3, and the address on the CPU 1 side of the analysis system and the READ signal from the control signal bus 18 are supplied to each memory block 4, 5, 6 Is different.
　これにより、解析システムのＣＰＵ１側はメモリブロック４、５、６に対し、書き出し処理だけでなく、読出し処理も可能となる。 Thus, the CPU 1 side of the analysis system can perform not only the writing process but also the reading process for the memory blocks 4, 5, and 6.
　従って、解析システムにおける解析処理が収束計算の様に、読出し、計算、書き出しの繰り返しで行われるものであっても作業領域をメモリブロック４、５、６上に取ることが可能であり、最終解析結果を他のメモリ２１、ＳＳＤ２２からコピーあるいは移動する必要がなくなる。 Therefore, even if the analysis processing in the analysis system is performed by repeated reading, calculation, and writing like the convergence calculation, the work area can be stored on the memory blocks 4, 5, and 6, and the final analysis is performed. It is not necessary to copy or move the result from another memory 21 or SSD 22.
　本発明の実施例２は、データ処理において、解析結果を次回の解析に用いないようなアルゴリズムを採用している場合には、書き出しの時間を省略でき、処理の高速化を図ることができる。 In the second embodiment of the present invention, when an algorithm that does not use the analysis result for the next analysis is employed in the data processing, the writing time can be omitted and the processing speed can be increased.
　なお、実施例２のその他の構成は、実施例１と同様であるので、図示及びその詳細な説明は省略する。 In addition, since the other structure of Example 2 is the same as that of Example 1, illustration and the detailed description are abbreviate | omitted.
　また、実施例２においても、実施例１と同様な効果を奏することができる。 Also in Example 2, the same effect as Example 1 can be achieved.
　（実施例３）
　次に、本発明の実施例３について説明する。 Example 3
Next, Embodiment 3 of the present invention will be described.
　図４は、本発明の実施例３による運転支援システム（情報処理システム）である情報処理装置の概略ブロック図である。本実施例４では、図示の簡略化のために、概略ブロック図のみ示している。 FIG. 4 is a schematic block diagram of an information processing apparatus which is a driving support system (information processing system) according to the third embodiment of the present invention. In the fourth embodiment, only a schematic block diagram is shown for simplification of illustration.
　図４において、本発明の実施例４では、出力側となる解析システムのＣＰＵＩ、入力側となるマッチングシステムのＣＰＵ２、保存装置制御部３の３つであるのに対し、メモリブロックは、第１メモリブロック４、第２メモリブロック５、第３メモリブロック６、第４メモリブロック１３（第４データ記憶部）の４つであり、メモリブロックの数が処理システムの数より１つ多い。 In FIG. 4, in the fourth embodiment of the present invention, there are three CPUs of the analysis system on the output side, CPU 2 of the matching system on the input side, and the storage device control unit 3, whereas the memory block is the first. There are four memory blocks, a second memory block 5, a third memory block 6, and a fourth memory block 13 (fourth data storage unit), and the number of memory blocks is one more than the number of processing systems.
　従って、ＣＰＵＩ、ＣＰＵ２、保存装置制御部３にメモリブロックを１個ずつ接続した場合には、どの処理部（ＣＰＵＩ、ＣＰＵ２、保存装置制御部３）にも接続されない、余剰のメモリブロックが１つ生じる。この余剰メモリブロックは、システムとしての予備となり、メモリブロック故障の際に代替として接続するという使い方や、何らかの事象により、いずれかの処理システムにおける処理のみが遅れた場合、このメモリブロックを投入することで１回分は他の処理を進め、結果をためておくことができるバッファメモリとしての使い方ができる。 Therefore, when one memory block is connected to each of the CPUI, CPU2, and storage device control unit 3, there is one surplus memory block that is not connected to any processing unit (CPUI, CPU2, storage device control unit 3). Arise. This surplus memory block is reserved for the system, and if only the processing in one of the processing systems is delayed due to the use of connecting as an alternative in the event of a memory block failure or some event, this memory block should be inserted Then, you can use it as a buffer memory that can proceed with other processing once and store the results.
　なお、第４メモリブロック１３は、ゲート１０－４を介して解析システムのＣＰＵ１と接続され、ゲート１４－４を介してマッチングシステムのＣＰＵ２と接続される。また、ゲート１５－４を介して保温装置制御部３と接続される。 The fourth memory block 13 is connected to the CPU 1 of the analysis system via the gate 10-4, and is connected to the CPU 2 of the matching system via the gate 14-4. Further, it is connected to the heat insulation device control unit 3 through the gate 15-4.
　他の構成は、実施例１と同様となる。 Other configurations are the same as those in the first embodiment.
　よって、実施例３においても、実施例１と同様な効果を奏することができる。 Therefore, also in Example 3, the same effect as Example 1 can be produced.
　なお、本発明は、原子力や火力などの発電プラント、あるいは石油化学などの化学プラントなどの大規模プラントの効率的運転あるいは事故時対処のためにプラント状態把握を補助する運転支援システムである情報処理装置に適用可能である。 The present invention is an information processing system that is an operation support system that assists in grasping the state of a plant for efficient operation of a large-scale plant such as a power plant such as nuclear power or thermal power, or a chemical plant such as petrochemical or for coping with an accident. Applicable to the device.
　１・・・解析システムのＣＰＵ、２・・・マッチングシステムのＣＰＵ、３・・・保存装置制御部、４・・・第１メモリブロック１、５・・・第２メモリブロック、６・・・第３メモリブロック、７・・・ＣＬＫ発生回路、８・・・切替回路、９・・・ＤＰＭ（Ｄｕａｌ　Ｐｏｒｔ　Ｍｅｍｏｒｙ）、１０－１、１０－２、１０－３、１０－４・・・単一方向ゲート、１２－１、１２－２、１２－３・・・双方向ゲート、１３・・・第４メモリブロック、１４－１、１４－２、１４－３、１４－４、１５－１、１５－２、１５－３、１５－４・・・単一方向ゲート、１６・・・記憶装置、１７、１８・・・アドレス制御バス、１９、２１・・・メモリ、２０、２２・・・ＳＳＤ、２３・・・表示部、２４・・・圧力センサ、２５・・・温度センサ、２６・・・流量センサ、２７・・・バルブ開閉センサ、２８－１、２８－２・・・データバス DESCRIPTION OF SYMBOLS 1 ... CPU of analysis system, 2 ... CPU of matching system, 3 ... Storage device control part, 4 ... 1st memory block 1, 5 ... 2nd memory block, 6 ... 3rd memory block, 7 ... CLK generating circuit, 8 ... switching circuit, 9 ... DPM (Dual Port Memory), 10-1, 10-2, 10-3, 10-4 ... single One-way gate, 12-1, 12-2, 12-3 ... Bidirectional gate, 13 ... Fourth memory block, 14-1, 14-2, 14-3, 14-4, 15-1 , 15-2, 15-3, 15-4 ... unidirectional gate, 16 ... storage device, 17, 18 ... address control bus, 19, 21 ... memory, 20, 22, ... -SSD, 23 ... display part, 24 ... pressure sensor, 25 ... temperature Capacitors, 26 ... flow sensor 27 ... valve opening and closing sensor, 28-1, 28-2 ... data bus

Claims (12)

  1. 　互いに機能が異なる複数のデータ処理部と、
    　複数のデータ記憶部と、
    　上記複数のデータ処理部のそれぞれが、上記複数のデータ記憶部に所定の順序で、データ書き込み動作又はデータ読み込み動作を行い、かつ、上記複数のデータ処理部のそれぞれが、互いに異なる上記データ記憶部に接続され、上記複数のデータ記憶部のデータへの書き込み動作又は読み込み動作を並列して行うように上記複数のデータ処理部と上記複数のデータ記憶部との接続を切り替える切替処理部と、
    　を備えることを特徴とする情報処理システム。     A plurality of data processing units having different functions, and
    A plurality of data storage units;
    Each of the plurality of data processing units performs a data write operation or a data read operation on the plurality of data storage units in a predetermined order, and each of the plurality of data processing units is different from each other. A switching processing unit that switches the connection between the plurality of data processing units and the plurality of data storage units so as to perform a writing operation or a reading operation on the data of the plurality of data storage units in parallel.
    An information processing system comprising:
  2. 　請求項１に記載の情報処理システムにおいて、
    　上記複数のデータ処理部は、第１データ処理部、第２データ処理部及び第３データ処理部を有し、上記複数のデータ記憶部は、第１データ記憶部、第２データ記憶部及び第３データ記憶部を有し、
    　上記切替処理部は、
    　上記第１データ処理部を上記第１データ記憶部、第２データ記憶部、第３データ記憶部に順に接続し、
    　上記第２データ処理部を、上記第１データ処理部のデータ書き込み動作又はデータ読み込み動作に続いて、上記第１データ処理部を上記第１データ記憶部、第２データ記憶部、第３データ記憶部に順に接続し、
    　上記第３データ処理部を、上記第２データ処理部のデータ書き込み動作又はデータ読み込み動作に続いて、上記第１データ処理部を上記第１データ記憶部、第２データ記憶部、第３データ記憶部に順に接続して、
    　第１データ処理部、第２データ処理部及び第３データ処理のデータ書き込み動作又はデータ読み込み動作が行われることを特徴とする情報処理システム。     The information processing system according to claim 1,
    The plurality of data processing units include a first data processing unit, a second data processing unit, and a third data processing unit, and the plurality of data storage units include a first data storage unit, a second data storage unit, and a second data storage unit. 3 data storage units
    The switching processing unit
    The first data processing unit is connected to the first data storage unit, the second data storage unit, and the third data storage unit in order,
    Following the data write operation or data read operation of the first data processing unit, the second data processing unit is changed to the first data storage unit, the second data storage unit, or the third data storage. Connect in turn,
    Following the data write operation or data read operation of the second data processing unit, the third data processing unit is changed to the first data storage unit, the second data storage unit, the third data storage. Connect in order to
    An information processing system in which a data writing operation or a data reading operation of a first data processing unit, a second data processing unit, and a third data processing is performed.
  3. 　請求項２に記載の情報処理システムにおいて、
    　上記情報処理システムは記憶装置を備え、
    　上記第１データ処理部は、解析対象に接続された複数のセンサからの検出信号を解析し、回析したデータを上記第１データ記憶部、上記第２データ記憶部及び上記第３データ記憶部に格納するデータ処理部であり、
    　上記第２データ処理部は、第１データ記憶部、上記第２データ記憶部及び上記第３データ記憶部に記憶された上記第１データ処理部の解析データを読み出して上記複数のセンサからの検出信号と比較し、上記解析対象の状態を判断するデータ処理部であり、
    　上記第３データ処理部は、第１データ記憶部、上記第２データ記憶部及び上記第３データ記憶部に記憶された上記第１データ処理部の解析データを読み出して、上記記憶装置に格納する保存装置制御部であることを特徴とする情報処理システム。     The information processing system according to claim 2,
    The information processing system includes a storage device,
    The first data processing unit analyzes detection signals from a plurality of sensors connected to an analysis target, and analyzes the analyzed data as the first data storage unit, the second data storage unit, and the third data storage unit. Is a data processing unit to be stored in
    The second data processing unit reads analysis data of the first data processing unit stored in the first data storage unit, the second data storage unit, and the third data storage unit and detects from the plurality of sensors. A data processing unit for comparing the signal and determining the state of the analysis target,
    The third data processing unit reads analysis data of the first data processing unit stored in the first data storage unit, the second data storage unit, and the third data storage unit, and stores the analysis data in the storage device. An information processing system which is a storage device control unit.
  4. 　請求項３に記載の情報処理システムにおいて、
    　上記第１データ処理部は、上記第１データ記憶部、上記第２データ記憶部及び上記第３データ記憶部に、データ格納動作のみ行う、第１の一方向ゲート、第２の一方向ゲート、第３の一方向ゲートに接続され、
    　上記第２データ処理部は、上記第１データ記憶部、上記第２データ記憶部及び上記第３データ記憶部に、データ読み込み動作のみ行う、第４の一方向ゲート、第５の一方向ゲート、第６の一方向ゲートに接続され、
    　上記第３データ処理部は、上記第１データ記憶部、上記第２データ記憶部及び上記第３データ記憶部に、データ読み込み動作のみ行う、第７の一方向ゲート、第８の一方向ゲート、第９の一方向ゲートに接続され、
    　上記切り替え処理部は、上記第１の一方向ゲート、第２の一方向ゲート、第３の一方向ゲート、第４の一方向ゲート、第５の一方向ゲート、第６の一方向ゲート、第７の一方向ゲート、第８の一方向ゲート、第９の一方向ゲートの開閉を制御することを特徴とする情報処理システム。     The information processing system according to claim 3,
    The first data processing unit includes a first one-way gate, a second one-way gate, which perform only data storage operations on the first data storage unit, the second data storage unit, and the third data storage unit, Connected to a third one-way gate;
    The second data processing unit performs only a data reading operation on the first data storage unit, the second data storage unit, and the third data storage unit, a fourth one-way gate, a fifth one-way gate, Connected to a sixth one-way gate;
    The third data processing unit performs only a data reading operation on the first data storage unit, the second data storage unit, and the third data storage unit, a seventh one-way gate, an eighth one-way gate, Connected to the ninth one-way gate;
    The switching processing unit includes the first unidirectional gate, the second unidirectional gate, the third unidirectional gate, the fourth unidirectional gate, the fifth unidirectional gate, the sixth unidirectional gate, 7. An information processing system that controls opening and closing of the one-way gate, the eighth one-way gate, and the ninth one-way gate.
  5. 　請求項３に記載の情報処理システムにおいて、
    　上記第１データ処理部は、上記第１データ記憶部、上記第２データ記憶部及び上記第３データ記憶部に、データ格納動作及び読み込み動作を行う、第１の双方向ゲート、第２の双方向ゲート、第３の双方向ゲートに接続され、
    　上記第２データ処理部は、上記第１データ記憶部、上記第２データ記憶部及び上記第３データ記憶部に、データ読み込み動作のみ行う、第４の一方向ゲート、第５の一方向ゲート、第６の一方向ゲートに接続され、
    　上記第３データ処理部は、上記第１データ記憶部、上記第２データ記憶部及び上記第３データ記憶部に、データ読み込み動作のみ行う、第７の一方向ゲート、第８の一方向ゲート、第９の一方向ゲートに接続され、
    　上記切り替え処理部は、上記第１の双方向ゲート、第２の双方向ゲート、第３の双方向ゲート、第４の一方向ゲート、第５の一方向ゲート、第６の一方向ゲート、第７の一方向ゲート、第８の一方向ゲート、第９の一方向ゲートの開閉を制御することを特徴とする情報処理システム。     The information processing system according to claim 3,
    The first data processing unit performs a data storing operation and a reading operation on the first data storage unit, the second data storage unit, and the third data storage unit. Connected to the direction gate, the third bidirectional gate,
    The second data processing unit performs only a data reading operation on the first data storage unit, the second data storage unit, and the third data storage unit, a fourth one-way gate, a fifth one-way gate, Connected to a sixth one-way gate;
    The third data processing unit performs only a data reading operation on the first data storage unit, the second data storage unit, and the third data storage unit, a seventh one-way gate, an eighth one-way gate, Connected to the ninth one-way gate;
    The switching processing unit includes the first bidirectional gate, the second bidirectional gate, the third bidirectional gate, the fourth unidirectional gate, the fifth unidirectional gate, the sixth unidirectional gate, 7. An information processing system that controls opening and closing of the one-way gate, the eighth one-way gate, and the ninth one-way gate.
  6. 　請求項１に記載の情報処理システムにおいて、
    　上記複数のデータ処理部は、第１データ処理部、第２データ処理部及び第３データ処理部を有し、上記複数のデータ記憶部は、第１データ記憶部、第２データ記憶部、第３データ記憶部、予備の第４データ記憶部を有し、
    　上記切替処理部は、
    　上記第１データ処理部を上記第１データ記憶部、第２データ記憶部、第３データ記憶部に順に接続し、
    　上記第２データ処理部を、上記第１データ処理部のデータ書き込み動作又はデータ読み込み動作に続いて、上記第１データ処理部を上記第１データ記憶部、第２データ記憶部、第３データ記憶部に順に接続し、
    　上記第３データ処理部を、上記第２データ処理部のデータ書き込み動作又はデータ読み込み動作に続いて、上記第１データ処理部を上記第１データ記憶部、第２データ記憶部、第３データ記憶部に順に接続して、
    　第１データ処理部、第２データ処理部及び第３データ処理のデータ書き込み動作又はデータ読み込み動作が行われ、
    　上記第４データ記憶部は、上記第１データ記憶部、第２データ記憶部又は第３データ記憶部に替えて使用される記憶部、又はバッファメモリとして使用される記憶部であることを特徴とする情報処理システム。     The information processing system according to claim 1,
    The plurality of data processing units include a first data processing unit, a second data processing unit, and a third data processing unit, and the plurality of data storage units include a first data storage unit, a second data storage unit, a second data storage unit, 3 data storage units, a spare 4th data storage unit,
    The switching processing unit
    The first data processing unit is connected to the first data storage unit, the second data storage unit, and the third data storage unit in order,
    Following the data write operation or data read operation of the first data processing unit, the second data processing unit is changed to the first data storage unit, the second data storage unit, or the third data storage. Connect in turn,
    Following the data write operation or data read operation of the second data processing unit, the third data processing unit is changed to the first data storage unit, the second data storage unit, the third data storage. Connect in order to
    A data writing operation or a data reading operation of the first data processing unit, the second data processing unit, and the third data processing is performed,
    The fourth data storage unit is a storage unit used in place of the first data storage unit, the second data storage unit, or the third data storage unit, or a storage unit used as a buffer memory. Information processing system.
  7. 　互いに機能が異なる複数のデータ処理部のそれぞれが、上記複数のデータ記憶部に所定の順序で、データ書き込み動作又はデータ読み込み動作を行い、かつ、上記複数のデータ処理部のそれぞれが、互いに異なる上記データ記憶部に接続され、上記複数のデータ記憶部のデータへの書き込み動作又は読み込み動作を並列して行うように上記複数のデータ処理部と上記複数のデータ記憶部との接続を切り替えることを特徴とする情報処理方法。 Each of the plurality of data processing units having different functions performs a data writing operation or a data reading operation in a predetermined order on the plurality of data storage units, and each of the plurality of data processing units is different from each other. Connected to the data storage unit, and switches the connection between the plurality of data processing units and the plurality of data storage units so as to perform a write operation or a read operation on data in the plurality of data storage units in parallel. Information processing method.
  8. 　請求項７に記載の情報処理方法において、
    　上記複数のデータ処理部は、第１データ処理部、第２データ処理部及び第３データ処理部を有し、上記複数のデータ記憶部は、第１データ記憶部、第２データ記憶部及び第３データ記憶部を有し、
    　上記第１データ処理部を上記第１データ記憶部、第２データ記憶部、第３データ記憶部に順に接続し、
    　上記第２データ処理部を、上記第１データ処理部のデータ書き込み動作又はデータ読み込み動作に続いて、上記第１データ処理部を上記第１データ記憶部、第２データ記憶部、第３データ記憶部に順に接続し、
    　上記第３データ処理部を、上記第２データ処理部のデータ書き込み動作又はデータ読み込み動作に続いて、上記第１データ処理部を上記第１データ記憶部、第２データ記憶部、第３データ記憶部に順に接続して、
    　第１データ処理部、第２データ処理部及び第３データ処理のデータ書き込み動作又はデータ読み込み動作が行われることを特徴とする情報処理方法。     The information processing method according to claim 7,
    The plurality of data processing units include a first data processing unit, a second data processing unit, and a third data processing unit, and the plurality of data storage units include a first data storage unit, a second data storage unit, and a second data storage unit. 3 data storage units
    The first data processing unit is connected to the first data storage unit, the second data storage unit, and the third data storage unit in order,
    Following the data write operation or data read operation of the first data processing unit, the second data processing unit is changed to the first data storage unit, the second data storage unit, or the third data storage. Connect in turn,
    Following the data write operation or data read operation of the second data processing unit, the third data processing unit is changed to the first data storage unit, the second data storage unit, the third data storage. Connect in order to
    An information processing method comprising performing a data writing operation or a data reading operation of a first data processing unit, a second data processing unit, and a third data processing.
  9. 　請求項８に記載の情報処理方法において、
    　上記第１データ処理部は、解析対象に接続された複数のセンサからの検出信号を解析し、回析したデータを上記第１データ記憶部、上記第２データ記憶部及び上記第３データ記憶部に格納するデータ処理部であり、
    　上記第２データ処理部は、第１データ記憶部、上記第２データ記憶部及び上記第３データ記憶部に記憶された上記第１データ処理部の解析データを読み出して上記複数のセンサからの検出信号と比較し、上記解析対象の状態を判断するデータ処理部であり、
    　上記第３データ処理部は、第１データ記憶部、上記第２データ記憶部及び上記第３データ記憶部に記憶された上記第１データ処理部の解析データを読み出して、上記記憶装置に格納する保存装置制御部であることを特徴とする情報処理方法。     The information processing method according to claim 8,
    The first data processing unit analyzes detection signals from a plurality of sensors connected to an analysis target, and analyzes the analyzed data as the first data storage unit, the second data storage unit, and the third data storage unit. Is a data processing unit to be stored in
    The second data processing unit reads analysis data of the first data processing unit stored in the first data storage unit, the second data storage unit, and the third data storage unit and detects from the plurality of sensors. A data processing unit for comparing the signal and determining the state of the analysis target,
    The third data processing unit reads analysis data of the first data processing unit stored in the first data storage unit, the second data storage unit, and the third data storage unit, and stores the analysis data in the storage device. An information processing method characterized by being a storage device control unit.
  10. 　請求項９に記載の情報処理方法において、
    　上記第１データ処理部は、上記第１データ記憶部、上記第２データ記憶部及び上記第３データ記憶部に、データ格納動作のみ行う、第１の一方向ゲート、第２の一方向ゲート、第３の一方向ゲートに接続され、
    　上記第２データ処理部は、上記第１データ記憶部、上記第２データ記憶部及び上記第３データ記憶部に、データ読み込み動作のみ行う、第４の一方向ゲート、第５の一方向ゲート、第６の一方向ゲートに接続され、
    　上記第３データ処理部は、上記第１データ記憶部、上記第２データ記憶部及び上記第３データ記憶部に、データ読み込み動作のみ行う、第７の一方向ゲート、第８の一方向ゲート、第９の一方向ゲートに接続され、
    　上記第１の一方向ゲート、第２の一方向ゲート、第３の一方向ゲート、第４の一方向ゲート、第５の一方向ゲート、第６の一方向ゲート、第７の一方向ゲート、第８の一方向ゲート、第９の一方向ゲートの開閉を制御することを特徴とする情報処理方法。     The information processing method according to claim 9,
    The first data processing unit includes a first one-way gate, a second one-way gate, which perform only data storage operations on the first data storage unit, the second data storage unit, and the third data storage unit, Connected to a third one-way gate;
    The second data processing unit performs only a data reading operation on the first data storage unit, the second data storage unit, and the third data storage unit, a fourth one-way gate, a fifth one-way gate, Connected to a sixth one-way gate;
    The third data processing unit performs only a data reading operation on the first data storage unit, the second data storage unit, and the third data storage unit, a seventh one-way gate, an eighth one-way gate, Connected to the ninth one-way gate;
    The first one-way gate, the second one-way gate, the third one-way gate, the fourth one-way gate, the fifth one-way gate, the sixth one-way gate, the seventh one-way gate, An information processing method comprising controlling opening and closing of an eighth unidirectional gate and a ninth unidirectional gate.
  11. 　請求項９に記載の情報処理方法において、
    　上記第１データ処理部は、上記第１データ記憶部、上記第２データ記憶部及び上記第３データ記憶部に、データ格納動作及び読み込み動作を行う、第１の双方向ゲート、第２の双方向ゲート、第３の双方向ゲートに接続され、
    　上記第２データ処理部は、上記第１データ記憶部、上記第２データ記憶部及び上記第３データ記憶部に、データ読み込み動作のみ行う、第４の一方向ゲート、第５の一方向ゲート、第６の一方向ゲートに接続され、
    　上記第３データ処理部は、上記第１データ記憶部、上記第２データ記憶部及び上記第３データ記憶部に、データ読み込み動作のみ行う、第７の一方向ゲート、第８の一方向ゲート、第９の一方向ゲートに接続され、
    　上記第１の双方向ゲート、第２の双方向ゲート、第３の双方向ゲート、第４の一方向ゲート、第５の一方向ゲート、第６の一方向ゲート、第７の一方向ゲート、第８の一方向ゲート、第９の一方向ゲートの開閉を制御することを特徴とする情報処理方法。     The information processing method according to claim 9,
    The first data processing unit performs a data storing operation and a reading operation on the first data storage unit, the second data storage unit, and the third data storage unit. Connected to the direction gate, the third bidirectional gate,
    The second data processing unit performs only a data reading operation on the first data storage unit, the second data storage unit, and the third data storage unit, a fourth one-way gate, a fifth one-way gate, Connected to a sixth one-way gate;
    The third data processing unit performs only a data reading operation on the first data storage unit, the second data storage unit, and the third data storage unit, a seventh one-way gate, an eighth one-way gate, Connected to the ninth one-way gate;
    The first bidirectional gate, the second bidirectional gate, the third bidirectional gate, the fourth unidirectional gate, the fifth unidirectional gate, the sixth unidirectional gate, the seventh unidirectional gate, An information processing method comprising controlling opening and closing of an eighth unidirectional gate and a ninth unidirectional gate.
  12. 　請求項７に記載の情報処理方法において、
    　上記複数のデータ処理部は、第１データ処理部、第２データ処理部及び第３データ処理部を有し、上記複数のデータ記憶部は、第１データ記憶部、第２データ記憶部、第３データ記憶部、予備の第４データ記憶部を有し、
    　上記第１データ処理部を上記第１データ記憶部、第２データ記憶部、第３データ記憶部に順に接続し、
    　上記第２データ処理部を、上記第１データ処理部のデータ書き込み動作又はデータ読み込み動作に続いて、上記第１データ処理部を上記第１データ記憶部、第２データ記憶部、第３データ記憶部に順に接続し、
    　上記第３データ処理部を、上記第２データ処理部のデータ書き込み動作又はデータ読み込み動作に続いて、上記第１データ処理部を上記第１データ記憶部、第２データ記憶部、第３データ記憶部に順に接続して、
    　第１データ処理部、第２データ処理部及び第３データ処理のデータ書き込み動作又はデータ読み込み動作が行われ、
    　上記第４データ記憶部は、上記第１データ記憶部、第２データ記憶部又は第３データ記憶部に替えて使用される記憶部、又はバッファメモリとして使用される記憶部であることを特徴とする情報処理方法。     The information processing method according to claim 7,
    The plurality of data processing units include a first data processing unit, a second data processing unit, and a third data processing unit, and the plurality of data storage units include a first data storage unit, a second data storage unit, a second data storage unit, 3 data storage units, a spare 4th data storage unit,
    The first data processing unit is connected to the first data storage unit, the second data storage unit, and the third data storage unit in order,
    Following the data write operation or data read operation of the first data processing unit, the second data processing unit is changed to the first data storage unit, the second data storage unit, or the third data storage. Connect in turn,
    Following the data write operation or data read operation of the second data processing unit, the third data processing unit is changed to the first data storage unit, the second data storage unit, the third data storage. Connect in order to
    A data writing operation or a data reading operation of the first data processing unit, the second data processing unit, and the third data processing is performed,
    The fourth data storage unit is a storage unit used in place of the first data storage unit, the second data storage unit, or the third data storage unit, or a storage unit used as a buffer memory. Information processing method.
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