JPS6491276A - Device for supporting circuit design - Google Patents

Device for supporting circuit design

Info

Publication number
JPS6491276A
JPS6491276A JP62247535A JP24753587A JPS6491276A JP S6491276 A JPS6491276 A JP S6491276A JP 62247535 A JP62247535 A JP 62247535A JP 24753587 A JP24753587 A JP 24753587A JP S6491276 A JPS6491276 A JP S6491276A
Authority
JP
Japan
Prior art keywords
circuit
gates
inputs
circuit design
ews
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62247535A
Other languages
Japanese (ja)
Inventor
Toshiaki Shirasago
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62247535A priority Critical patent/JPS6491276A/en
Publication of JPS6491276A publication Critical patent/JPS6491276A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To learn the total number of gates in a circuit design graphic at any time by adding subtracting the number of the gates in correspondence to the addition or deletion of a circuit in a prescribed unit and storing the result in the generation stage of the circuit design graphic. CONSTITUTION:For newly generating the graphic, for drawing 'the AND circuit of two inputs', for example, '+' and Wright control signals are transmitted from an EWS engine 6 to a counter 8, and address data corresponding to the 'AND circuit of the two inputs' is transmitted from the EWS engine 6 to a gate number registration memory 7. Thus, data for the number of the gates corresponding to the address, namely, the 'AND circuit of the two inputs' are read, in the gate number registration memory 7, and are read into the counter 8 through a data bus 10, whereby they are added to the number of the gates till then. At the time of deletion, '-' and Wright signals are outputted and a similar addition subtraction processing is executed so forth.
JP62247535A 1987-09-30 1987-09-30 Device for supporting circuit design Pending JPS6491276A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62247535A JPS6491276A (en) 1987-09-30 1987-09-30 Device for supporting circuit design

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62247535A JPS6491276A (en) 1987-09-30 1987-09-30 Device for supporting circuit design

Publications (1)

Publication Number Publication Date
JPS6491276A true JPS6491276A (en) 1989-04-10

Family

ID=17164941

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62247535A Pending JPS6491276A (en) 1987-09-30 1987-09-30 Device for supporting circuit design

Country Status (1)

Country Link
JP (1) JPS6491276A (en)

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