JPS56168255A - Interface adapter - Google Patents
Interface adapterInfo
- Publication number
- JPS56168255A JPS56168255A JP7232680A JP7232680A JPS56168255A JP S56168255 A JPS56168255 A JP S56168255A JP 7232680 A JP7232680 A JP 7232680A JP 7232680 A JP7232680 A JP 7232680A JP S56168255 A JPS56168255 A JP S56168255A
- Authority
- JP
- Japan
- Prior art keywords
- stored
- register
- information
- registers
- adapeter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
Abstract
PURPOSE:To make response time faster by providing memories which store condition information and execution okay or not information in an interface adapeter for the purpose of connecting a minicomputer or the like to the channel interface of a host computer. CONSTITUTION:The information indicating whether a magnetic tape is in a write protection state or not is stored in the condition memory 16 of an interface adapeter 2, and the information relating to the action to be made in response to the conditions stored in the condition memory 16 is stored in a requirement memory 17. The information in a bus 11 from a minicomputer is stored in the respective registers in the adapeter, and devices addresses are stored in a register 13, and command codes in a register 15, respectively. The registers 13 and 15 operate as address registers respectively, to read out the addresses from memories 16 and 17 respectively and store them in registers 18 and 19. In the next logical circuit 20, all the bits are collated, and by the results thereof, the contents of an acceptance register 25 or a reject register 26 are sent to the host computer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7232680A JPS56168255A (en) | 1980-05-30 | 1980-05-30 | Interface adapter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7232680A JPS56168255A (en) | 1980-05-30 | 1980-05-30 | Interface adapter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56168255A true JPS56168255A (en) | 1981-12-24 |
Family
ID=13486041
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7232680A Pending JPS56168255A (en) | 1980-05-30 | 1980-05-30 | Interface adapter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56168255A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3719578A1 (en) | 2019-04-03 | 2020-10-07 | Ricoh Company, Ltd. | Electrophotographic developer, replenishment developer, image forming apparatus, process cartridge, and image forming method |
-
1980
- 1980-05-30 JP JP7232680A patent/JPS56168255A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3719578A1 (en) | 2019-04-03 | 2020-10-07 | Ricoh Company, Ltd. | Electrophotographic developer, replenishment developer, image forming apparatus, process cartridge, and image forming method |
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