JPS61187061A - Time-division multiplex bus interface device - Google Patents

Abstract

PURPOSE:To prevent malfunction due to variance or the like of parts characteristics by providing a transparent latch on a data bus connecting a processor and a register to take sufficiently the data holding time for writing on the register. CONSTITUTION:A transparent latch 13 is provided on a data bus 5 connecting a processor 1 and a register 2, and a system clock pulse 8 is supplied to this latch 13. The data signal given to the data register 2 is fixed to the value at the time, when the clock pulse shown in a figure (a) is changed from the high level to the low level, as shown in a figure (c) and is not changed until the clock pulse is changed from the low level to the high level. Data is written surely because data to the register 2 is held even if the time when a write pulse, which is shown in a figure (d), for write on the data register 2 is changed from the low level to the high level is varied somewhat.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a time division multiplex bus interface device with improved data hold time during data writing.

Writing data to a register is performed by a write pulse derived from a system clock pulse, but in order to ensure writing, it is desirable to adjust the time relationship between the data signal arriving at the register and the write pulse.

[Conventional technology]

FIG. 4 shows the configuration of a conventional time division multiplexed bus interface in a block circuit diagram. In the figure, 1 is a processor;
2 and 3 are registers, 4 is a decoder, 5 is a data bus, 6
7 is an address bus, 7 is a clock pulse generator, 8 is a system clock pulse, 9 is an inverter, 10 is a write pulse output line, 11 is an address buffer, and 12 is a transceiver.

The data bus 5 and address bus 6 of the main unit including the processor 1 and decoder 4 are connected to the data register 2 and address register 3 of other subunits via the TDM bus section sandwiched by broken lines.

The data write operation to data register 2 in FIG.
The explanation will be made according to the waveform diagrams in columns a to d in the figure.

The system clock pulse supplied from processor 1 to decoder 4 via line 8 is applied to column a, the address and data signals from processor 1 are supplied to column b and column 0, and the write pulse supplied from decoder 4 to data register 2 is applied to column a. d
Shown in columns.

The data signal is sent out from the processor 1 after the rising edge of the system clock pulse, as shown in columns a and 0 in FIG. 5, and is sent out to the bus so that the data signal level is determined by the falling edge of the system clock pulse. On the other hand, the system clock pulse is sent from processor 1 to decoder 4.
It is supplied as a write pulse to register 2 or 3 specified by the address signal supplied to register 2 or 3. The polarity of this is reversed by the inverter 9. Writing of the data signal occurs on the rising leading edge of the write pulse, which corresponds to the trailing edge of the system clock pulse. However, since the signal passes through a decoder and an inverter, there is a time delay, and it is necessary to provide a delay to the address signal and data signal given to the register to determine the write timing. The role of this delay is played by the buffer 11 for the address bus and the transceiver 12 for the data bus, which are conventionally provided to increase fan-out.

[Problem that the invention seeks to solve]

Regarding data transmission from a processor, it is necessary that the data be transmitted after the clock signal rises, and that the data signal be established before the clock falls.

Data is written to the register at the rising edge of the write pulse, that is, at the falling edge of the clock, but due to variations in component characteristics, temperature fluctuations, and delay time variations, the data to the register at the time of data writing is There are four problems: it is not possible to sufficiently compensate for the hold time, and it is difficult to design a circuit to match the timing.
be.

[Means for solving problems]

The above problems are solved by the time division multiplex bus interface device according to the present invention, which includes a transparent latch on the data bus connecting the processor and the registers.

[Effect]

The transparent latch provided on the data bus according to the present invention outputs the data signal applied to its input part with the same change as the input waveform during the period of the set pulse H (high), but during the period of the set pulse H (high), the transparent latch is provided on the data bus. During this period, the value that the data signal takes at the time when the set pulse changes from H to L is held, so that the data hold time to the register at the time of data writing can be sufficiently compensated.

〔Example〕

Hereinafter, the gist of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block configuration diagram showing one embodiment of the time division multiplex bus interface device of the present invention, FIG. 2 is a waveform diagram for explaining its operation, and FIG. 3 is a diagram used in the circuit of the present invention. FIG. 3 is a waveform diagram for explaining the operation of the transparent latch circuit.

In the drawings, the same parts as in FIG. 1 are indicated by the same numbers.

In FIG. 1, a transparent latch 13 is provided on a data bus connecting a processor 1, a data register, and a register 2 according to the present invention. The system clock pulse 8 is supplied to the latch 13 as a cent pulse.

As shown in column C of FIG. 2, the data signal applied to data register 2 is fixed at the value at the time when the clock pulse in column a changes from H to L, and until the time when the clock pulse changes from L to H. It is constant and never changes. Therefore, even if the time point at which the write pulse for column d, which is to be written to the data register 2, changes from L to H changes somewhat,
Since the data in register 2 is held, data writing is performed reliably.

FIG. 3 shows the waveforms of the input and output signals to the transparent latch, where the e column shows the set pulse, the 1st column shows the data input, and the g column shows the data output.

When the set pulse applied to the transparent latch is at H level, the data output signal waveform changes in the same way as the data input waveform, but when the set pulse is at L level, the data output signal waveform remains constant and the set pulse The data input value at the time of change from H level to L level is held.

In the illustrated case, since the input data value is H, the output data value is held at H level.

〔Effect of the invention〕

As described above, according to the present invention, the data hold time in the register is sufficiently compensated for, so variations in component characteristics,
The design difficulties caused by taking into consideration temperature fluctuations, signal delay characteristics, etc. are eliminated, and the writing operation of the register is ensured, so the effect is extremely large.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the time division multiplex bus interface device of the present invention, FIG. 2 is a waveform diagram for explaining its operation, and FIG. 3 is a transparent latch circuit used in the circuit of the present invention. FIG. 4 is a block circuit diagram showing the configuration of a conventional time-division multiplexed path interface, and FIG. 5 is a waveform diagram of its operation. In the drawing, 1 is a processor 2.3 is a register, 4 is a decoder, 5 is a data bus, 6 is an address bus, 7 is a clock pulse generator, 8 is a system clock pulse, 9 is an inverter, 10 is a write pulse output line, 11 is an address buffer, 12 is a transceiver, and 13 is a transparent latch. 7￥a Man 1 Keru Hasui〉Kuhwei Source Pessimism Bokugo Furon 20
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Claims (1)

[Claims] A time division multiplex bus interface device characterized in that a data bus connecting a processor and a register is provided with a transparent latch.