JPS57130135A - Timing control circuit - Google Patents
Timing control circuitInfo
- Publication number
- JPS57130135A JPS57130135A JP56014822A JP1482281A JPS57130135A JP S57130135 A JPS57130135 A JP S57130135A JP 56014822 A JP56014822 A JP 56014822A JP 1482281 A JP1482281 A JP 1482281A JP S57130135 A JPS57130135 A JP S57130135A
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- clock
- phicpu
- cpu
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
- G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
Abstract
PURPOSE:To secure the stability of data transmission and receiving between a CPU and peripheral circuits, by giving clock pulses different from one another to the CPU, peripheral cirtuits (including a memory), and a buffer driver, respectively. CONSTITUTION:A clock pulse WE for write is generated in a clock circuit 5, and the pulse WE is applied to a flip-flop and is delayed by driving it by a reference clock CL to generate a CPU operation clock phiCPU and a clock pulse RE for read. The pulse WE is >=10 nanoseconds earlier than the clock phiCPU, and the pulse RE is >=10 nanoseconds later than the clock phiCPU. These pulses are applied individually, and thus, the pulse RE is outputted from an AND gate 8 in the data read mode where a CPU 1 reads data from a peripheral circuit, and the pulse RE and the pulse WE are combined in an OR gate 7, and the edge of the combined pulse is later than that of the clock phiCPU, and a required pulse for read is obtained.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56014822A JPS57130135A (en) | 1981-02-03 | 1981-02-03 | Timing control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56014822A JPS57130135A (en) | 1981-02-03 | 1981-02-03 | Timing control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57130135A true JPS57130135A (en) | 1982-08-12 |
Family
ID=11871724
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56014822A Pending JPS57130135A (en) | 1981-02-03 | 1981-02-03 | Timing control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57130135A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6083166A (en) * | 1983-10-14 | 1985-05-11 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPH02168340A (en) * | 1988-09-16 | 1990-06-28 | Hitachi Ltd | Processor system using distributed machine state control method |
-
1981
- 1981-02-03 JP JP56014822A patent/JPS57130135A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6083166A (en) * | 1983-10-14 | 1985-05-11 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPH059835B2 (en) * | 1983-10-14 | 1993-02-08 | Hitachi Seisakusho Kk | |
| JPH02168340A (en) * | 1988-09-16 | 1990-06-28 | Hitachi Ltd | Processor system using distributed machine state control method |
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