JPS5569860A - Clock margin setting system - Google Patents

Clock margin setting system

Info

Publication number
JPS5569860A
JPS5569860A JP14377078A JP14377078A JPS5569860A JP S5569860 A JPS5569860 A JP S5569860A JP 14377078 A JP14377078 A JP 14377078A JP 14377078 A JP14377078 A JP 14377078A JP S5569860 A JPS5569860 A JP S5569860A
Authority
JP
Japan
Prior art keywords
circuit
pulse
clock
circuits
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14377078A
Other languages
Japanese (ja)
Other versions
JPS603221B2 (en
Inventor
Tsutomu Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53143770A priority Critical patent/JPS603221B2/en
Publication of JPS5569860A publication Critical patent/JPS5569860A/en
Publication of JPS603221B2 publication Critical patent/JPS603221B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To make it possible to point out a defective part in the concrete by setting a clock margin to some circuits instead of margining the whole data processor by driving it by a high-speed pulse, etc.
CONSTITUTION: For a strict clock margin test, control signals G1 and G4 are applied to AND circuits 4-1 and 4-4. Consequently, clock pulse C1 sent from OR circuit 5-1 to 1st FF circuit 6 is clock pulse CL1 from phase adjustment circuit 2, and similarly clock pulse C2 applied to 2nd FF circuit 9 is clock pulse CL2 from phase adjustment circuit 3. Therefore pulses C1 and C2 are shown in Fig. (e). Since pulse C2 leads C1 in phase, pulse C1 is applied to circuit 6 first and after time T2, pulse C2 is applied to circuit 9. Since intervals of clock C1 are time T1 and T1 is greater than T2, circuit 9 is limited in a shorter time than when circuits 6 and 9 are controlled at the same timing by pulses C1 and C2.
COPYRIGHT: (C)1980,JPO&Japio
JP53143770A 1978-11-21 1978-11-21 Clock margin test method Expired JPS603221B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53143770A JPS603221B2 (en) 1978-11-21 1978-11-21 Clock margin test method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53143770A JPS603221B2 (en) 1978-11-21 1978-11-21 Clock margin test method

Publications (2)

Publication Number Publication Date
JPS5569860A true JPS5569860A (en) 1980-05-26
JPS603221B2 JPS603221B2 (en) 1985-01-26

Family

ID=15346611

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53143770A Expired JPS603221B2 (en) 1978-11-21 1978-11-21 Clock margin test method

Country Status (1)

Country Link
JP (1) JPS603221B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6015727A (en) * 1983-07-05 1985-01-26 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション System clock controller
JPS625445A (en) * 1985-07-01 1987-01-12 Nec Corp Information processor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6015727A (en) * 1983-07-05 1985-01-26 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション System clock controller
JPH0418329B2 (en) * 1983-07-05 1992-03-27 Intaanashonaru Bijinesu Mashiinzu Corp
JPS625445A (en) * 1985-07-01 1987-01-12 Nec Corp Information processor

Also Published As

Publication number Publication date
JPS603221B2 (en) 1985-01-26

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