KR850007155A - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
KR850007155A
KR850007155A KR1019850001299A KR850001299A KR850007155A KR 850007155 A KR850007155 A KR 850007155A KR 1019850001299 A KR1019850001299 A KR 1019850001299A KR 850001299 A KR850001299 A KR 850001299A KR 850007155 A KR850007155 A KR 850007155A
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KR
South Korea
Prior art keywords
signal
reset
complementary
semiconductor memory
memory device
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KR1019850001299A
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Korean (ko)
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KR910000963B1 (en
Inventor
쇼오이찌로오 가와시마
Original Assignee
야마모도 다꾸마
후지쓰 가부시끼가이샤
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Application filed by 야마모도 다꾸마, 후지쓰 가부시끼가이샤 filed Critical 야마모도 다꾸마
Publication of KR850007155A publication Critical patent/KR850007155A/en
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Publication of KR910000963B1 publication Critical patent/KR910000963B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

내용 없음No content

Description

반도체 메모리 장치Semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제10도 내지 제12도는 본 발명의 실시예를 설명하는 도. 제10도는 본 발명의 실시예에 따른 반도체 메모리장치내에서 리세트 펄스 발생기를 일반적으로 도시한 블룩회로도. 제11도는 제10도에 도시된 리세트 펄스발생기에서 리세트 발생회로의 블록도. 제12도는제 11도에 도신된 회로의 상세한 회로도.10 through 12 illustrate an embodiment of the present invention. 10 is a block diagram generally showing a reset pulse generator in a semiconductor memory device according to an embodiment of the present invention. FIG. 11 is a block diagram of a reset generation circuit in the reset pulse generator shown in FIG. 12 is a detailed circuit diagram of the circuit shown in FIG.

*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

3 : 플립플롭, 4 : 지연회로,: 칩선택 제어신호,ØR : 비트선 리세트신호.3: flip-flop, 4: delay circuit, : Chip select control signal, ØR: Bit line reset signal.

Claims (5)

제어신호에 응하여 선택상태와 비선택상태를 갖는 반도체 메모리장치에 있어서, 상기 장치는 상보적(complementary)신호를 전송하는 1쌍의 신호선, 및 상기 제어신호가 상기 장치의 상기 비선택상태를 나타낼때 상기 신호선을 등가전위로 리세트하는 제 1리세트 신호를 발생하는 리세트신호 발생기를 포함하고 있으며, 상기 제 1리세트 신호는 상기 제어신호에 의하여 나타내진 비선택상태의 시간이 소정기간보다 짧을대라도 상기 소정기간보다 더 긴 리세트기간을 갖는 것을 특징으로하는 반도체 메모리장치.A semiconductor memory device having a selected state and a non-selected state in response to a control signal, the apparatus comprising: a pair of signal lines for transmitting a complementary signal, and when the control signal indicates the non-selected state of the device; And a reset signal generator for generating a first reset signal for resetting the signal line at an equivalent potential, wherein the time of the non-selection state represented by the control signal is shorter than a predetermined period. Wherein the semiconductor memory device has a reset period longer than the predetermined period. 제1항에 있어서, 더우기 상기 장치는 상보적 어드레스 신호를 제공하는 어드레스 버퍼회로를 포함하고 있으며, 상기 상부적 어드레스신호는 상기 비선택상태 동안 등가전위로 리세트되며, 더우기 상기 리세트신호 발생기는 상기 상보적 어드레스신호의 변환에 응하여 제 2리세트신호를 발생하는 펄스 발생회로를 포함하고 있으며, 상기 상보적 신호는 상기 제 1리세트신호와 상기 제 2리세트신호중 어느 하나로부터 획득된 보다 긴 리세트기간을 갖는 리세트신호에 의하여 리세트되는 것을 특징으로 하는 반도체 메모리장치.2. The apparatus of claim 1, further comprising an address buffer circuit that provides a complementary address signal, wherein the top address signal is reset to an equivalent potential during the non-selection state, and further, the reset signal generator And a pulse generating circuit for generating a second reset signal in response to the conversion of the complementary address signal, wherein the complementary signal is longer than one obtained from either the first reset signal or the second reset signal. And a reset signal having a reset period. 제2항에 있어서, 상기 제2리세트신호의 펄스폭이 상기 비선택상태의 시간이 증가함에 따라서 더 짧아지는 것을 특징으로 하는 반도체 메모리장치.3. The semiconductor memory device according to claim 2, wherein the pulse width of said second reset signal becomes shorter as the time of said non-selection state increases. 제1항에 있어서, 상기 상보적 신호가 비트선쌍인 것을 특징으로 하는 반도체 메모리장치.2. The semiconductor memory device according to claim 1, wherein said complementary signal is a bit line pair. 제1항에 있어서, 상기 리세트신호 발생회로는 상기 제어신호를 세트단자에서 수신하는 플립플롭, 및 상기 상보적 신호전위를 리세트하는데 필요한 시간만큼 상기 플립플롭의 출력을 지연시키는 지연회로로 구성되어 있으며, 상기 지연회로의 출력에 의하여 상기 플립플롭을 리세트하도록 구성되어 있고 상기 플립플롭의 출력이 제 1리세트 신호로서 사용되는 것을 특징으로 하는 반도체 메모리장치.2. The circuit of claim 1, wherein the reset signal generation circuit comprises a flip-flop for receiving the control signal at a set terminal, and a delay circuit for delaying the output of the flip-flop by a time necessary to reset the complementary signal potential. And the flip-flop is reset by the output of the delay circuit, and the output of the flip-flop is used as a first reset signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR8501299A 1984-02-29 1985-02-28 Semiconductor memory device KR910000963B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59035920A JPS60182096A (en) 1984-02-29 1984-02-29 Semiconductor memory device
JP59-035920 1984-02-29

Publications (2)

Publication Number Publication Date
KR850007155A true KR850007155A (en) 1985-10-30
KR910000963B1 KR910000963B1 (en) 1991-02-19

Family

ID=12455464

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Application Number Title Priority Date Filing Date
KR8501299A KR910000963B1 (en) 1984-02-29 1985-02-28 Semiconductor memory device

Country Status (5)

Country Link
US (1) US4766571A (en)
EP (1) EP0155787B1 (en)
JP (1) JPS60182096A (en)
KR (1) KR910000963B1 (en)
DE (1) DE3581223D1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4800552A (en) * 1985-12-18 1989-01-24 Fujitsu Limited Semiconductor memory device with reset signal generating circuit
JPH0612612B2 (en) * 1987-03-06 1994-02-16 株式会社東芝 Semiconductor memory device
US5719812A (en) * 1988-11-16 1998-02-17 Fujitsu Limited Semiconductor memory including bit line reset circuitry and a pulse generator having output delay time dependent on type of transition in an input signal
JPH0814995B2 (en) * 1989-01-27 1996-02-14 株式会社東芝 Semiconductor memory
US5566129A (en) * 1992-02-28 1996-10-15 Sony Corporation Semiconductor memory device with address transition detector
GB2277390B (en) * 1993-04-21 1997-02-26 Plessey Semiconductors Ltd Random access memory
KR100695512B1 (en) * 2005-06-30 2007-03-15 주식회사 하이닉스반도체 Semiconductor memory device

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52119160A (en) * 1976-03-31 1977-10-06 Nec Corp Semiconductor circuit with insulating gate type field dffect transisto r
JPS5432235A (en) * 1977-08-18 1979-03-09 Fujitsu Ltd Output timing measuring circuit of high impedance
US4150441A (en) * 1978-03-20 1979-04-17 Microtechnology Corporation Clocked static memory
US4272834A (en) * 1978-10-06 1981-06-09 Hitachi, Ltd. Data line potential setting circuit and MIS memory circuit using the same
JPS5634186A (en) * 1979-08-29 1981-04-06 Hitachi Ltd Bipolar memory circuit
GB2070372B (en) * 1980-01-31 1983-09-28 Tokyo Shibaura Electric Co Semiconductor memory device
JPS56165983A (en) * 1980-05-26 1981-12-19 Toshiba Corp Semiconductor storage device
JPS6055916B2 (en) * 1980-09-26 1985-12-07 日本電気株式会社 timing circuit
US4405996A (en) * 1981-02-06 1983-09-20 Rca Corporation Precharge with power conservation
JPS5819794A (en) * 1981-07-29 1983-02-04 Fujitsu Ltd Semiconductor memory
JPS58121195A (en) * 1982-01-13 1983-07-19 Nec Corp Producing circuit of precharging signal
JPS5963091A (en) * 1982-09-30 1984-04-10 Fujitsu Ltd Static memory circuit

Also Published As

Publication number Publication date
JPS60182096A (en) 1985-09-17
EP0155787B1 (en) 1991-01-09
DE3581223D1 (en) 1991-02-14
US4766571A (en) 1988-08-23
EP0155787A3 (en) 1987-11-25
EP0155787A2 (en) 1985-09-25
KR910000963B1 (en) 1991-02-19

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