KR870002697A - Clock signal generator for dynamic semiconductor memory - Google Patents

Clock signal generator for dynamic semiconductor memory Download PDF

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Publication number
KR870002697A
KR870002697A KR1019860006548A KR860006548A KR870002697A KR 870002697 A KR870002697 A KR 870002697A KR 1019860006548 A KR1019860006548 A KR 1019860006548A KR 860006548 A KR860006548 A KR 860006548A KR 870002697 A KR870002697 A KR 870002697A
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KR
South Korea
Prior art keywords
signal
clock signal
address strobe
strobe signal
address
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KR1019860006548A
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Korean (ko)
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KR900001806B1 (en
Inventor
시게끼 노자끼
Original Assignee
야마모도 다꾸마
후지쓰 가부시끼 가이샤
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Publication of KR870002697A publication Critical patent/KR870002697A/en
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Publication of KR900001806B1 publication Critical patent/KR900001806B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

내용 없음No content

Description

다이나믹형 반도체 기억장치용 클럭신호 발생회로Clock signal generator for dynamic semiconductor memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제8도는 본 발명의 실시예에 의한 다이나믹형 반도체 기억장치용 클록신호 발생회로.8 is a clock signal generation circuit for a dynamic semiconductor memory device according to an embodiment of the present invention.

제9도는 본 발명의 다른 실시예에 따른 다이나믹형 반도체 기억장치용 클록신호 발생회로.9 is a clock signal generation circuit for a dynamic semiconductor memory device according to another embodiment of the present invention.

제10도는 본 발명의 또 다른 실시예에 따른 다이나믹형 반도체 기억장치용 클록신호 발생회로.10 is a clock signal generation circuit for a dynamic semiconductor memory device according to another embodiment of the present invention.

Claims (6)

다이나믹형 반도체 기억장치용 클록신호 발생회로에 있어서, 어드레스 스트로브 신호를 전달하는 동안 트랜지스터-트랜지스터-논리(TTL)드라이브 레벨을 산화-금속-반도체(MOS)드라이브 레벨로 변환하는 입력전압 레벨 제어수단 ; 어드레스 스트로브 신호의 트레일링 에지에 응하여 어드레스 신호 및 반전된 어드레스신호를 발생시키는 어드레스 버퍼제어수단 ; 어드레스 스트로브 신호의 로레벨에 응하여 워드라인 선택에 사용되는 클록신호와 다음 단계를 위한 입력신호를 발생시키는 클록신호 발생수단 ; 및 어드레스 스트로브 신호가 클록신호의 리딩 에지 타이밍내의 하이레벨에 있을 때 클록신호에 의한 워드라인의 드라이브를 금지하는 금지 수단으로 구성되는 것을 특징으로 하는 다이나믹형 반도체 기억장치용 클록신호 발생회로.A clock signal generation circuit for a dynamic semiconductor memory device, comprising: input voltage level control means for converting a transistor-transistor-logic (TTL) drive level to an oxide-metal-semiconductor (MOS) drive level while transmitting an address strobe signal; Address buffer control means for generating an address signal and an inverted address signal in response to the trailing edge of the address strobe signal; Clock signal generation means for generating a clock signal used for word line selection and an input signal for the next step in response to the low level of the address strobe signal; And prohibiting means for prohibiting the drive of the word line by the clock signal when the address strobe signal is at a high level within the leading edge timing of the clock signal. 제1항에 있어서, 상기 금지수단은 어드레스 스트로브 신호를 반전하는 반전기와 클록신호 및 반전된 어드레스 스트로브 신호의 양자가 하이레벨로 됨에 의하여 워드라인 선택신호를 출력하는 AND게이트로 구성되는 것을 특징으로 하는 클록신호 발생회로.The method of claim 1, wherein the prohibiting means comprises an inverter for inverting the address strobe signal and an AND gate for outputting a word line selection signal because both the clock signal and the inverted address strobe signal become high level. Clock signal generation circuit. 제1항에 있어서, 상기 금지수단은 소정기간동안 어드레스 스트로브 신호의 하이레벨을 어드레스 스트로브 신호의 로레벨로 간주하기 위한 타임아웃 유닛, 및 클록신호 및 반전된 타임아웃 신호의 양자가 하이레벨인 경우에 워드라인 선택신호를 출력하는 AND게이트로 구성되는 것을 특징으로 하는 클록신호 발생회로.The timeout unit for considering the high level of the address strobe signal as the low level of the address strobe signal for a predetermined period, and when both the clock signal and the inverted timeout signal are high level. And an AND gate for outputting a word line selection signal to the clock signal generation circuit. 제1항에 있어서, 상기 금지수단은 소정기간동안 어드레스 스트로브 신호의 하이레벨이 어드레스 스트로브 신호의 로레벨로 간주하기 위한 타임아웃 유닛, 및 클록신호 및 반전된 타임아웃 신호의 두 하이레벨에 기하여 워드라인 선택신호를 출력하는 AND게이트, 및 어드레스 스트로브 신호를 반전하는 반전기로서 구성되는 것을 특징으로 하는 클록신호 발생회로.2. The prohibiting means according to claim 1, wherein the prohibiting means includes a timeout unit for considering the high level of the address strobe signal as the low level of the address strobe signal for a predetermined period, and a word based on two high levels of the clock signal and the inverted timeout signal. And a gate for outputting a line select signal and an inverter for inverting the address strobe signal. 제4항에 있어서, AND게이트로부터 나오는 상기 워드라인 선택신호가 타임아웃 회로로 귀환되는 것을 특징으로 하는 클록신호 발생회로.5. The clock signal generation circuit as claimed in claim 4, wherein the word line selection signal from the AND gate is fed back to the timeout circuit. 제1항에 있어서, 상기 능동 리스토어(restore) 신호가 금지회로에 귀환되는 것을 특징으로 하는 클록신호 발생회로.The clock signal generation circuit according to claim 1, wherein the active restore signal is fed back to a prohibition circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR8606548A 1985-08-14 1986-08-08 Clock signal generator for dynamic semiconductor memroy KR900001806B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP60-178963 1985-08-14
JP60178963A JPS6238593A (en) 1985-08-14 1985-08-14 Dynamic semiconductor storage device

Publications (2)

Publication Number Publication Date
KR870002697A true KR870002697A (en) 1987-04-06
KR900001806B1 KR900001806B1 (en) 1990-03-24

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KR8606548A KR900001806B1 (en) 1985-08-14 1986-08-08 Clock signal generator for dynamic semiconductor memroy

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US (1) US4739502A (en)
EP (1) EP0212945B1 (en)
JP (1) JPS6238593A (en)
KR (1) KR900001806B1 (en)
DE (1) DE3686926T2 (en)

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JPH0812760B2 (en) * 1986-11-29 1996-02-07 三菱電機株式会社 Dynamic memory device
JPH06101227B2 (en) * 1986-11-29 1994-12-12 三菱電機株式会社 Semiconductor memory device
JPH0197014A (en) * 1987-10-09 1989-04-14 Toshiba Corp Semiconductor integrated circuit
US5007022A (en) * 1987-12-21 1991-04-09 Texas Instruments Incorporated Two-port two-transistor DRAM
JP2818203B2 (en) * 1988-08-26 1998-10-30 株式会社東芝 Dynamic memory and dynamic memory system
US5157769A (en) * 1989-07-21 1992-10-20 Traveling Software, Inc. Computer data interface for handheld computer transfer to second computer including cable connector circuitry for voltage modification
EP1004956B2 (en) * 1990-04-18 2009-02-11 Rambus Inc. Method of operating a synchronous memory having a variable data output length
US6751696B2 (en) 1990-04-18 2004-06-15 Rambus Inc. Memory device having a programmable register
IL96808A (en) 1990-04-18 1996-03-31 Rambus Inc Integrated circuit i/o using a high performance bus interface
KR950010622B1 (en) * 1992-05-20 1995-09-20 삼성전자주식회사 Bit line sensing control circuit
US5504864A (en) * 1994-04-29 1996-04-02 Traveling Software, Inc. Low power-consumption interface apparatus and method for transferring data between a hand-held computer and a desk top computer
JPH09300152A (en) * 1996-05-13 1997-11-25 Nishida Kikai Kosakusho:Kk Machine tool
JP2008257868A (en) * 2008-07-30 2008-10-23 Texas Instr Japan Ltd Dynamic memory

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US4087704A (en) * 1974-11-04 1978-05-02 Intel Corporation Sequential timing circuitry for a semiconductor memory
US4060794A (en) * 1976-03-31 1977-11-29 Honeywell Information Systems Inc. Apparatus and method for generating timing signals for latched type memories
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JPS5956284A (en) * 1982-09-24 1984-03-31 Hitachi Micro Comput Eng Ltd Semiconductor storage device
JPS6066393A (en) * 1983-09-21 1985-04-16 Fujitsu Ltd Memory driving circuit
JPS6142797A (en) * 1984-08-06 1986-03-01 Nec Corp Dynamic semiconductor memory device

Also Published As

Publication number Publication date
EP0212945A2 (en) 1987-03-04
EP0212945A3 (en) 1989-11-02
KR900001806B1 (en) 1990-03-24
DE3686926D1 (en) 1992-11-12
EP0212945B1 (en) 1992-10-07
DE3686926T2 (en) 1993-02-18
US4739502A (en) 1988-04-19
JPS6238593A (en) 1987-02-19
JPH0520837B2 (en) 1993-03-22

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