KR980004998A - An initial pre-charge generator of the synchronous DRAM - Google Patents

An initial pre-charge generator of the synchronous DRAM Download PDF

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Publication number
KR980004998A
KR980004998A KR1019960025738A KR19960025738A KR980004998A KR 980004998 A KR980004998 A KR 980004998A KR 1019960025738 A KR1019960025738 A KR 1019960025738A KR 19960025738 A KR19960025738 A KR 19960025738A KR 980004998 A KR980004998 A KR 980004998A
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South Korea
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signal
node
inverter
precharge
bank
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KR1019960025738A
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Korean (ko)
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KR100225949B1 (en
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오학준
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김주용
현대전자산업 주식회사
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

본 발명은 싱크로너스 디램의 초기 프리차지 상태를 신속히 만들기 위하여 동작 전원전압이 인가된 후 기판바이어스 전압 발생장치에서 발생되는 기판바이어스 전압의 레벨을 감지하는 파워업 신호 발생기를 이용하여 싱크로너스 디램 내부의 각 뱅크들을 프리차지 시키는 펄스 신호를 자체적으로 발생시키는 외부에서 입력되는 프리차지 을 뱅크 코맨드와 동등한 효과를 갖게 하는 싱크로너스 포기 프리차지 발생 장치에 관한 것으로 상기 목적 달성을 위하여 클럭버퍼 수단과, 입력버퍼 및 코맨드 디코더 수단과, 뱅크 프리차지 신호 발생 수단과, 기판 바이어스 전압 발생 수단과, 파워업 발생 수단을 구비한다.The present invention relates to a method and apparatus for quickly generating an initial precharge state of a synchronous DRAM by using a power-up signal generator for sensing a level of a substrate bias voltage generated in a substrate bias voltage generator after an operation power source voltage is applied, The present invention relates to a synchronous aeration precharge generation device that has an effect equivalent to that of a bank command input to an externally input precharge circuit that generates a pulse signal for precharging the input buffer and the command decoder. A bank precharge signal generating means, a substrate bias voltage generating means, and a power up generating means.

Description

싱크로너스 디램의 초기 프리차지 발생장치An initial pre-charge generator of the synchronous DRAM

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제3도는 본 발명의 일실시예에 따른 싱크로너스 디램 초기 프리차지 발생 회로도.FIG. 3 is a circuit diagram of a synchronous DRAM initial precharge circuit according to an embodiment of the present invention; FIG.

Claims (3)

외부 클럭신호를 입력으로 하여 내부 클럭신호를 발생시키는 클럭버퍼 수단과, 상기 내부를 클럭신호 및 칩 선택신호, 로오 어드레스 스트로우브 신호, 컬럼 어드레스 스트로우브 신호 그리고 라이트 인에이블 신호 및 어드레스 신호를 입력으로 하여 싱크로너스 디램의 제반 코맨드들을 디코딩하는 입력버퍼 및 코맨드 디코더 수단과, 동작전원전압과 접지전압을 입력으로 하여 기판 바이어스 전압을 발생시키는기판 바이어스 전압 발생수단과, 상기 기판 바이어스 전압의 레벨을 감지하여 이를 펄스 형태의 신호로 발생시키는 파워업 신호 발생수단과, 상기 펄스 형태의 신호와 상기 입력버퍼 및 코맨드 디코더부의 출력신호들을 입력으로 하여 뱅크 프리차지 신호를 발생시키는 뱅크 프리차지 신호 발생수단을 포함하는 것을 특징으로 하는 싱크로너스 디램의 초기 프리차지 발생 장치.Clock buffer means for generating an internal clock signal with an external clock signal as an input, and a clock buffer means for receiving the clock signal and the chip select signal, the row address strobe signal, the column address strobe signal, the write enable signal, A substrate bias voltage generating means for generating a substrate bias voltage by receiving an operating power supply voltage and a ground voltage as inputs and an input buffer and command decoder for detecting the level of the substrate bias voltage, And a bank precharge signal generating means for generating a bank precharge signal by taking the pulse type signal and the output signals of the input buffer and command decoder as inputs Synchronous features The initial pre-charge generator of the SDRAM. 제1항에 있어서, 상기 뱅크 프리차지 신호 발생수단은 게이트로 내부 프리차지 명령신호가 인가되고 동작 전원전압과 제4 노드 사이에 접속된 제3 PMOS형 트랜지스터와, 게이트로 제4 인버터의 출력신호가 인가되고 상기 동작 전원전압과 상기 제4 노드 사이에 접속된 제4 PMOS형 트랜지스터와, 게이트로 뱅크 셀렉트 어드레스 신호가 인가되고 상기 제4 노드와 제5 노드 사이에 접속된 제4 NMOS형 트랜지스터와, 게이트로 프리차지 올 뱅크 플래그어드레스 신호가 인가되고 상기 제4 노드와 상기 제5 노드 사이에 접속된 제5 NMOS형 트랜지스터와, 게이트로 상부 내부 프리차지 명령 신호가 인가되고 상기 제5 노드와 접지전압 사이에 접속된 제6 NMOS형 트랜지스터와, 내부오토 프리차지 신호와 인에이블 뱅크 내부 프리차지 신호와 상기 제4 인버터의 출력신호와 제2 파워업 신호를 입력으로 하여 논리 연산된 값을 제6 노드로 출력하는 제2 노아 게이트와 상기 제2 노아 게이트의 출력신호를 반전시켜 제6 인버터의 입력단으로 출력하는 제5 인버터와, 상기 제5 인버터의 출력신호를 반전시켜 뱅크 프리차지 신호를 발생시키는 제6 인버터를 포함하는 것을 특징으로 하는 싱크로너스 디램 초기 프리차지 발생 장치.2. The semiconductor memory device according to claim 1, wherein the bank precharge signal generating means comprises: a third PMOS transistor having an internal precharge command signal applied thereto and connected between an operating power supply voltage and a fourth node; A fourth PMOS transistor connected between the fourth power supply voltage and the fourth node, a fourth NMOS transistor coupled between the fourth node and the fifth node to which a bank select address signal is applied, A fifth NMOS transistor to which a precharge all bank flag address signal is applied to the gate and which is connected between the fourth node and the fifth node and a fifth NMOS transistor connected between the fifth node and the fifth node, An internal precharge signal, an enable bank internal precharge signal, an output signal of the fourth inverter, and an internal precharge signal, A second inverter for inverting the output signal of the second NOR gate and outputting the inverted output signal to the input terminal of the sixth inverter, And a sixth inverter for inverting an output signal of the fifth inverter to generate a bank precharge signal. 제1항에 있어서, 상기 파워업 신호 발생수단은 게이트로 접지전압이 인가되고 동작 전압전원과 제7 노드 사이에 접속된 제5 PMOS형 트랜지스터와, 게이트로 상기 접지전압이 인가되고 상기 제7 노드와 기판 바이어스 전압 입력단자 사이에 접속된 제7 NMOS형 트랜지스터와, 상기 제7 노드상의 전압을 일정시간 지연시켜 제8 노드로 출력하는 직렬접속된 3개의 인버터와, 상기 제8 노드에 접속된 제1 파워업 신호와, 상기 제8 노드상의 신호를 반전시켜 제9 노드로 출력하는 제10 인버터와, 상기 제9 노드상으로 신호를 일정시간 지연시켜 제3 노아 게이트의 한 입력단자로 출력하는 직렬접속된 제11, 제12 인버터와, 상기 제12 인버터의 출력신호와 상기 제9 노드상의 출력신호를 논리 연산하여 제2 파워업 신호를 출력하는 제3 노아 게이트를 포함하는 것을 특징으로 하는 싱크로너스 디램 초기 프리차지 발생 장치.The power-up signal generator according to claim 1, wherein the power-up signal generating means comprises: a fifth PMOS transistor having a gate to which a ground voltage is applied and connected between a seventh node and an operating voltage power supply; And a sixth NMOS transistor connected between the substrate bias voltage input terminal and the substrate bias voltage input terminal, three inverters connected in series for delaying the voltage on the seventh node to an eighth node for a predetermined time, A first inverter for inverting a signal on the eighth node and outputting the inverted signal to the ninth node, a serial inverter for delaying the signal on the ninth node by a predetermined time and outputting the inverted signal to one input terminal of the third N0 gate, And a third Noah gate for outputting a second power-up signal by logically computing an output signal of the twelfth inverter and an output signal of the ninth node, Synchronous DRAM initial pre-charge generator. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960025738A 1996-06-29 1996-06-29 Precharge generating circuit of synchronous dram KR100225949B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100557538B1 (en) * 1999-06-29 2006-03-03 주식회사 하이닉스반도체 Command decording device of a SDRAM

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100924356B1 (en) 2008-06-05 2009-11-02 주식회사 하이닉스반도체 Command decoder and command signal generating circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100557538B1 (en) * 1999-06-29 2006-03-03 주식회사 하이닉스반도체 Command decording device of a SDRAM

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