KR100225949B1 - Precharge generating circuit of synchronous dram - Google Patents

Abstract

The present invention uses a power-up signal generator that detects the level of the substrate bias voltage generated by the substrate bias positive voltage generator after an operating power supply voltage is applied to quickly create an initial precharge state of the synchronous DRAM. The present invention relates to a synchronous initial precharge generating device which generates a pulse signal for precharging the signals by itself and has an effect equivalent to a precharge all bank command inputted from the outside. The present invention relates to a clock buffer means, an input buffer and a command decoder. Means, a bank precharge signal generating means, a substrate bias voltage generating means, and a power-up generating means.

Description

Initial precharge generator of synchronous DRAM

1 is a synchronous DRAM initial precharge circuit diagram according to the prior art.

2 is an operation timing diagram illustrating the precharge process of FIG. 1.

3 is a synchronous DRAM initial precharge circuit proposed in the present invention.

FIG. 4 is a detailed circuit diagram of the power up generator shown in FIG.

5 is an operation timing diagram illustrating the precharge process of FIG.

* Explanation of symbols for main parts of the drawings

1, 4: clock buffer section 2, 5: input buffer and command decoder section

3, 6: bank precharge signal generator 7: substrate bias voltage generator

8: Power up generator CLK, CKE: External clock signal

φICLK: Internal clock signal

φAPCG: Internal automatic precharge signal

φREFR: Enable bank internal precharge signal

φPRE: Internal precharge command signal φBSA: Bank select address signal

φPALLA: Precharge all bank flag address signal

φRAS-PCG: Bank precharge signal φPWRUP-P: Second power-up signal

φPWRUP: first power-up signal

The present invention relates to a synchronous synchronous DRAM, and more particularly, when an operating power supply voltage is initially applied and the substrate bias voltage drops below a predetermined potential level, the present invention detects the synchronous synchronous DRAM to quickly precharge the synchronous DRAM to generate the precharge process. The present invention relates to a precharge generator for reducing power consumption and facilitating a chip test process.

Synchronous DRAM (SDRAM) is a memory device that operates in synchronization with an external clock (CLOCK), it is required to stabilize the chip by sequentially inputting external commands after the operating power supply voltage (VDD) is initially applied.

This is commonly referred to as a power-on sequence, which includes a precharge all bank command, eight or more auto refresh commands, and a mud register set command. Command) and the like.

Meanwhile, the synchronous DRAM must maintain a No Operation state of 200 ms or more on the basis of the clock clock stabilized after the operation power supply voltage VDD is applied before all the commands COMMAND are input.

In particular, since all operations of the synchronous DRAM (SDRAM) are performed in a precharge state, the initial pre-autonomous configuration by the precharge all bank command is very important.

1 is a conventional circuit diagram illustrating an initial precharge relationship of a synchronous DRAM.

As shown in FIG. 1, the conventional precharge device performs a precharge operation from the bank precharge signal? RAS-PCG generated by a precharge command input from the outside.

Specifically, the clock buffer unit 1 receives the external clock signals CLK and CKE to generate the internal clock signal φICLK, and the input buffer and the command decoder unit 2 are connected to the internal clock signal φICLK. Input chip select signal (/ CS), low address strobe signal (/ RAS), column address strobe signal (/ CAS), write enable signal (/ WE), and address signal (ADD) input from outside the chip. Outputs an internal automatic precharge signal (φAPCG), an enable bank internal precharge signal (φREFR), an internal precharge command signal (φPRE), a bank select address signal (φBSA) and a precharge all bank flag address signal (φPALLA) do.

Subsequently, the bank precharge signal generator 3 generates the bank precharge signal φRAS-PCG by inputting the internal precharge command signal φPRE and the precharge all bank flag address signal φPALLA to generate a synchronous DRAM. Precharge initially.

Here, the bank precharge signal generator 3 may include a first PMOS transistor having a precharge command signal? PRE applied to a gate and connected between an operating power supply voltage VDD and a first node N1. MP1), a second PMOS transistor MP2 connected to the first inverter IV1 output potential and connected between the operating power supply voltage VDD and the first node N1, and a gate. A first NMOS transistor MN1 connected to the first node N1 and the second node N2 and a gate precharge all bank flag address signal φPALLA is applied to the bank selection address signal φBSA. ) Is applied and the second NMOS transistor MN2 connected between the first node N1 and the second node N2 and an internal precharge command signal φ PRE are applied to the gate and the second node A third NMOS transistor MN3 connected between the terminal N2 and the ground voltage VSS, and a first node; Logic operation of the first inverter IV1 for inverting and outputting the potential on the N1, the internal automatic precharge signal? APCG, the enable bank internal precharge signal? REFR, and the output potential of the first inverter IV1; A first node (NR1) for outputting a predetermined potential to the third node (N3) and a serially connected second for inverting the output potential on the third node (N3) to generate a bank precharge signal (φRAS-PCG) It consists of two inverters IV2 and a third inverter IV3.

Here, the internal automatic precharge signal φ APCG is a signal obtained by internally decoding an automatic precharge command of a synchronous DRAM (SDRAM), and the enable bank internal precharge signal φREFR is a synchronous DRAM an automatic refresh command or a self refresh command. When the refresh operation is performed by the refresh operation, the refresh operation is performed for a predetermined time by its own delay signal within the synchronous DRAM, and then a signal is performed to automatically precharge the enabled bank, and an internal precharge command signal. (PRE) is a signal obtained by internally decoding a bank precharge command of a synchronous DRAM.

The bank selection address signal φ BSA is a clock-synchronized internal decoding signal of a bank selection address input simultaneously with the bank precharge command, and the precharge all bank flag address signal φ PALLA is an all bank input simultaneously with the bank precharge command. This is a clock-synchronized internal decoding signal of the precharge flag address.

Hereinafter, a conventional precharge operation will be described with reference to the operation timing diagram shown in FIG. 2.

When the precharge all bank command is input to the synchronous DRAM, the input buffer and the command decoder 2 generate an internal precharge command signal? PRE and a precharge all bank flag address signal? PALLA.

At this time, the two signals have a positive pulse shape as shown in FIG.

As a result, the first PMOS transistor MP1 of the bank precharge signal generator 3 is turned off and the third NMOS transistor MN3 is turned on.

The second NMOS transistor MN2 is also turned on by the precharge all bank flag address signal? PALLA, so that the potential level on the first node N1 becomes logic low.

The logic low on the first node N1 is inverted by the first inverter IV1, and the logic high, which is the inversion signal, is applied to an input terminal of one side of the first NOR gate NR1.

Accordingly, a logic low is output to the first NOR gate NR1 output terminal regardless of the potential level of the other input signal, and finally, the bank precharge signal of the logic low is passed through the second and third inverters IV2 and IV3. Precharge operation of synchronous DRAM (SDRAM) is performed by outputting φRAS-PCG.

FIG. 2 illustrates the precharge process of the synchronous DRAM.

When the operating power supply voltage VDD transitions from logic low to logic high, and CKE remains logic high, the chip select signal (/ CS) is applied when one cycle of the external clock CLK transitions from logic low to logic high. ) And the row address strobe signal (/ RAS) and the write enable signal (/ WE) are combined with the column address strobe signal (/ CAS) and the logic low during the set-up and hold time. When the address signal ADD has logic high for a defined setup time and hold time, the synchronous DRAM recognizes the precharge all bank command.

For this reason, in order for the synchronous DRAM to perform the precharge operation stably after the initial operating power supply voltage is applied, the stable external clock signal and the command of the No Operation state must be maintained for 200 ms, and the precharge all bank You must enter the command externally.

This increases the time required for the precharge operation and increases the power consumption since the precharge all bank command must be externally applied.

The present invention was devised to solve such a conventional problem, and detects that the substrate bias voltage drops below a certain level after the operation power supply voltage is applied, thereby generating a power-up signal that is involved in the precharge operation of the synchronous DRAM. Therefore, the object of the present invention is to provide a precharge generator of a synchronous DRAM to reduce precharge operation time and power consumption.

Synchronous DRAM initial precharge generation device of the present invention for achieving the above object is a clock buffer for buffering the internal clock in response to the external clock, and an input buffer and command decoder unit for decoding and outputting the external command in synchronization with the internal clock And a bank precharge signal generator for outputting a bank precharge signal in response to the decoded outputs of the input buffer and the command decoder unit, comprising: a substrate bias voltage generating means and an operating power supply; And a power-up generating means for sensing the voltage drop of the substrate bias voltage after generating the voltage to generate a power-up signal for controlling the bank precharge signal generator, thereby performing a precharge operation of the synchronous DRAM.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

FIG. 3 is a synchronous DRAM initial precharge generation circuit proposed by the present invention. The clock buffer unit 4 receives the external clocks CLK and CKE and buffers the internal clock φICLK, and the internal clock φICLK and Internal automatic precharge signal by receiving chip select signal (/ CS), row address strobe signal (/ RAS), column address strobe signal (/ CAS) and write enable signal (/ WE) and address signal (ADD) Input buffer and command decoder for outputting (φAPCG), enable bank internal precharge signal (φREFR), internal precharge command signal (φPRE), bank selection address signal (φBSA) and precharge all bank flag address signal (φPALLA) The substrate bias voltage generator 7 which receives the unit 5, the operating power supply voltage VDD and the ground voltage VSS, and generates the substrate bias voltage VBB, and the level of the substrate bias voltage VBB Detect power up signal A power up generator 8 for outputting and a bank precharge signal generator 6 for outputting a bank precharge signal in response to the decoding output of the power up signal, the input buffer and the command decoder 5. .

The bank precharge signal generator 6 receives an internal precharge command signal? PRE as a gate and is connected to a third PMOS transistor MP3 connected between the operating power supply voltage VDD and the fourth node N4. A fourth PMOS transistor MP4 connected between the operating power supply voltage VDD and the fourth node N4, and a bank selection address as a gate; A signal φBSA is applied and a fourth NMOS transistor MN4 connected between the fourth node N4 and the fifth node N5 and a precharge all-bank flag address signal φPALLA are applied to the gate. And a fifth NMOS transistor MN5 connected between the fourth node N4 and the fifth node N5, an internal precharge command signal φ PRE is applied to a gate, and the fifth node N5. ), A sixth NMOS transistor MN6 connected between the ground voltage VSS terminal, and an internal automatic precharge A predetermined output potential to the sixth node N6 by performing a logical operation on the signal? APCG, the enable bank internal precharge signal? REFR, the output potential of the fourth inverter IV4, and the power up signal? PWRUP-P. The fifth and sixth inverters IV5 connected in series to generate a bank precharge signal φRAS-PCG by delaying the second noacetate NR2 for generating a voltage and the output potential of the second noah gate NR2 for a predetermined time. , IV6).

Here, the third and fourth PMOS transistors MN3 and MN4, the fourth, fifth and sixth NMOS transistors MN4, MN5 and MN6 and the first inverter IV1 are referred to as logic circuits for convenience. The second NOR gate NR2, the fifth inverter IV5, and the sixth inverter IV6 are referred to as logic gate circuits.

As shown in FIG. 4, the power-up generator 8 is applied with a ground voltage VSS to a gate, and is connected to a fifth PMOS transistor connected between an operating power supply voltage VDD and a seventh node N7. A sensing unit comprising a seventh NMOS transistor MN7 connected to an input terminal MP5 and a ground voltage VSS, and connected between the seventh node N7 and the substrate bias voltage VBB input terminal; A first delay unit comprising three inverters IV7, IV8, and IV9 connected in series to invert the first power-up signal? PWRUR to the eighth node N8 after delaying the potential on the seven node N7; And an inverting unit comprising a tenth inverter IV10 for inverting and outputting the first power-up signal? PWRUR to the ninth node N9, and inverting the output potential on the ninth node N9 after a predetermined time delay. A second delay part comprising an eleventh, twelfth, and thirteenth inverters IV11, IV12, and IV13 connected in series, an output potential of the second delay part, and a ninth node N9. Claim to a logic operation to the output potential and outputting a second power-up signal (φPWRUP-P) 3 is composed of a logic gate consisting of a NOR gate (NR3).

Hereinafter, the operation relationship of FIG. 4 will be described with reference to the operation timing diagram shown in FIG. 5.

First, when the potential level of the substrate bias voltage VBB is 0V, the seventh NMOS transistor MN7 is turned off.

Since the gate is connected to the ground potential terminal of the fifth PMOS transistor MP5, the seventh node N7 has a logic high.

Accordingly, the power-up generator 8 outputs the logic low first power-up signal φ PWRUP and the second power-up signal φ PWRUP-P.

On the other hand, when the substrate bias voltage VBB drops below the predetermined potential level after the operating power supply voltage VDD is applied as shown in FIG. 5, that is, the seventh NMOS type. The transistor MN7 is low enough to turn on, and the seventh node N7 transitions from logic high to logic low so that the first power-up signal φ PWRUP transitions to logic high.

The generated first power-up signal φ PWRUP is input to main circuits inside the device to determine an initial state, and prepares the device to receive an external command.

Next, the logic high first power-up signal φ PWRUP is inverted and output by the tenth inverter IV10 and applied to one input terminal of the third NOR gate NR3.

In addition, the logic low, which is an output of the tenth inverter IV10, is delayed by the eleventh, twelfth, and thirteenth inverters IV11, IV12, and IV13, and is then inverted and input to the other terminal of the third NOR gate NR3.

Accordingly, the second power up signal? PWRUP-P as shown in FIG. 5 is generated at the output terminal of the third NOR gate NR3, so that the second NOR gate NR2 of the bank precharge signal generator 6 is generated. To control.

As a result, a logic low is always output to the second NOR gate NR2 output regardless of the decoding output of the input buffer and the command decoder.

As a result, a logic low bank precharge signal? RAS-PCG is finally output through the fifth and sixth inverters IV5 and IV6 to initially charge the synchronous DRAM.

As described above, the present invention, unlike the conventional precharge device which precharges the synchronous DRAM by inputting the precharge all bank command by the external input pins after a predetermined time has elapsed, the operating power supply voltage VDD is applied. After the substrate bias voltage VBB is detected to be lowered to a predetermined potential level, a pulse signal is generated within the synchronous DRAM and used for precharging, thereby enabling all-bank precharge operation in a short time. .

As described above, when the synchronous DRAM initial precharge generator of the present invention is implemented in a memory device using a substrate bias voltage, a separate precharge all bank command is not required, thereby reducing time and power consumption.

The present invention is applicable to a memory device which is internally bank distinguished and synchronized by a clock.

Preferred embodiments of the present invention are for purposes of illustration and various modifications, changes, substitutions and additions are possible to those skilled in the art through the spirit and scope of the invention as set forth in the appended claims.

Claims (5)

A clock buffer for buffering and outputting an internal clock in response to an external clock, an input buffer and a command decoder for decoding and outputting an external command in synchronization with the internal clock, and a bank in response to decoding outputs of the input buffer and the command decoder An initial precharge generator of a synchronous DRAM including a bank precharge signal generator for outputting a precharge signal, the apparatus comprising: a substrate bias voltage generating means and a voltage drop of the substrate bias voltage after sensing an operating power supply voltage; And a power-up generating means for generating a power-up signal for controlling the charge signal generation unit to perform a precharging operation of the synchronous DRAM. The method of claim 1, wherein the bank precharge signal generating means comprises: a logic circuit for outputting a predetermined potential in response to predetermined decoding outputs of the input buffer and the command decoder unit during a precharge operation; And a logic gate means for outputting a bank precharge signal for performing a precharge operation by logically decoding a decoding output and the power-up signal. 2. The apparatus of claim 1, wherein the power-up generating means comprises: sensing means for sensing a voltage drop of the substrate bias voltage after application of an operating power supply voltage, first delay means for inverting and outputting an output potential of the sensing means; A logical combination of an inverting means for inverting and outputting the output potential of the first delaying means, a second delaying means for inverting and outputting the output potential of the inverting means after a delay, an output potential of the inverting means and an output potential of the second delaying means And logic gate means for generating a power-up signal. 4. The synchronous DRAM initial precharge generator of claim 3, wherein the sensing means comprises two MOS transistors connected in series. 4. The synchronous DRAM initial precharge generator of claim 3, wherein the logic gate means comprises a noble gate.