KR0135686B1 - Write control signal generating circuit in memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for generating a light control signal of a semiconductor device. In particular, an on-chip light signal generated inside a chip during a write cycle is turned off and a column decoder is turned off. The present invention relates to a write control signal generation circuit which reduces the cycle time by allowing the light to proceed internally during the precharge (RAS) by using it to enable.

Description

Write Control Signal Generation Circuit of Memory Device

1 is a circuit diagram showing an example of a conventional light control signal generation circuit.

2 is an operation timing diagram of a conventional write control signal generation circuit.

3 is a light control signal generation circuit diagram according to the present invention.

4 is an operation timing diagram of the write control signal generation circuit according to the present invention.

* Description of the symbols for the main parts of the drawings *

RASB: row address strobe signal,

CASB: column address strobe signal, ØWLCB: word line off signal,

Øsg: Sense Amplifier Enable Signal, ØCSB: Column Cycle Start Signal,

yi: Bit line select signal, WEB: Light enable signal,

ØWYGB: chip internal write signal, 11: word line off signal generator,

12: bit line selection signal generator,

13: column cycle start signal generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light control signal generation circuit of a semiconductor device. In particular, a write signal ØWYGB made in a chip cIP during a write cycle is turned off and a column decoder is turned off. The present invention relates to a write control signal generation circuit which shortens a cycle time by enabling writing internally in a chip when precharging (RASB) is high by use of an E.

The present invention can be applied to all semiconductor memory devices such as DRAM, SRAM, and ROM.

1 illustrates an example of a conventional write control signal generation circuit, and uses a low address strobe signal (hereinafter referred to as "RASB") at the end of a read or write cycle. Receiving a column cycle start signal (ØCSB) by receiving a logic circuit consisting of a plurality of inverters and a NOA gate generating a word line off signal (ØWLCB), a sense amplifier enable signal (Øsg), and the row address strobe signal (RASB). A plurality of inverters for generating a plurality of inverters and a NAND gate, a plurality of inverters for generating a bit line selection signal yi by receiving the column cycle start signal ØCSB and a column decoder output signal; It consists of a logic circuit composed of NAND gates.

Hereinafter, an operation relationship of the conventional light control signal generation circuit having the above configuration will be described with reference to the operation timing diagram shown in FIG.

The word line off signal ØWLCB transitions to “high” when the row address strobe signal RASB is enabled, turning the word line on to turn the word line on to full Vcc. After storing the Vss and the row address strobe signal (RASB) is disabled, the transition to the "low" level to maintain the word line turned on for a period of time to turn off (Turn Off).

The column cycle start signal ØCSB is enabled after the row address strobe signal RASB is enabled so that the sense amplifier enable signal Øsg is enabled to select data of the bit line corresponding to the output of the column decoder. The bit line select signal yi is enabled so that the bit address select signal yi is disabled and immediately disabled after the row address strobe signal RASB is disabled.

The operation timing diagram of FIG. 2 shows the operation of the circuit and the operation at the time of writing. The chip internal write signal ØWYGB generated by the write enable signal WEB indicating the write operation is the write enable signal WEB. ) Is enabled by the column address strobe signal (CASB) in the enabled state (Vss), and remains enabled for the time required for the write operation. Vcc).

At this time, if the row address strobe signal RABB is disabled during the write operation, that is, before the write data is sufficiently transmitted to the cell, the word line is turned off (Vss) while the data is written to the cell. State, which prevents write data from being delivered to the cell.

Therefore, to prevent this, the disable operation of the row address strobe signal RASB should occur after the time required for the write operation after the column address strobe signal CASB is enabled.

This delays the enable state of the row address strobe signal RABB, resulting in an increase in the write cycle time.

Accordingly, the present invention uses a chip-in-write signal ØWYGB made inside the chip by the write enable signal pad WEB PAD input in the semiconductor memory device to turn off the word line and to enable the column decoder, thereby precharging the chip. The circuit is implemented to reduce the write cycle time by proceeding the write operation in the state (RASB High).

3 is a circuit diagram of a write control signal generation according to the present invention, and receives a word address off signal by receiving a row address strobe signal RASB and a chip internal write signal ØWYGB at the end of a read or write cycle. A column cycle for generating a column cycle start signal ØCSB by receiving a word line off signal generator 11 generating a ØWLCB, a sense amplifier enable signal Øsg, and the row address strobe signal RASB. A bit line selection for generating a bit line selection signal yi by receiving a start signal generator 13, the column cycle start signal ØCSB, an internal chip write signal ØWYGB, and a column decoder output signal. It comprises a signal generation part 12.

The word line off signal generator 11 may include a first inverter IV1 for inverting the received row address strobe signal RASB and a second inverter IV2 for inverting the received chip internal write signal ØWYGB. And a NOR gate receiving the first inverter IV1 output signal and the second inverter IV2 output signal, and connected in series with the NOR gate NR output terminal to delay the NOR gate NR output signal for a predetermined time. Third, fourth, fifth, and sixth inverters IV3, IV4, IV5, and IV6, a first NAND gate that receives the Noah gate NR output signal, and the sixth inverter output signal, and the first The seventh and eighth inverters IV7 and IV8 are connected in series to the NAND gate ND1 output terminal and output a word line off signal ØWLCB.

The column cycle start signal generator 13 receives the sense amplifier enable signal Øsg and receives the serially connected ninth and tenth inverters IV9 and IV10 for delaying a predetermined time and the row address strobe signal RASB. ) Is connected in series to an eleventh inverter IV11 for receiving and inverting the second inverter, a second NAND gate receiving the tenth inverter output signal and an eleventh inverter IV11 output signal, and an output terminal of the second NAND gate ND2. And the twelfth and thirteenth inverters IV12 and IV13 generating the column cycle start signal ØCSB.

The bit line selection signal generation 12 may include a third NAND gate configured to receive the column cycle start signal ØCSB and an internal chip write signal ØWYGB, and a fourth NAND gate serially connected to an output terminal of the third NAND gate ND3. And a bit line selection signal yi connected in series with the fifteenth inverters IV14 and IV15, a fourth NAND gate receiving the fifteenth inverter output signal and the column decoder output signal, and an output terminal of the fourth NAND gate ND4. And the sixteenth and seventeenth inverters IV16 and IV17 for generating ().

As in the prior art, the word line off signal ØWLCB is a signal for turning off the word line (Vss). The word line off signal generator 11 proposed in the present invention is a row address strobe signal RASB and a chip internal write signal. It receives (ØWYGB) as an input and sends the wordline off signal to the output.

Therefore, if the low address strobe signal RASB is disabled (high state) while the write is in progress, the word line off signal ØWLCB is high because the chip internal write signal ØWYGB is enabled (low). To keep the selected word line high and then write the chip internal write signal (Ø) after the write operation is completed.

WYGB) is disabled (high) to turn off the word line (Vss).

The bit line selection signal generator 12, which generates the bit line selection signal yi for selecting the bit line corresponding to the column address, also inputs the column cycle start signal ØCSB and the chip internal write signal ØWYGB unlike the prior art. Accept as a signal

When the row address strobe signal RASB is disabled, the column cycle signal ØCSB is disabled (high), but the chip internal write signal ØWYGB remains enabled (low) during the write operation. The bit line selection signal generator 12, which generates the bit line selection signal yi by the signal ØWYGB, is kept turned on so that the data signal input to the data line passes through the bit line. To be stored in.

4 is an operation timing diagram of the write control signal generation circuit according to the present invention, in which the column address strobe signal CASB and the write enable signal WEB are enabled when the row address strobe signal RASB is enabled. When the address strobe signal RASB is disabled after the write operation is started, the word line off signal ØWYCB does not go low due to the low address strobe signal RASB. By keeping it high, the word line can be left in an enabled (high) state so that data can be stored in the cell.

When the row address strobe signal RASB is disabled (high) while the write operation is in progress, the word line is not turned off by the row address strobe signal RASB. ØWYGB) goes high (Vcc) to turn off the word line.

Therefore, since the column address strobe signal CASB is enabled, there is no restriction on the time for which the row address strobe signal RABS is disabled, and thus the cycle time may be reduced during the write cycle.

When the light control signal generation circuit of the present invention described above is used, the word line is turned off by using the chip internal light signal generated inside the chip during the write cycle, thereby enabling the internal write during precharging to reduce the write cycle time. It works.

Claims (4)

Receives a row address strobe signal (RASB) and a chip internal write signal (ØWYGB) and is enabled by the enable of the address strobe signal (RASB), and the chip internal write signal (ØWYGB) in an enabled state. Word line off signal generating means for disabling by disabling and outputting a word line off signal (ØWLCB) for turning off the word line, the row address strobe signal (RASB) and sense amplifier enable signal (Øsg); Column cycle start signal generation means for receiving the column cycle start signal ØCSB which is disabled by the disable of the row address strobe signal RASB in the enabled state, and the column cycle start signal. Receives the (ØCSB) and the chip internal write signal (ØWYGB) and the column decoder output signal, and the column cycle start signal (ØCSB). A bit line that is enabled by an enable and disabled by the disable of the chip internal write signal ØCYGB in an enabled state, and outputs a bit line selection signal yi for turning off a predetermined bit line And a selection signal generating means. 2. The write control signal generation circuit of a memory device according to claim 1, wherein said word line off signal generating means comprises a plurality of inverters and a plurality of logic gates. 2. The write control signal generation circuit of a memory device according to claim 1, wherein said column cycle start signal generating means comprises a plurality of inverters and a plurality of logic gates. 2. The write control signal generating circuit of a memory device according to claim 1, wherein the bit line selection signal generating means comprises a plurality of inverters and a plurality of logic gates.