KR100933801B1 - Ring Oscillator and Internal Voltage Generator - Google Patents

Abstract

The present invention provides a ring oscillator comprising an inverted delay loop, comprising: a plurality of delay means for providing a delay time corresponding to a pulse width of an oscillation signal, and skew detection for generating a skew information signal by detecting skew according to a process change. Means and a switching means for selectively including a portion of said plurality of delay means in said inversion delay loop in response to said skew information signal.

Description

RING OSCILLATOR AND INTERNAL VOLTAGE GENERATOR USING SAME}

1 is a block diagram illustrating a general substrate bias voltage generator.

FIG. 2 is a circuit diagram illustrating the ring oscillator of FIG. 1. FIG.

3 is a circuit diagram for explaining a ring oscillator according to the present invention.

FIG. 4 is a circuit diagram illustrating the skew detector of FIG. 3. FIG.

5 is a circuit diagram illustrating a ring oscillator of the substrate bias voltage generator according to the present invention.

* Explanation of symbols for the main parts of the drawings

310: first delay unit 330: second delay unit

350: third delay unit 370: skew detection unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to a ring oscillator of a semiconductor device and an internal voltage generator using the same.

BACKGROUND ART In general, semiconductor devices including DDR SDRAM (Double Data Rate Synchronous DRAM) are equipped with an internal voltage generator, and internally generate and use an internal voltage required for internal circuit operation.

As the internal voltage, a boosting voltage (VPP) having a voltage level higher than the external voltage (VDD), a substrate via voltage (VBB) having a voltage level lower than the ground voltage (VSS), and an external voltage And a core voltage VCORE having a voltage level between VDD and a ground voltage VSS, a ferry voltage VPERI, and the like. Here, the substrate bias voltage VBB may be applied to the P-Well surrounding the NMOS transistor to be used to prevent a partial forward bias of the PN junction.

Meanwhile, the boost voltage VPP and the substrate bias voltage VBB are generally generated through a charge pumping operation, and the internal voltage generators generating the two voltages have similar configurations.

1 is a block diagram illustrating a general substrate bias voltage generator.

Referring to FIG. 1, the substrate bias voltage generator includes a voltage detector 110, a ring oscillator 130, and a voltage pumping unit 150 to generate a substrate bias voltage VBB.

The voltage detector 110 receives the reference voltage VREF and the substrate bias voltage VBB fed back, detects the voltage level of the substrate bias voltage VBB corresponding to the voltage level of the reference voltage VREF, and detects the detected voltage level. Output as (DET_V).

For example, when the voltage level of the substrate bias voltage VBB is higher than the voltage level of the reference voltage VREF, the logic signal 'low' detection signal DET_V for enabling the ring oscillator 130 is output. When the voltage level of the substrate bias voltage VBB is lower than the voltage level of the reference voltage VREF, the logic signal 'high' detection signal DET_V for disabling the ring oscillator 130 is output. .

The ring oscillator 130 generates an oscillation signal OSC having a predetermined frequency in response to the detection signal DET_V output from the voltage detector 110. Thus, the ring oscillator 130 generates an oscillation signal OSC having a predetermined frequency through an oscillation operation when the detection signal DET_V is activated, and stops the oscillation operation when the detection signal DET_V is inactivated.

The voltage pumping unit 150 generates the substrate bias voltage VBB through a pumping operation in response to the oscillation signal OSC, and the generated substrate bias voltage VBB is fed back to the voltage detector 110.

The substrate bias voltage generator generates the desired substrate bias voltage VBB through such an operation.

FIG. 2 is a circuit diagram illustrating the ring oscillator 130 of FIG. 1.

Referring to FIG. 2, the ring oscillator 130 receives an oscillation signal OSC fed back and an activation unit 132 for activating the ring oscillator 130 in response to a detection signal DET_V and an oscillation signal OSC. And a delay unit 134 for providing a delay time corresponding to the pulse width.

The activator 132 generates an oscillation signal OSC that is fed back when the detection signal DET_V is logic 'low', that is, when the voltage level of the substrate bias voltage VBB is higher than the voltage level of the reference voltage VREF. Invert the output.

The delay unit 134 reflects a predetermined delay time in the output signal of the activator 132 and outputs the oscillation signal OSC.

For example, it is assumed that the delay time provided by the four inverters INV1, INV2, INV3, and INV4 constituting the delay unit 134 is 4 ns without considering the delay time of the XOR gate of the activation unit 132. The signal OSC will have a pulse width of 4 ns. That is, the oscillation signal OSC has a constant half cycle of 4 ns.

On the other hand, the inverter is generally composed of an NMOS transistor and a PMOS transistor, the operation speed of such a component may vary depending on the process state.

Hereinafter, for convenience of description, process states are divided into TYPICAL, FAST, and SLOW.

TYPICAL means that the operating speed of NMOS transistor and PMOS transistor is typical, FAST means that the operating speed of NMOS transistor and PMOS transistor is faster than standard, and SLOW means NMOS transistor and PMOS transistor. This means that the operating speed of is slower than the standard.

Therefore, even if the delay unit 134 is designed to generate the oscillation signal OSC having a constant frequency, the pulse width is changed according to the process change, that is, TYPICAL, FAST, and SLOW, so that the frequency of the oscillation signal OSC is changed. Can be. This means that the voltage pumping unit 150 may not perform the pumping operation in an optimal state in preparation for the initial design target value.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide an oscillator capable of generating an oscillation signal having a constant frequency regardless of a process change.

Another object is to provide an internal voltage generator capable of generating a stable internal voltage by performing a constant pumping operation regardless of a process change.

According to an aspect of the present invention for achieving the above object, a ring oscillator comprising an inversion delay loop, a plurality of delay means for providing a delay time corresponding to the pulse width of the oscillation signal; Skew detection means for generating a skew information signal by detecting a skew according to a process change; And switching means for selectively including a part of the plurality of delay means in the inversion delay loop in response to the skew information signal.

According to another aspect of the present invention for achieving the above object, the voltage detection means for detecting the internal voltage corresponding to the reference voltage; A ring oscillator having an inverted delay loop and configured to generate an oscillation signal in response to a detection signal which is an output signal of the voltage detection means; And a voltage pumping means for generating the internal voltage corresponding to the oscillation signal, wherein the ring oscillator comprises: an activation unit for activating the ring oscillator in response to the detection signal; A plurality of delay units for providing a delay time corresponding to the pulse width of the oscillation signal; A skew detector for generating a skew information signal by detecting a skew according to a process change; And a switching unit for selectively including a part of the plurality of delay means in the inversion delay loop in response to the skew information signal.

The present invention can generate an oscillation signal having a constant frequency at all times by detecting a skew according to a process change and adjusting the pulse width of the oscillation signal using the same. In addition, the internal voltage generator having such an oscillator may generate a stable internal voltage through an optimal pumping operation.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

3 is a circuit diagram illustrating a ring oscillator according to the present invention.

Referring to FIG. 3, a ring oscillator having an inverted delay loop includes a plurality of inverters and includes first to third delay units 310 for providing a delay time corresponding to a pulse width of an oscillation signal OSC. 330 and 350, a skew detector 370 for generating a skew information signal DET_SQ by detecting skew according to a process change, and first and second delay units 310 in response to the skew information signal DET_SQ. , 330 may be provided with a switching unit 390 for selectively including any one of the inversion delay loop.

The first and second delay units 310 and 330 provide a delay time corresponding to the pulse width of the oscillation signal OSC, and the third delay unit 350 inverts the oscillation signal OSC fed back. It is for.

The skew information signal DET_SQ is a signal having information about a process state, that is, TYPICAL, FAST, and SLOW, which will be described with reference to FIG. 4.

The switching unit 390 may include an NMOS transistor NM1 having a source-drain path formed between an input terminal and an output terminal of the first delay unit 310 and receiving a skew information signal DET_SQ as a gate. Therefore, the input terminal and the output terminal of the first delay unit 310 may be connected or separated according to the skew information signal DET_SQ.

Thus, the second delay unit 330 receives the output signal of the first delay unit 310 or the output signal of the third delay unit 350 according to the skew information signal DET_SQ to reflect the delay time. do.

For convenience of description, the delay time reflected by the third delay unit 350 will not be considered.

If the desired pulse width is set to 4 ns, it is assumed that the delay time provided from the first and second delay units 310 and 330 is 2 ns, respectively.

In this case, when the process state becomes SLOW and a delay time of 4 ns is provided in the first and second delay units 310 and 330, respectively, the NMOS transistor is configured by a logic high signal skew information signal DET_SQ. The signal NM1 is turned on and input to the first delay unit 310 to be input to the second delay unit 330 without passing through the first delay unit 310. That is, the delay time provided by the first delay unit 310 does not affect the pulse width. Therefore, only 4 ns provided from the second delay unit 330 affects the pulse width, thereby generating an oscillation signal OSC corresponding to the desired 4 ns.

If it is assumed that the delay time provided from the second delay unit 330 is 4 ns, the design is performed in order to set the desired pulse width to 4 ns.

Here, when the process state is FAST and a delay time of 2 ns is provided from the second delay unit 330 differently than expected, the NMOS transistor NM1 is turned off by the logic 'low' skew information signal DEST_SQ. It is turned off to further add a delay time provided by the first delay unit 310. That is, the delay time provided by the first delay unit 310 and the second delay unit 330 both affect the pulse width. Therefore, the delay time of 2 ns provided by the second delay unit 330 and the delay time provided by the first delay unit 310 affect the pulse width, so that the oscillation signal OSC corresponding to the desired 4 ns is affected. Can be generated.

4 is a circuit diagram illustrating the skew detector 370 of FIG. 3.

Referring to FIG. 4, the skew detector 370 generating the skew information signal DET_SQ through fuse programming includes a fuse 372 and a fuse 372 in which information corresponding to a process change is programmed. The skew information signal output unit 374 may be provided to output the skew information signal DET_SQ in response to the output signal OUT_FU.

The fuse FU of the fuse unit 372 may be programmed, such as fuse cutting, and determine whether the fuse FU is cut according to a process change. If the fuse FU is not blown, the output signal OUT_FU of the fuse 372 has a voltage level corresponding to the external voltage VDD. If the fuse FU is blown, the fuse 372 is blown. The output stage of is floated.

The skew information signal output unit 374 outputs the skew information signal DET_SQ corresponding to the output signal OUT_FU of the fuse unit 372 in response to the power-up signal POWER_UP. The power-up signal POWER_UP is a pulse signal that is activated when the voltage level of the external voltage VDD is initially secured to a desired voltage level.

When the output signal OUT_FU of the fuse unit 372 has a voltage level corresponding to the external voltage VDD, that is, when the fuse FU is not blown, the skew information signal output unit 374 has a logic 'low'. Outputs the skew information signal DET_SQ. When the fuse FU is blown, the skew information signal output unit 374 outputs a skew information signal DET_SQ of logic 'high'.

Referring back to Figures 3 and 4, the ring oscillator according to the present invention can detect the skew according to the process change, and adjust the delay time to match the constant pulse width of the oscillation signal (OSC) according to the result. Therefore, the ring oscillator can generate the oscillation signal OSC which always has a constant frequency even when the process state changes.

In the above embodiment, an example in which the delay time is changed according to one process state has been described. However, a plurality of skew detectors corresponding to the process state and corresponding delay and switching units may be provided to respond to both process changes. Oscillators may also be implemented.

For example, if it is designed to have three delays and expects the two delays to reflect the desired delay time when the process state is TYPICAL, a desired switching operation is performed by programming a fuse corresponding to FAST or SLOW and outputting a skew information signal accordingly. In this case, when the process state is FAST, the desired delay time may be reflected by using three delay units, and when the process state is SLOW, one delay unit may be used to reflect the desired delay time.

5 is a circuit diagram illustrating a ring oscillator of a substrate bias voltage generator according to the present invention.

For convenience of description, the voltage detector 110 and the voltage pumping unit 150 of FIG. 1 are not shown, and the operations of the voltage detector 110 and the voltage pumping unit 150 are substantially the same as in the prior art, and thus the present invention. It will be apparent to those who work in the technical field belonging to, specific description thereof will be omitted.

In addition, FIG. 5 illustrates that the ring oscillator according to the present invention of FIG. 3 is applied to a substrate bias voltage generator, and the activator 510 is different from that of FIG. 3.

Referring to FIG. 5, the ring oscillator provides an activator 510 for activating the ring oscillator in response to the detection signal DET_V (see FIG. 1), and a delay time corresponding to the pulse width of the oscillation signal OSC. First and second delay units 530 and 550, a skew detector 570 for generating a skew information signal DET_SQ by detecting skew according to a process change, and a skew information signal DET_SQ in response to the skew information signal DET_SQ. The switching unit 590 may be provided to include the first delay unit 530 in the inversion delay loop.

The activation unit 510 inverts and outputs the oscillation signal OSC fed back in response to the logic 'low' detection signal DET_V, and outputs a logic 'low' in response to the logic 'high' detection signal DET_V. Output Thus, when the detection signal DET_V is logic 'low', the ring oscillator starts oscillation. When the detection signal DET_V is logic 'high', oscillation is stopped.

The switching unit 590 may connect or disconnect the input terminal and the output terminal of the first delay unit 310 according to the skew information signal DET_SQ.

Meanwhile, the first and second delay units 530 and 550 are provided to provide a delay time corresponding to the pulse width of the oscillation signal OSC, and the second delay unit 550 is used to operate the switching unit 590. Accordingly, the output signal of the activator 510 is input or the output signal of the first delay unit 530 is received.

As a result, the apparatus for generating a substrate bias voltage according to the present invention may maintain a pulse width of the oscillation signal OSC by providing a desired delay time according to a process change.

As described above, the present invention can keep the pulse width of the oscillation signal OSC output from the ring oscillator constant by detecting the skew according to the process change and varying the delay time. Therefore, the pulse width of the oscillation signal OSC always has a constant frequency regardless of the process change. Subsequently, the voltage pumping unit may always receive an optimized oscillation signal OSC having a constant frequency to perform a stable pumping operation.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above-described embodiment, the internal voltage generator generates the substrate bias voltage VBB lower than the ground voltage VSS as an example, but the present invention provides a pumping voltage higher than the external voltage VDD. It is also applicable to the generation of (VPP), and also to the case of generating an oscillation signal having a constant pulse width.

The present invention described above can generate an output signal having a constant frequency at all times even in process changes, and the internal voltage generator using the oscillation signal can obtain the effect of generating the internal voltage in an optimal state.

Claims (16)

In a ring oscillator consisting of an inverse delay loop, A plurality of delay means for providing a delay time corresponding to the pulse width of the oscillation signal; Skew detection means for generating a skew information signal by detecting a skew according to a process change; And Switching means for selectively including a part of said plurality of delay means in said inversion delay loop in response to said skew information signal; Ring oscillator having a. The method of claim 1, The plurality of delay means, A first delay unit for providing a predetermined delay time to the pulse width of the oscillation signal; And a second delay unit for providing a delay time greater than the predetermined delay time to the pulse width of the oscillation signal. The method of claim 2, And the switching means connects an input terminal and an output terminal of any one of the first and second delay units in response to the skew information signal. The method of claim 1, And the skew detecting means outputs the skew information signal through fuse programming. The method of claim 1, The skew detection means, A fuse unit in which information corresponding to the process change is programmed; And a skew information signal output unit for outputting the skew information signal in response to an output signal of the fuse unit. The method of claim 5, And the skew information signal output unit outputs the skew information signal in response to a power up signal. Voltage detecting means for detecting an internal voltage corresponding to the reference voltage; A ring oscillator having an inverted delay loop and configured to generate an oscillation signal in response to a detection signal which is an output signal of the voltage detection means; And A voltage pumping means for generating the internal voltage corresponding to the oscillation signal, The ring oscillator, An activation unit for activating the ring oscillator in response to the detection signal; A plurality of delay units for providing a delay time corresponding to the pulse width of the oscillation signal; A skew detector for generating a skew information signal by detecting a skew according to a process change; And And a switching unit for selectively including a part of the plurality of delay means in the inversion delay loop in response to the skew information signal. The method of claim 7, wherein The plurality of delay units, A first delay unit for providing a predetermined delay time to the pulse width of the oscillation signal; And a second delay unit for providing a delay time greater than the predetermined delay time to the pulse width of the oscillation signal. The method of claim 8, And the switching unit connects an input terminal and an output terminal of any one of the first and second delay units in response to the skew information signal. The method of claim 7, wherein The switching unit, And a MOS transistor having a source-drain path formed between at least one input terminal and the output terminal of the plurality of delay units and gated to the skew information signal. The method of claim 7, wherein And the skew detection unit outputs the skew information signal through fuse programming. The method of claim 7, wherein The skew detection unit, A fuse unit in which information corresponding to the process change is programmed; And a skew information signal output unit configured to output the skew information signal in response to an output signal of the fuse unit. The method of claim 12, And the skew information signal output unit outputs the skew information signal in response to a power up signal. The method of claim 7, wherein And the activator is inverted in response to the detection signal. The method of claim 7, wherein The internal voltage generation device, characterized in that the reduced voltage of the ground voltage. The method of claim 7, wherein The internal voltage is a boosted voltage of an external voltage.

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