KR20060022161A - Circuit for providing bootstrapping voltage stably - Google Patents

Abstract

A boosted voltage providing circuit for stably supplying a boosted voltage having a voltage value higher than the power supply voltage to a semiconductor device is provided. The boosted voltage providing circuit is a pump unit for generating a predetermined boosted voltage, a first detector for comparing a first detected voltage, which is a divided voltage of the reference voltage and the boosted voltage, and providing a first detected voltage comparison signal, and a divided voltage of the boosted voltage. A detector unit comprising a second detector for comparing the reference voltage and the second detection voltage lower than the first detection voltage to provide a second detection voltage comparison signal, and receiving the first detection voltage comparison signal and the second detection voltage comparison signal. And a periodic signal unit providing a first periodic signal and a second periodic signal, and an oscillator unit receiving the first periodic signal and the second periodic signal and providing a pump driving signal having a corresponding period to the pump unit.

Semiconductor devices, step-up voltages, oscillators

Description

Boost voltage supply circuit for stably supplying boost voltage {Circuit for providing bootstrapping voltage stably}

1 is a block diagram of a conventional boosted voltage providing circuit.

2 is a block diagram of a boosted voltage providing circuit according to an exemplary embodiment of the present invention.

3 is a circuit diagram illustrating a detector of a boosted voltage providing circuit according to an exemplary embodiment of the present invention.

4 is a circuit diagram illustrating a periodic signal unit of a boosted voltage providing circuit according to an exemplary embodiment of the present invention.

5 is a circuit diagram illustrating an oscillator unit of a boosted voltage providing circuit according to an exemplary embodiment of the present invention.

6 is a circuit diagram illustrating an oscillator unit of a boosted voltage providing circuit according to another exemplary embodiment of the present invention.

7 is a circuit diagram illustrating a pump unit of a boosted voltage providing circuit according to an exemplary embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

100: detector portion 200: cycle signal portion                 

300: oscillator portion 400: pump portion

The present invention relates to a boosted voltage providing circuit, and more particularly, to a boosted voltage providing circuit for stably supplying a boosted voltage having a voltage value higher than a power supply voltage to a semiconductor device (for example, a semiconductor memory device). .

In general, since a boosted voltage having a voltage value higher than the power supply voltage can compensate for a loss of a threshold voltage of the MOS transistor, the boosted voltage providing circuit supplying the boosted voltage is a semiconductor memory device, particularly a word line. Widely used in drivers and bit line isolation circuit data output buffers.

Referring to Fig. 1, a conventional boosted voltage providing circuit will be described. The detector unit 10 compares the boosted voltage VPP provided by the pump unit 30 with a reference voltage and outputs an activated detection voltage comparison signal VPPDET when the boosted voltage VPP is lower than the reference voltage. 20) to provide. The oscillator unit 20 is activated by the activated detection voltage comparison signal VPPDET to provide a pump driving signal VPPDRV having a predetermined period to the pump unit 30. The pump unit 30 performs a charge pumping operation by the pump driving signal VPPDRV to increase the boosted voltage VPP until the boosted voltage VPP becomes equal to the reference voltage.                         

However, since the period of the pump driving signal VPPDRV of the oscillator unit 20 of the conventional boosted voltage providing circuit is constant, when the level of the boosted voltage VPP is sharply lowered, the level of the rapidly increased boosted voltage VPP is lowered. It was difficult to ascend quickly. If the word line driver is activated while the level of the boosted voltage VPP is not sufficiently raised to perform a write or read operation, data may not be effectively written to the semiconductor memory device or may be written from the semiconductor memory device. The data cannot be read effectively.

Therefore, the technical problem to be achieved by the present invention is to provide a boosted voltage providing circuit which can stably supply the boosted voltage by providing a pump driving signal having a different period according to the level of the voltage drop of the boosted voltage to perform a pumping operation. .

Technical problems to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to another aspect of the present invention, a booster voltage providing circuit includes a pump unit generating a predetermined boosted voltage, a first detection voltage by comparing a reference voltage with a first detection voltage that is a divided voltage of the boosted voltage. A first detector for providing a voltage comparison signal and a second detector for comparing the reference voltage with a second detection voltage lower than the first detection voltage and providing a second detection voltage comparison signal by dividing the boosted voltage; A detector unit receives the first detection voltage comparison signal and the second detection voltage comparison signal to provide a first periodic signal and a second periodic signal, and transmits the first periodic signal and the second periodic signal. And an oscillator unit for providing a pump driving signal having a corresponding period to the pump unit.

According to another aspect of the present invention, a booster voltage providing circuit includes a pump unit generating a predetermined boosted voltage, a first detection voltage by comparing a reference voltage with a first detection voltage that is a divided voltage of the boosted voltage. A first detector providing a voltage comparison signal, a second detector providing a second detection voltage comparison signal by comparing a second detection voltage that is a divided voltage of the reference voltage and the boosted voltage and lower than the first detection voltage, and the reference A detector comprising a third detector for comparing a third detection voltage that is a divided voltage of the voltage and the boosted voltage and lower than the second detection voltage to provide a third detection voltage comparison signal, the first detection voltage comparison signal, and the The second period voltage signal and the third period voltage signal are received to receive the first period signal, the second period signal, and the third period signal. And an oscillator unit configured to receive the first periodic signal, the second periodic signal, and the third periodic signal, and provide a pump driving signal having a corresponding period to the pump unit.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

The boosted voltage providing circuit according to an exemplary embodiment of the present invention includes a detector unit for comparing the divided voltages of the plurality of boosted voltages with reference voltages to provide respective detected voltage comparison signals in order to effectively detect the degree of falling of the boosted voltage level. The plurality of detection voltage comparison signals are combined to generate a plurality of periodic signals. In addition, a plurality of periodic signals are provided to the oscillator to generate pump driving signals having different periods according to the level of the voltage drop. As a result, the boosted voltage can be stably supplied to the semiconductor memory device even when the level of the boosted voltage is drastically lowered.

A boosted voltage providing circuit according to an exemplary embodiment of the present invention will be described with reference to FIG. 2. 2 is a block diagram of a boosted voltage providing circuit according to an exemplary embodiment of the present invention.

The booster providing circuit according to an exemplary embodiment of the present invention includes a detector unit 100, a periodic signal unit 200, an oscillator unit 300, and a pump unit 400. Here, the detector unit 100 compares the reference voltage with the first detection voltage which is the divided voltage of the boosted voltage VPP provided by the pump unit 400 to provide the first detection voltage comparison signal DET1. A first detector 110, a second detector 120 that compares a second detection voltage that is a divided voltage between the reference voltage and the boosted voltage VPP and is lower than the first detection voltage to provide a second detection voltage comparison signal DET2, And a third detector 130 that compares a third detection voltage that is a divided voltage of the reference voltage and the boosted voltage VPP and is lower than the second detection voltage to provide a third detection voltage comparison signal DET3.

The periodic signal unit 200 receives the first detection voltage comparison signal DET1, the second detection voltage comparison signal DET2, and the third detection voltage comparison signal DET3 from the detector unit 100 and receives the first detection voltage. The first periodic signal VPPDET1, the second periodic signal VPPDET2, and the third periodic signal VPPDET3 by combining the comparison signal DET1, the second detection voltage comparison signal DET2, and the third detection voltage comparison signal DET3. ).

The pump driving signal VPPDRV receives the first cycle signal VPPDET1, the second cycle signal VPPDET2, and the third cycle signal VPPDET3 from the cycle signal unit 200, and has a corresponding cycle. (VPPDRV) to the pump unit (400).

The pump unit 400 receives the pump driving signal VPPDRV according to the first periodic signal VPPDET1, the second periodic signal VPPDET2, and the third periodic signal VPPDET3, and performs a pumping operation to perform a boosting voltage VPP. ).

A detailed description of the operation of the detector unit 100 will be described with reference to FIG. 3. 3 is a circuit diagram illustrating a detector of a boosted voltage providing circuit according to an exemplary embodiment of the present invention. As described above, the detector unit includes a first detector 110, a second detector 120, and a third detector 130.

The first detector 110 includes a differential amplifier composed of two PMOS transistors Mp11 and Mp21 and two NMOS transistors Mn11 and Mn21 and a resistor RB1. The reference voltage Vref is applied to the gate of the NMOS transistor Mn21, and the first detector voltage A1 is applied to the gate of the NMOS transistor Mn21. When it is lower than Vref, the first detection voltage A1 comparison signal DET1 in a high state is provided, and when the first detection voltage A1 is higher than the reference voltage Vref, the first detection voltage in a low state is compared. The reference voltage Vref is a voltage VDD2 * Rd / (Ru + Rd) obtained by multiplying the resistance ratio Rd / (Ru + Rd) by the first power supply voltage VDD2. The first detection voltage A1 is a voltage VPP * R11 / (R21 + R21) obtained by multiplying the boost voltage VPP by the resistance ratio R21 / (R11 + R21), where the reference voltage Vref and Before the first detection Providing a separate power supply voltage for (A1) is to suppress the change in the reference voltage (Vref) even if the boosted voltage (VPP) changes, and the resistors (Ru, Rd, R11, R21, RB1) An active resistor using a polysilicon resistor or a MOS transistor can be used.

The second detector 120 includes two PMOS transistors Mp12 and Mp22, two NMOS transistors Mn12 and Mn22 and a resistor RB2. The reference voltage Vref is applied to the gate of the NMOS transistor Mn12, and the second detection voltage A2 is applied to the gate of the NMOS transistor Mn22. Thus, the second detector 120 provides the second detection voltage comparison signal DET2 in a high state when the second detection voltage A2 is lower than the reference voltage Vref, and the second detection voltage A2 is When the reference voltage Vref is higher than the reference voltage Vref, the second detection voltage A2 of the low state is provided. On the other hand, the second detection voltage A2 is the voltage VPP * R12 / (R22 + R22) obtained by multiplying the boost voltage VPP by the resistance ratio R22 / (R12 + R22), and the first detection voltage A1. Lower than Accordingly, the second detector 120 may detect that the level of the boosted voltage VPP decreases more than the first detector 110. Here, providing a separate power supply voltage for the reference voltage Vref and the second detection voltage A2 is for suppressing the change of the reference voltage Vref even if the boosted voltage VPP is changed as described above. In some cases, the reference voltage Vref applied to the first detector 110 and the reference voltage Vref applied to the second detector 120 may be provided using separate power supply voltages. As described above, the resistors R12, R22, and RB2 may use an active resistor using a polysilicon resistor or a MOS transistor.

The third detector 130 includes a differential amplifier composed of two PMOS transistors Mp13 and Mp23, two NMOS transistors Mn13 and Mn23, and a resistor RB3. The reference voltage Vref is applied to the gate of the NMOS transistor Mn13, and the third detection voltage A3 is applied to the gate of the NMOS transistor Mn23. As a result, the third detector 130 provides the third detection voltage comparison signal DET3 in a high state when the third detection voltage A3 is lower than the reference voltage Vref. When higher than the reference voltage Vref, the third detection voltage comparison signal DET3 in a low state is provided. On the other hand, the third detection voltage A3 is the voltage (VPP * R23 / (R13 + R23)) multiplied by the boosted voltage VPP by the resistance ratio R23 / (R13 + R23), and the second detection voltage A2. Lower than Accordingly, the third detector 130 may detect that the level of the boosted voltage VPP decreases more than the second detector 120. Here, providing a separate power supply voltage for the reference voltage Vref and the third detection voltage A3 is for suppressing the change of the reference voltage Vref even if the boosted voltage VPP is changed as described above. In some cases, the reference voltage Vref applied to the second detector 120 and the reference voltage Vref applied to the third detector 130 may be provided using separate power supply voltages. As described above, the resistors R13, R23, and RB3 may use an active resistor using a polysilicon resistor or a MOS transistor.

A detailed operation description of the periodic signal unit 200 will be described with reference to FIG. 4. 4 is a circuit diagram illustrating a periodic signal unit of a boosted voltage VPP providing circuit according to an exemplary embodiment of the present invention.

The periodic signal unit 200 calculates the logical products 210 and 213 of the first detection voltage comparison signal DET1, the inverted second detection voltage comparison signal DET2, and the inverted third detection voltage comparison signal DET3. The first period signal VPPDET1 is provided, and the first detection voltage comparison signal DET1, the second detection voltage comparison signal DET2, and the inverted third detection voltage comparison signal DET3 are logical products 220 and 222. Computation is provided as the second periodic signal VPPDET2, and the first detection voltage comparison signal DET1, the second detection voltage comparison signal DET2, and the third detection voltage comparison signal DET3 are logical products 230 and 231. It calculates and provides as a 1st periodic signal VPPDET1.                     

Therefore, when the first detection voltage comparison signal DET1 is in a high state and the second detection voltage comparison signal DET2 and the second detection voltage comparison signal DET2 are in a low state, the first period signal VPPDET1 in a high state is performed. The second periodic signal VPPDET2 and the third periodic signal VPPDET3 in a low state are provided, and the first detection voltage comparison signal DET1 and the second detection voltage comparison signal DET2 are high and the third detection is performed. When the voltage comparison signal DET3 is in the low state, the second period signal VPPDET2 in the high state, the first period signal VPPDET1 and the third period signal VPPDET3 in the low state are provided, and the first through third times. When the detected voltage comparison signals DET1 to DET3 are in a high state, a third period signal VPPDET3 in a high state, a first period signal VPPDET1 and a third period signal VPPDET3 in a low state are provided. Low when the third to third detection voltage comparison signals DET1 to DET3 are low. The womb of the first to third period signals (VPPDET1 to VPPDET3) is provided.

A detailed operation description of the oscillator will be described with reference to FIG. 5. 5 is a circuit diagram illustrating an oscillator unit of a boosted voltage VPP providing circuit according to an exemplary embodiment of the present invention.

The oscillator 310 is activated by the oscillator enable signal OSC_EN in the high state. The oscillator enable signal OSC_EN is a logical sum operation signal of the first to third periodic signals VPPDET1 to VPPDET3. Therefore, when any one of the first to third periodic signals VPPDET1 to VPPDET3 is in a high state, the oscillator enable signal OSC_EN is in a high state, and thus the oscillator 310 is activated.                     

When the third period signal VPPDET3 having the high state is transmitted, the transmission gate T130 is activated to transmit an inversion signal of the NAND gate 313 operation signal to the third inversion delay unit D130, and a third inversion delay unit. Since D130 inverts the inverted signal of the NAND 313 operation signal, the ND gate 313 operation signal is delayed and transmitted to the input terminal of the NAND gate 313. Therefore, when the high state oscillator enable signal OSC_EN is applied, the high state oscillator enable signal OSC_EN is transmitted to another input terminal of the NAND gate 313, so that the NAND gate 313 has a pulse shape having a third period. Provide the pump drive signal (VPPDRV). Here, the third inversion delay unit D130 may be configured by connecting an odd number of inverters in series, and adjusts the number of inverters of the third inversion delay unit D130 to adjust the third cycle time of the pump driving signal VPPDRV. I can regulate it.

When the second period signal VPPDET2 in the high state is transferred, the transmission gate T120 is activated to transmit an inversion signal of the NAND gate 312 operation signal to the second inversion delay unit D120, and a second inversion delay unit. Since the inverting signal of the NAND 313 operation signal (D120) inverts the signal, the NAND gate 312 operation signal is delayed and transmitted to the input terminal of the NAND gate 312. Therefore, when the high state oscillator enable signal OSC_EN is applied, the high state oscillator enable signal OSC_EN is transmitted to another input terminal of the NAND gate 312, so that the NAND gate 312 inverts the pulse type signal in a third inverted manner. The pump driving signal VPPDRV having a second period is provided through the NAND gate 313 to the delay unit D130. Here, the second inversion delay unit D120 may be configured by connecting an odd number of inverters in series, and by adjusting the number of inverters of the second inversion delay unit D120 and the third inversion delay unit D130, a pump driving signal ( VPPDRV) may adjust the second cycle time. Since the pump driving signal VPPDRV having the second period is generated through the second inversion delay unit D120 and the third inversion delay unit D130, the cycle time of the pump driving signal VPPDRV having the third period is generated. Longer than

When the first period signal VPPDET1 having a high state is transmitted, the transmission gate T110 is activated to transmit an inversion signal of the NAND gate operation signal to the first inversion delay unit D110 and the first inversion delay unit. (D110) inverts the inverted signal of the NAND 311 operation signal, so that the NAND 311 gate operation signal is delayed and transmitted to the input terminal of the NAND gate 311. Therefore, when the oscillator enable signal OSC_EN in the high state is applied, the oscillator enable signal OSC_EN in the high state is transmitted to another input terminal of the NAND gate 311, so that the NAND gate 311 inverts the pulse type signal in a second inversion. The pump driving signal VPPDRV having a first period is provided through the NAND gates 312 and 313 by transferring to the delay unit D120. Here, the first inversion delay unit D110 may be configured by connecting an odd number of inverters in series, and by adjusting the number of inverters of the first to third inversion delay units D110 to D130, the first driving delay signal DPPDRV may be formed. 1 cycle time can be adjusted. Since the pump driving signal VPPDRV having the first period is generated through the first to third inverting delay units D110 to D130, the pump driving signal VPPDRV is longer than the cycle time of the pump driving signal VPPDRV having the second period.

Another embodiment of the oscillator section will be described with reference to FIG. 6. 6 is a circuit diagram illustrating an oscillator unit of a boosted voltage VPP providing circuit according to another exemplary embodiment of the present invention.

The oscillator unit 320 is configured to form a feedback circuit with first to fifth inverters including pull-up elements 441, 541, 641, 741, and 841 and pull-down elements 442, 542, 642, 742, and 842. A second ring constituting a feedback circuit with sixth to tenth inverters including a one-ring oscillator, pull-up elements 411, 511, 611, 711, 811 and pull-down elements 412, 512, 612, 712, 812 It includes an oscillator. The second inverters 541 and 542 and the sixth inverters 411 and 412 are connected by latches, the third inverters 641 and 642 and the seventh inverters 511 and 512 are connected by latches, and the fourth inverters. 741 and 742 and the eighth inverters 611 and 612 are connected by latches, and the fifth inverters 841 and 842 and the ninth inverters 711 and 712 are connected by latches. In addition, power supply voltage transmitters 420 and 520 transferring a power supply voltage VCC to each of the pull-up devices 411, 441, 511, 541, 611, 641, 711, 741, 811, and 841 of the first to tenth inverters. , 620, 720, and 820 and the pull-down elements 412, 442, 512, 542, 612, 642, 712, 742, 812, and 842 of the first to tenth inverters, respectively. Voltage transfer units 430, 530, 630, 730, and 830 are included. The oscillator 320 is activated by the oscillator enable signal OSC_EN in the high state. When the oscillator enable signal OSC_EN of the high state is transmitted, the low state signal is transmitted to the first inverters 441 and 442 to provide the pump driving signal VPPDRV having a predetermined period. Here, the oscillator enable signal OSC_EN is a logical sum operation signal of the first to third periodic signals VPPDET1 to VPPDET3 as described above. Accordingly, when any one of the first to third periodic signals VPPDET1 to VPPDET3 is in the high state, the oscillator enable signal OSC_EN is in the high state, and thus the oscillator 320 is activated.

The oscillator 320 is activated by the first periodic signal VPPDET1 to each of the pull-up elements 411, 441, 511, 541, 611, 641, 711, 741, 811, and 841 of the first to tenth inverters. Pull-up elements 411, 441, 511, 541, 611, 641, 711, of the first power supply voltage transfer units 421, 521, 621, 721, 821, and the first to tenth inverters that transfer the voltage VCC. Second power supply voltage transfer units 422, 522, 622, 722, 822 and first to tenth inverters that are activated to the second periodic signal VPPDET2 to transfer the power supply voltage VCC to each of 741, 811, and 841. A third power supply voltage that is activated to a third periodic signal VPPDET3 to each of the pull-up elements 411, 441, 511, 541, 611, 641, 711, 741, 811, and 841 to transfer a power supply voltage VCC. Parts 423, 523, 623, 723, 823. The current driving capability of the second power supply voltage transfer units 422, 522, 622, 722, and 822 is greater than the current driving capability of the first power supply voltage transfer units 421, 521, 621, 721, and 821, and The current driving capability of the power supply voltage transfer units 423, 523, 623, 723, 823 is greater than the current driving capability of the second power supply voltage transfer units 422, 522, 622, 722, and 822. Here, the first to third power supply voltage transfer units may be formed of PMOS transistors 421, 521, 621, 721, 821, 422, 522, 622, 722, 822, 423, 523, 623, 723, and 823. Can be. The width and length ratios of the PMOS transistors 422, 522, 622, 722, and 822 of the second power supply voltage transmitters are determined by the PMOS transistors 421, 521, 621, 721, and 821 of the first power supply voltage transmitters. By making it larger than the width and length ratio of the power supply, the current driving capability of the second power supply voltage transmitters 422, 522, 622, 722, and 822 is increased by the first power supply voltage transmitters 421, 521, 621, 721, and 821. It can be made larger than the current driving capability. In addition, the width and length ratios of the PMOS transistors 423, 523, 623, 723, and 823 of the third power supply voltage transmitters may be used to determine the PMOS transistors 422, 522, 622, 722, and 822 of the second power supply voltage transmitters. Greater than the width-to-length ratio, the current driving capability of the third power supply voltage transfer units 423, 523, 623, 723, 823 is increased by the second power supply voltage transfer units 422, 522, 622, 722, 822. It can be made larger than the current driving capability of. Therefore, when the second period signal VPPDET2 in the high state is transmitted, the pull-up elements 411, 441, 511, 541, and 611 of the first to tenth inverters are compared with the case in which the first period signal VPPDET1 in the high state is transmitted. 641, 711, 741, 811, and 841 are provided with the power supply voltage VCC in a shorter time, and thus the pump driving signal VPPDRV having the first period generated by transmitting the first period signal VPPDET1 in a high state. ) Is longer than the period time of the pump drive signal VPPDRV having the second period generated by the transmission of the second period signal VPPDET2 in the high state. When the third period signal VPPDET3 in the high state is transferred, the pull-up elements 411, 441, 511, 541, and 611 of the first to tenth inverters are compared with the case in which the second period signal VPPDET2 in the high state is transmitted. , 641, 711, 741, 811, and 841 are provided with a power supply voltage VCC in a shorter time, so that the second period signal VPPDET2 in a high state is transmitted to generate a pump driving signal VPPDRV. ) Is longer than the period time of the pump drive signal VPPDRV having the third period generated by the transmission of the third period signal VPPDET3 in the high state.

The oscillator 320 is activated by the first periodic signal VPPDET1 to each of the pull-down elements 412, 442, 512, 542, 612, 642, 712, 742, 812, and 842 of the first to tenth inverters and is grounded. First ground voltage transfer parts 431, 531, 631, 731, 831, which transfer voltage VSS, pull-down elements 412, 442, 512, 542, 612, 642, 712, of the first to tenth inverters. Second ground voltage transmitters 432, 532, 632, 732, and 832, which are activated on the second periodic signal VPPDET2 to transfer the ground voltage VSS to each of 742, 812, and 842, and the first to tenth inverters. A third ground voltage that is activated on the third periodic signal VPPDET3 to transfer the ground voltage VSS to each of the pull-down elements 412, 442, 512, 542, 612, 642, 712, 742, 812, 842. Parts 433, 533, 633, 733, 833. The current driving capability of the second ground voltage transfer units 432, 532, 632, 732, and 832 is greater than that of the first ground voltage transfer units 431, 531, 631, 731, and 831, and The current driving capability of the ground voltage transfer parts 433, 533, 633, 733, 833 is greater than the current driving capability of the second ground voltage transfer parts 432, 532, 632, 732, and 832. Here, the first to third ground voltage transfer units may include NMOS transistors 431, 531, 631, 731, 831, 432, 532, 632, 732, 832, 433, 533, 633, 733, and 833. Can be. The width and length ratios of the NMOS transistors 432, 532, 632, 732, and 832 of the second ground voltage transmitters are determined by the NMOS transistors 431, 531, 631, 731, and 831 of the first ground voltage transmitters. By making it larger than the width and length ratio, the current driving capability of the second ground voltage transmitters 432, 532, 632, 732, and 832 may increase the current driving capability of the first ground voltage transmitters 431, 531, 631, 731, and 831. It can be made larger than the current driving capability. In addition, the width and length ratios of the NMOS transistors 433, 533, 633, 733, and 833 of the third ground voltage transmitters may be defined by the NMOS transistors 432, 532, 632, 732, and 832 of the second ground voltage transmitters. Greater than the width-to-length ratio, the current driving capability of the third ground voltage transmitters 433, 533, 633, 733, 833 is reduced to the second ground voltage transmitters 432, 532, 632, 732, and 832. It can be made larger than the current driving capability of. Therefore, when the second period signal VPPDET2 in the high state is transmitted, the pull-down elements 412, 442, 512, 542, and 612 of the first to tenth inverters are compared with the case in which the first period signal VPPDET1 in the high state is transmitted. The pump driving signal VPPDRV having the first period generated by transmitting the first period signal VPPDET1 in a high state because the ground voltage VSS is provided to the terminals 642, 712, 742, 812, and 842 in a shorter time. ) Is longer than the period time of the pump drive signal VPPDRV having the second period generated by the transmission of the second period signal VPPDET2 in the high state. When the third period signal VPPDET3 in the high state is transferred, the pull-down elements 412, 442, 512, 542, and 612 of the first to tenth inverters are compared with the case in which the second period signal VPPDET2 in the high state is transmitted. Since the ground voltage VSS is provided to the 642, 712, 742, 812, and 842 in a shorter time, the pump driving signal VPPDRV having the second period generated by the transmission of the second period signal VPPDET2 in the high state is generated. ) Is longer than the period time of the pump drive signal VPPDRV having the third period generated by the transmission of the third period signal VPPDET3 in the high state.

A detailed description of the operation of the pump unit 400 will be described with reference to FIG. 7. 7 is a circuit diagram illustrating a pump unit of a boosted voltage providing circuit according to an exemplary embodiment of the present invention. The pump unit 400 includes a capacitor 951 and two MOS transistors 952 and 953. When the pump driving signal VPPDRV is applied to the capacitor 951 from the oscillator unit 300, the capacitor 951 performs charge pumping to increase the boosted voltage VPP while the pump driving signal VPPDRV is maintained at a high state. The boost voltage VPP is maintained while the pump driving signal VPPDRV is kept low. Therefore, when the period of the pump driving signal VPPDRV is short, charge pumping of the capacitor 951 is frequently performed, so that the level of the boost voltage VPP is quickly increased even if the level of the boost voltage VPP is sharply lowered. You can. Therefore, the charge pumping operation of the pump unit 400 can be performed by adjusting the period of the pump driving signal VPPDRV at the level of the voltage drop of the boosted voltage VPP, so that the boosted voltage VPP can be stably supplied.

In the boosted voltage providing circuit according to an exemplary embodiment of the present invention, a case in which three detectors have three detectors is exemplarily described. However, in some cases, the detector unit may include two detectors, and four or more detectors may be used. It may also include.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

According to an exemplary embodiment of the present invention, the boosted voltage providing circuit may provide a pump driving signal having a different period according to the degree of falling of the boosted voltage level to perform a pumping operation. A boosted voltage can be stably supplied to the memory device.

Claims (10)

A pump unit generating a predetermined boosted voltage; A first detector configured to compare a reference voltage with a first detection voltage that is a divided voltage of the boosted voltage to provide a first detected voltage comparison signal, and a second voltage that is divided by the boosted voltage and lower than the reference voltage and the first detected voltage A detector unit including a second detector for comparing the detection voltages to provide a second detection voltage comparison signal; A periodic signal unit receiving the first detection voltage comparison signal and the second detection voltage comparison signal and providing a first period signal and a second period signal; And And an oscillator unit configured to receive the first period signal and the second period signal and provide a pump driving signal having a corresponding period to the pump unit. The method of claim 1, The oscillator unit is activated by the first periodic signal to provide a pump drive signal having a first period, and is activated by the second periodic signal to provide a pump drive signal having a second period shorter than the first period. Boost voltage providing circuit. The method of claim 1, The oscillator unit comprises a ring oscillator constituting a feedback circuit with an odd number (≥ 3) inverters, first power voltage transfer units activated by the first periodic signal to each of the pull-up elements of the inverters to transfer a power voltage; Step-up voltage providing circuits, each of which is activated by the second periodic signal to transfer the power supply voltage to each of the pull-up elements of the inverters, includes second power supply voltage transfer units having a greater current driving capability than the first power supply voltage transfer units. . The method of claim 1, The oscillator unit comprises a ring oscillator constituting a feedback circuit with an odd number of inverters (≥ 3), first ground voltage transfer units activated by the first periodic signal to each of the pull-down elements of the inverters to transfer a ground voltage; Step-up voltage providing circuits each of the pull-down elements of the inverters includes second ground voltage transfer parts activated by the second periodic signal to transfer the ground voltage and having a greater current driving capability than the first ground voltage transfer parts. . The method of claim 1, The oscillator unit comprises a ring oscillator constituting a feedback circuit with an odd number of inverters (≥ 3), first power voltage transfer units activated by the first periodic signal to each of the pull-up elements of the inverters to transfer a power voltage; Second power voltage transfer parts activated by the second periodic signal to each of the pull-up elements of the inverters to transfer the power supply voltage, and having a greater current driving capability than the first power supply voltage transfer parts, pull-down elements of the inverters; Each of the first ground voltage transmitters and the pull-down elements of the inverters, which are activated by the first periodic signal to transmit a ground voltage, respectively, are activated by the second periodic signal to transmit the ground voltage, and the first ground. A multiplier including second ground voltage transfers having greater current drive capability than voltage transfers. Voltage providing circuit. A pump unit generating a predetermined boosted voltage; A first detector configured to compare a first detection voltage, which is a division voltage of the reference voltage and the boosted voltage, to provide a first detection voltage comparison signal, and a second voltage that is a division voltage of the reference voltage and the boosted voltage and lower than the first detection voltage A second detector for comparing the detected voltages to provide a second detected voltage comparison signal and comparing a third detected voltage divided by the reference voltage and the boosted voltage and lower than the second detected voltage to obtain a third detected voltage comparison signal; A detector unit including a third detector to provide; A periodic signal unit receiving the first detection voltage comparison signal, the second detection voltage comparison signal, and the third detection voltage comparison signal to provide a first period signal, a second period signal, and a third period signal; And And an oscillator unit configured to receive the first periodic signal, the second periodic signal, and the third periodic signal, and provide a pump driving signal having a corresponding period to the pump unit. The method of claim 6, The oscillator unit is activated by the first periodic signal to provide a pump drive signal having a first period, and is activated by the second periodic signal to provide a pump drive signal having a second period shorter than the first period. And a boosted voltage providing circuit activated by the third periodic signal to provide a pump drive signal having a third period shorter than the second period. The method of claim 6, The oscillator unit comprises a ring oscillator constituting a feedback circuit with an odd number of inverters (≥ 3), first power voltage transfer units activated by the first periodic signal to each of the pull-up elements of the inverters to transfer a power voltage; Second power supply voltage transmitters and pull-up devices of the inverters, which are activated by the second periodic signal to each of the pull-up elements of the inverters, transfer the power supply voltage, and have a greater current driving capability than the first power supply voltage transmitters; And boosting voltage providing circuits each of which is activated by the third periodic signal to transfer the power supply voltage and has a current driving capability greater than that of the second power supply voltage transmitters. The method of claim 6, The oscillator unit comprises a ring oscillator constituting a feedback circuit with an odd number of inverters (≥ 3), first ground voltage transfer units activated by the first periodic signal to each of the pull-down elements of the inverters to transfer a ground voltage, Second ground voltage transmitters and pull-down elements of the inverters, which are activated by the second periodic signal to each of the pull-down elements of the inverters, transfer the ground voltage, and have a greater current driving capability than the first ground voltage transfer units. And a third ground voltage transfer unit, each of which is activated by the third periodic signal to transfer the ground voltage and has a greater current driving capability than the second ground voltage transfer units. The method of claim 6, The oscillator unit comprises a ring oscillator constituting a feedback circuit with an odd number of inverters (≥ 3), first power voltage transfer units activated by the first periodic signal to each of the pull-up elements of the inverters to transfer a power voltage; Second power voltage transfer parts activated by the second periodic signal to each of the pull-up elements of the inverters to transfer the power supply voltage and having a greater current driving capability than the first power supply voltage transfer parts, pull-up elements of the inverters Third power voltage transfer parts activated by the third period signal to transfer the power supply voltage and having a greater current driving capability than the second power supply voltage transfer parts, and the first period to each of the pull-up elements of the inverters; First power voltage transfer parts activated by a signal to transfer a power supply voltage, pull-ups of the inverters Each of the second power supply voltage transmitters and the pull-up elements of the inverters, which are activated by the second periodic signal to transfer the power supply voltage to each of the devices, and which have a current driving capability greater than the first power supply voltage transmitters. 3. A booster voltage providing circuit comprising third power supply voltage transmitters activated by a three period signal to transfer the power supply voltage and having a greater current driving capability than the second power supply voltage transmitters.

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