JP2006140548A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of performing a variety of signal output operations including data transfer at a high frequency while simplifying the circuitry. <P>SOLUTION: For an output circuit capable of setting a plurality of output impedances through combination of a plurality of output MOSFETs, an output signal is formed with a first output impedance lower than the characteristic impedance of a transmission line based on a first control signal in correspondence with the variation timing of an input signal. Upon elapsing a first time later than the variation timing of input signal, an output signal is formed with a second output impedance matched to the characteristic impedance of a second control signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device, and relates to a circuit technique suitable for use in a semiconductor integrated circuit device that enables data transfer at a high frequency on a system.

As examples in which the output impedance of an output circuit formed in a semiconductor integrated circuit device can be adjusted, there are JP-A-2002-152032 and JP-A-2002-325019.
JP 2002-152032 A JP 2002-325019 A

  In the above-mentioned Patent Document 1, an output circuit capable of impedance control that provides a small output impedance while keeping the output capacitance small is provided. That is, as shown in FIG. 1, a plurality of PMOS Qp0 to Qp7 having different impedance values and drains connected to the output terminal OUT and a plurality of logics for generating signals for controlling the corresponding PMOS Qp0 to Qp7. First control signal generating means comprising gates 10 to 17, a plurality of NMOSs Qn0 to Qn7 each having a different impedance value and having a drain connected to the output terminal OUT, and a plurality of signals for controlling the corresponding NMOSs Qn0 to Qn7 A second control signal generation means comprising logic gates 20 to 27, and a common output control signal is input to one input terminal of each of the logic gates 10 to 17 and 20 to 27, The selection signals UP0 to UP7 and DN0 to DN7 are input to the other input terminals, respectively, so that signals can be output. An output circuit configured to signal for the output control from the selected logic gates are output to the corresponding N-channel MOSFET and P-channel MOSFET. The output impedance of the output circuit can be increased or decreased by selecting an N-channel MOSFET and a P-channel MOSFET that operate in accordance with the selection signal. For example, the output impedance is changed from a specified value due to process variations or changes in temperature or power supply voltage. Even in such a case, the impedance can be controlled and adjusted so as to be within a specified value.

  In the above-mentioned Patent Document 2, as shown in FIG. 5, the output impedance is composed of a driver (140) and a pre-driver (120) and matches the characteristic impedance of the transmission line of the signal transmission medium (148). Is provided. The pre-driver (120) is electrically coupled to the driver in parallel and is configured to receive and amplify the signal in response to the control signal (115). That is, when a control signal is applied, the pre-driver is turned on during a portion of the clock cycle in response to the transition of the signal (105) applied to the driver's signal input. The predriver is controlled by a control signal configured to inject a high frequency component into the transmission line during a portion of the clock cycle. FIG. 6 of the publication shows a timing diagram of such a control signal. The control signal (300) causes the pre-driver to be “on” at about the same time as the transition of the data signal (200) from the driver, and the impedance of the pre-driver and its downstream components (ie, transmission lines and receivers). It is configured to be “off” before the reflected signal resulting from the matching appears at the output of the parallel driver.

  In order to transfer data between a memory LSI (large scale integrated circuit) and an MPU (microprocessor) at high speed (high frequency), it is necessary to perform impedance matching of the transmission system and suppress distortion of the transfer waveform due to reflection. . In the technique described in Patent Document 1, the output impedance is simply set so as to match the impedance of the transmission line. In the Gbps class data transmission system, the dielectric loss tangent (dielectric loss) / skin on the transmission line No consideration is given to the fact that the period (data window) in which valid data appears due to the occurrence of high-frequency attenuation due to the effect (resistance loss) or the like decreases. The technique described in Patent Document 2 requires two drivers having a relatively large area such as a driver and a pre-driver, so that consideration is given to the fact that the circuit area increases and the chip size increases accordingly. It has not been. Also, no consideration is given to the fact that the output impedance deviates from the specified value when there is a process variation or a change in temperature or power supply voltage, for example.

  In transmission systems with a data transfer rate of Gbps (Giga-bit / s) class, the period during which valid data appears due to the dielectric loss tangent (dielectric loss) and skin effect (resistance loss) on the transmission line (data The decrease in wind is getting serious. According to the simulation, it is clear that the current development product of about 1 Gbps barely satisfies the specification, but the next generation product that requires 1.5 Gbps or more cannot satisfy the specification by adjusting the output impedance as described above. became. Therefore, a study was made to realize a countermeasure against data window due to the dielectric loss tangent (dielectric loss) and skin effect (resistance loss) on the transmission line with a simple circuit.

  An object of the present invention is to provide a semiconductor integrated circuit device which enables various signal output operations including data transfer at a high frequency while simplifying the circuit. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. For an output circuit in which a plurality of output impedances can be set by a combination of a plurality of output MOSFETs, it is smaller than the characteristic impedance of the transmission line based on the first control signal corresponding to the signal change timing of the input signal. An output signal is formed by the first output impedance, and an output signal is formed by the second output impedance matched to the characteristic impedance based on the second control signal after a lapse of a first time delayed by the signal change timing of the input signal. To.

  Data transfer at high frequency is included by changing the output impedance during the signal output operation by effectively using the circuit function that enables the setting of multiple output impedances by combining multiple output MOSFETs Various signal output operations can be realized.

  FIG. 1 is a block diagram showing an embodiment of an output circuit mounted on a semiconductor integrated circuit device according to the present invention. In the figure, IN is a data input signal to the output circuit, OUT is a data output signal from the output circuit, and CTRL is an output enable signal. UP1 <0: n> (n is an integer of 0 or more) is a control signal for controlling the output impedance when the data output signal OUT is at a high level. DN1 <0: n> is a control signal for controlling the output impedance when the data output signal OUT is at a low level. These control signals UP1 <0: n> and DN1 <0: n> are control signals that have an output impedance that matches the characteristic impedance of the transmission line through which the output signal is transmitted.

  In this embodiment, in addition to the control signals UP1 <0: n> and DN1 <0: n>, control signals UP2 <0: n> and DN2 <0: n> are added. UP2 <0: n> is a control signal for controlling the output impedance when the data output signal OUT changes from the low level to the high level. DN2 <0: n> is a control signal for controlling the output impedance when the data output signal OUT transits from a high level to a low level.

  The data input signal IN and the output enable signal CTRL are used as a pull-down input signal IIZN through a NAND gate circuit G2. As the data input signal IN, a signal obtained by inverting the output enable signal CTRL by the inverter circuit INV1 is used as a pull-up input signal IIZP through a NOR gate circuit G1. DLP and DLN are delay circuits, which form the delay signals IPDEL and INDEL of the input signals IIZP and IIPN, respectively. SEL1 is a selection circuit that selects one of the control signals UP1 <0: n> or UP2 <0: n>, and SEL2 is one of the control signals DN1 <0: n> or DN2 <0: n>. Is a selection circuit for selecting. MOSFET 1 has a pull-up circuit whose impedance is variable by control signal UP1 <0: n> or UP2 <0: n>, and MOSFET2 has a variable impedance by control signal DN1 <0: n> or DN2 <0: n>. Pull-down circuit.

  In FIG. 1, for example, when the output signal OUT transitions from a low level to a high level, when the data signal IN passes through the gate circuit G1 and is input to the selection circuit SEL1 as the signal IIZP, the impedance of the MOSFET 1 is controlled by the control signal UP2 < 0: controlled by n>. After that, when the data signal IN passes through the delay circuit DLP and is input to the selection circuit SEL1 as the signal IPDEL, the impedance of the MOSFET 1 is switched to be controlled by the control signal UP1 <0: n>. Further, when the output signal OUT transits from the high level to the low level, the impedance of the MOSFET 2 corresponds to the signal IIZN, is controlled by the control signal DN2 <0: n> selected by the selection circuit SEL2, and is generated thereafter. Corresponding to the delayed signal INDEL to be controlled by the control signal DN1 <0: n> selected by the selection circuit SEL2.

  The control signals UP1 <0: n> and DN1 <0: n> are generated so that the output impedance becomes a predetermined value matching the characteristic impedance of the transmission line, and the control signals UP2 <0: n> and DN2 < If 0: n> is generated so that the output impedance is smaller than the predetermined value, the output impedance becomes lower than the predetermined impedance when the output signal waveform transitions in response to the signal IIZP or IIZN. High frequency components can be injected, and the data window can be prevented from decreasing. In other words, in anticipation of dielectric loss tangent (dielectric loss) and skin effect (resistance loss) on the transmission line, pre-emphasis of injecting high-frequency components is performed to compensate for the reduction of high-frequency components on the receiving side. be able to.

  Since the output circuit can be composed of one pull-up circuit (MOSFET 1) and one pull-down circuit (MOSFET 2), the circuit area can be reduced as compared with Patent Document 2 in which the output impedance at the time of output is changed. The size can be reduced. That is, the output circuit provided in the semiconductor integrated circuit device is constituted by a plurality corresponding to the output data width, that is, the number of output bits. For example, in an output circuit corresponding to a 16-bit bus width, 16 output circuits are provided, and in an output circuit corresponding to a 32-bit bus width, 32 are provided, and in order to drive a relatively large load A MOSFET having a relatively large element size is used. For this reason, compared with Patent Document 2 in which two circuits are combined to set two impedances, the output circuit of the present application can be about half the circuit scale.

  Further, in this embodiment, since the output impedance can be controlled by the impedance control signals UP1 <0: n> and DN1 <0: n>, the output impedance is defined by, for example, process variations or changes in temperature or power supply voltage. Even if the values are likely to deviate from the values, the impedance can be controlled by the control signals UP1 <0: n> and DN1 <0: n> so as to be within a specified value.

  In this embodiment, UP1 <0: n> and UP2 <0: n> (DN1 <0: n> and DN2 <0: n>) are formed as two output impedance control signals as described above. Since the output impedance is switched with a simple configuration in which it is selected by IIZP or IPDEL (IIZN or INDEL) corresponding to the input signal IN, UP1 <0: n> (DN1 <0: n>) and the like can be easily realized by changing in accordance with process variations or changes in temperature or power supply voltage.

  In general, the control signals UP1 <0: n> and DN1 <0: n> are desirably substantially equal to the characteristic impedance of the transmission line driven by the output circuit as in the above-described embodiment. However, the value may be different from the characteristic impedance of the transmission line depending on the situation where the semiconductor integrated circuit device is mounted.

  FIG. 2 is a timing waveform diagram conceptually illustrating an example of the operation of the output circuit of FIG. In the figure, in order to make the relationship between the input signal IN and the output signal OUT easy to understand, the input signal is shown as an inverted signal / IN. When the output enable signal CTRL is at a high level (logic 1) and the input signal / IN is at a high level (the input signal IN is at a low level), the signal IIZP changes from the low level to the high level accordingly. Corresponding to this change timing, the output impedance is made smaller than the characteristic impedance corresponding to the control signal UP2 <i> (i is an integer from 0 to n) selected by the selection circuit SEL1. As a result, the output signal OUT is outputted as a signal level that is larger by VPE. When the delay signal IPDEL is delayed from the low level to the high level by the delay circuit DLP, the selection circuit SEL1 switches to the selection of the control signal UP1 <i> and changes the output impedance to the impedance corresponding to the characteristic impedance. . As a result, the output signal OUT is returned to the level corresponding to the output level VO corresponding to the normal impedance matching state.

  When the input signal / IN becomes low level (the input signal IN is high level), the signal IIZN changes from high level to low level correspondingly. Corresponding to this change timing, the output impedance is made smaller than the characteristic impedance corresponding to the control signal DN2 <i> selected by the selection circuit SEL2. As a result, the output signal OUT is outputted as a signal level smaller by VPE. When the delay signal INDEL is delayed from the high level to the low level by the delay circuit DLN, the selection circuit SEL2 switches to the selection of the control signal DN1 <i> and changes the output impedance to the impedance corresponding to the characteristic impedance. . As a result, the output signal OUT is returned to the level corresponding to the output level VO corresponding to the normal impedance matching state.

  In this embodiment, the signal UP2 <i> is selected when the delay signal IPDEL is low level, and the signal UP1 <i> is selected when the delay signal IPDEL is high level. Conversely, the signal DN2 <i> is selected when the delay signal INDEL is at a high level, and the signal DN1 <i> is selected when the delay signal INDEL is at a low level. The selected signals UP0 <i> and DN0 <i> are set to the high level / low level corresponding to the levels of the signals IIZP and IIZN corresponding to the input signal IN. Therefore, when the output signal OUT changes from the low level to the high level, the MOSFET II that has been turned on in response to the signal DN1 <i> is turned off by the signal IIZN that changes from the low level to the high level, and the output signal OUT Is changed from the high level to the low level, the signal IIZP changing from the high level to the low level causes all the MOSFETs 1 that have been turned on in response to the signal UP1 <i> to be turned off.

  FIG. 3 shows a configuration diagram of a specific example of the selection circuits SEL1, SEL2, the pull-up circuit MOSFET1, and the pull-down circuit MOSFET2 in FIG. The signal IIZP, the delayed signal IPDEL, the signal IIZN, and the delayed signal INDEL in the same figure correspond to those in FIGS. The pull-up circuit MOSFET1 is composed of a plurality of N + 2 parallel P-channel MOSFETs. The pull-down circuit MOSFET2 is composed of a plurality of N + 2 parallel N-channel MOSFETs.

  Among the N + 2 pull-up circuit MOSFET1, the signal IIZP is supplied to the gate of one P-channel MOSFET through the inverter circuit INV2, and the control signal UP1 <is supplied to the remaining N + 1 P-channel MOSFET gates through the selection circuit SEL1. Any one of 0> to UP1 <N> or UP2 <0> to UP2 <N> is selected according to the high level / low level of the signal IPDEL, and is output corresponding to the signal IIZP. Of the N + 2 pull-down circuit MOSFET2, the signal IIZN is supplied to the gate of one N-channel MOSFET through the inverter circuit INV3, and the control signal DN1 <0 is supplied to the remaining N + 1 N-channel MOSFET gates through the selection circuit SEL2. > To DN1 <N> or DN2 <0> to DN2 <N> are selected according to the high level / low level of the signal INDEL and output in response to the signal IIZN. The one MOSFET sets the maximum output impedance of the pull-up circuit and pull-down circuit.

  An operation as a variable resistance circuit is performed by a combination of on-resistances of the plurality of parallel MOSFETs which are turned on. For example, by selecting a combination of MOSFETs to be turned on in parallel connection in which the resistance ratio of the four resistors R1 to R4 is proportional to 8: 4: 2: 1, R1, R1 / 2, Fifteen types of impedance adjustment from R1 / 3 to R1 / 15 are possible. By making the impedance proportional to every two times, in other words, by using a resistance ratio with a binary weight, the selection of R1 to R4 can be controlled by a 4-bit binary code.

  FIG. 4 shows a circuit diagram of an embodiment of the selection circuit used in the present invention. FIG. 2A shows a circuit diagram of the selection circuit SEL1 corresponding to the pull-up circuit MOSFET1, and FIG. 2B shows a circuit diagram of the selection circuit SEL2 corresponding to the pull-down circuit MOSFET2. In the selection circuit SEL1 in FIG. 4A, an arbitrary 1-bit control signal UP1 {i} of the control signals UP1 <0: N> consisting of a plurality of bits is generated by a CMOS comprising a P-channel MOSFET Q1 and an N-channel MOSFET Q3. The signal is transmitted to one input of the NAND gate circuit G3 through the switch. An arbitrary 1-bit control signal UP2 {i} of the control signals UP2 <0: N> composed of a plurality of bits is also input to the one input of the NAND gate circuit G3 through a CMOS switch composed of a P-channel MOSFET Q2 and an N-channel MOSFET Q4. Reportedly. A signal IIZP is supplied to the other input of the gate circuit G3. Then, a signal UP0 {i} transmitted from the gate circuit G3 to the gate of one MOSFET of the pull-up circuit is output.

  In the selection circuit SEL2 in FIG. 4B, an arbitrary 1-bit control signal DN1 {i} among the control signals DN1 <0: N> consisting of a plurality of bits is a CMOS including a P-channel MOSFET Q5 and an N-channel MOSFET Q6. The signal is transmitted to one input of the NOR gate circuit G4 through the switch. An arbitrary 1-bit control signal DN2 {i} of the control signals DN2 <0: N> composed of a plurality of bits is also input to the one input of the NAND gate circuit G4 through a CMOS switch composed of a P-channel MOSFET Q6 and an N-channel MOSFET Q8. Reportedly. A signal IIZN is supplied to the other input of the gate circuit G4. The signal DN0 {i} transmitted from the gate circuit G4 to the gate of one MOSFET of the pull-down circuit is output.

  In FIG. 4A, MOSFETs Q1 and Q3 and Q2 and Q4 of the two CMOS switches constituting the selection circuit SEL1 are turned on / off complementarily by the high level / low level of the delay signal IPDEL. The delay signal IPDEL is supplied to the gates of the N-channel MOSFET Q3 and the P-channel MOSFET Q2, and is supplied to the gates of the P-channel MOSFET Q1 and the N-channel MOSFET Q4 through the inverter circuit INV4. For example, when the delay signal IPDEL is at a low level, the P-channel MOSFET Q2 and the N-channel MOSFET Q4 are turned on, and the signal UP2 {i} is selected and transmitted to one input of the gate circuit G3. When the delay signal IPDEL is set to the high level, the P channel MOSFET Q2 and the N channel MOSFET Q4 are turned off, the P channel MOSFET Q1 and the N channel MOSFET Q3 are turned on, and the signal UP1 {i} is selected and gated. It is transmitted to one input of the circuit G3.

  When the signal IIZP supplied to the other input of the gate circuit G3 changes to a high level, the output signal of the gate circuit G3 corresponding to the signal UP2 {i} set to the high level becomes a low level, and the pull-up circuit MOSFET1. Is turned on. That is, a plurality of P-channel MOSFETs corresponding to the signal UP2 <0: N> that is set to the high level are turned on, and the output signal OUT is changed from the low level to the high level by the output impedance as described above. Launch. When the delay signal IPDEL is set to the high level, the selection circuit SEL1 selects the signal UP1 {i}, so that a plurality of Ps corresponding to the signals UP1 <0: N> that are set to the high level. The channel MOSFET is turned on, and the high level of the output signal OUT is maintained by the output impedance matched to the transmission line as described above.

  In FIG. 4B, the MOSFETs Q5 and Q6 and Q7 and Q8 of the two CMOS switches constituting the selection circuit SEL2 are complementarily turned on / off by the high level / low level of the delay signal INDEL. The delay signal INDEL is supplied to the gates of the P-channel MOSFET Q5 and the N-channel MOSFET Q8, and is supplied to the gates of the N-channel MOSFET Q7 and the P-channel MOSFET Q6 through the inverter circuit INV5. For example, when the delay signal INDEL is at a high level, the P-channel MOSFET Q6 and the N-channel MOSFET Q8 are turned on, and the signal DN2 {i} is selected and transmitted to one input of the gate circuit G4. When the delay signal INDEL is set to the low level, the P-channel MOSFET Q6 and the N-channel MOSFET Q8 are turned off, the P-channel MOSFET Q5 and the N-channel MOSFET Q7 are turned on, and the signal DN1 {i} is selected and the gate circuit G4 To one of the inputs.

  When the signal IIZN supplied to the other input of the gate circuit G4 changes to the low level, the output signal corresponding to the signal DN2 {i} which is set to the low level in the gate circuit G4 becomes the high level, and the pull-down circuit MOSFET2 is configured. The N channel MOSFET to be turned on is turned on. That is, a plurality of N-channel MOSFETs corresponding to the low level signal DN2 <0: N> are turned on, and the output signal OUT is changed from the high level to the low level by the output impedance as described above. Lower. When the delay signal INDEL is set to the low level, the selection circuit SEL2 selects the signal DN1 {i}, so that a plurality of N-channel MOSFETs corresponding to the signals DN1 <0: N> that are set to the low level. Is turned on to maintain the low level of the output signal OUT by the output impedance matched to the transmission line as described above.

  FIG. 5 shows a circuit diagram of another embodiment of the selection circuit used in the present invention. FIG. 2A shows a circuit diagram of the selection circuit SEL1 corresponding to the pull-up circuit MOSFET1, and FIG. 2B shows a circuit diagram of the selection circuit SEL2 corresponding to the pull-down circuit MOSFET2. In the embodiment of FIG. 5A, a NOR gate circuit G5 is added to the selection circuit SEL1 of FIG. Corresponding to the addition of the NOR gate circuit G5, since the delay signal IPDEL is inverted, the CMOS switches are controlled in the same manner as in FIG. 4A. Is done. That is, the signal passing through the inverter circuit INV4 is supplied to the gates of the MOSFETs Q3 and Q2. If the signal ISEL1 is fixed at a high level by adding the NOR gate circuit G5, the signal IPDEL is invalidated, the output signal of the gate circuit G5 is fixed at a low level, and the MOSFETs Q1 and Q3 are steadily turned on, and the output impedance is reduced. It is constant corresponding to the signal UP1 {i}. This is because, for example, when the input signal IN to be transmitted is a relatively low frequency signal, or the wiring length of the transmission line is short, high frequency attenuation becomes a problem due to the dielectric loss tangent (dielectric loss), skin effect (resistance loss), or the like. It is used to stop the pre-emphasis function of the high frequency component when mounted on a system that does not become necessary.

  In the embodiment of FIG. 5B, a NAND gate circuit G6 is added to the selection circuit SEL2 of FIG. Corresponding to the addition of the NAND gate circuit G6, the delay signal INDEL is inverted, so that the CMOS switch is controlled in the same manner as in FIG. Is done. That is, the signal that has passed through the inverter circuit INV5 is supplied to the gates of the MOSFETs Q5 and Q8. If the signal ISEL2 is fixed to the low level by adding the NOR gate circuit G6, the signal INDEL is invalidated, the output signal of the gate circuit G6 is fixed to the high level, and the MOSFETs Q5 and Q7 are steadily turned on, and the output impedance is reduced. It is constant corresponding to the signal DN1 {i}. This is because, for example, when the input signal IN to be transmitted is a relatively low frequency signal, or the transmission line has a short wiring length, the high frequency attenuation is caused by the dielectric loss tangent (dielectric loss), skin effect (resistance loss), etc. Is used to stop the high-frequency component pre-emphasis function when installed in a system where the problem does not become a problem.

  By using the selection circuit as in the embodiment of FIG. 5, the versatility of the semiconductor integrated circuit device including the output circuit can be increased. For example, if the purpose of mounting the semiconductor integrated circuit device is known before shipment, the level of the signals ISEL1 and 2 is set by cutting the bonding wire or the fuse at the time of manufacture by the manufacturer of the semiconductor integrated circuit device. do it. In order to set the function of the output circuit when the system is mounted, the function may be set by a signal from an external terminal. In this case, when an electrically writable storage element is used, the function of the output circuit can be selected by a one-time setting. As described above, in the embodiment of FIG. 5, the signals ISEL1 and ISEL2 are added, and it is possible to select whether or not to perform high frequency compensation by inputting these signals into the fuse signal or the control signal from the external terminal. .

  FIG. 6 shows a block diagram of an embodiment of the delay circuit DLP or DLN of FIG. In this embodiment, the delay time of the delay circuit is made variable. It is desirable that the delay time of the delay circuit be shorter than approximately twice the delay time of the transmission line driven by the output circuit. In this case, the reflected wave from the receiving device of the signal output from the output circuit is terminated with a predetermined impedance on the transmitting end side, so that there is no impedance mismatch and re-reflection there occurs. It is possible to prevent the quality of the transmitted signal from being deteriorated without being generated. On the other hand, the characteristics of the transmission line driven by the output circuit vary depending on the situation such as the length of the transmission line of the system in which the semiconductor integrated circuit device is mounted. Therefore, it is desirable that the delay time of the delay circuit can be varied and optimally controlled to suit the system.

  In the embodiment of FIG. 6A, the control signals φi, / φi (i is an integer from 1 to n) are used to select which one of the n switches is turned on, and n delay times are formed. One delay time can be selected by switching the number of inverter stages constituting the delay circuits DL1 to DLn. In the embodiment of FIG. 6B, by controlling the potential levels of the control signals Vp and Vn, the current flowing through the P-channel MOSFET QP and the N-channel MOSFET QN is linearly controlled, and the equivalent impedances of the inverters INV10 and INV11 are switched. The delay time can be controlled.

  In this embodiment, the load driving currents flowing in the inverter circuits INV10 and INV11 are controlled by the MOSFETs QP and QN, respectively, and the delay time is controlled there. The inverter circuit INV10 controls the delay time when the output signal changes from low level to high level by the current flowing through the P-channel MOSFET QP, and the inverter circuit INV11 determines the delay time when the output signal changes from high level to low level. It is controlled by the current flowing through the N-channel MOSFET QN. That is, in the delay circuit of FIG. 6B, the delay time when the signal IIZP (IIZN) changes from the high level to the low level is controlled by the voltages Vp and Vn. On the other hand, when the signal IIZP (IIZN) changes from the low level to the high level, it changes at a relatively high speed regardless of the voltages Vp and Vn.

  FIG. 7 shows a circuit diagram of another embodiment of the delay circuit DLP or DLN of FIG. In this embodiment, the delay time can be controlled by switching the load capacitances of the cascade-connected inverter circuits INV12 and INV13 constituting the delay circuit by the control signals DLCTRL0 to DLCTRL2. In other words, the capacitors C0, C1, and C2 are selectively added as load capacitors according to the ON state of the switches corresponding to the control signals DLCTRL0 to DLCTRL2, and the delay time is lengthened. In this embodiment, the same delay time corresponding to the control signals DLCTRL0 to DLCTRL2 is set when the signal IIZP (IIZN) changes from the low level to the high level and when the signal IIZP (IIZN) changes from the high level to the low level.

  FIG. 8 is a block diagram showing an embodiment of a control signal generation circuit used in the output circuit according to the present invention. The control signal UP2 {i} or DN2 {i} (i is an integer from 0 to n) is generated by an addition (subtraction) circuit. In FIG. 8A, UP2 {i} or DN2 {i} is generated by adding or subtracting a fixed constant value to the control signal UP1 {i} or DN1 {i}. When the control signal UP2 {i} or DN2 {i} is generated in this way, the reciprocal of the output impedance (conductance) can be made larger than the reciprocal of the predetermined impedance (conductance) by a certain value when the output signal waveform changes. That is, the impedance can be reduced.

  FIG. 8B shows an example in which a constant value to be added or subtracted can be controlled. That is, UP2 {i} or DN2 {i} is generated by adding or subtracting a predetermined value designated by the addition (subtraction) amount adjustment to the control signal UP1 {i} or DN1 {i}. In this way, the output impedance when the output signal waveform transitions can be controlled by specifying the amount of addition (subtraction) with a fuse signal or other control signal depending on the situation in which the semiconductor integrated circuit device is mounted. Is possible.

  FIG. 9 is a block diagram showing another embodiment of the control signal generation circuit used in the output circuit according to the present invention. The control signal UP2 {i} or DN2 {i} is generated by a multiplication (division) circuit. In FIG. 9A, UP2 {i} or DN2 {i} is generated by multiplying or dividing the control signal UP1 {i} or DN1 {i} by a fixed constant value. That is, in the embodiment of FIG. 8, the control signal UP2 {i} or DN2 {i} is generated so as to have a certain difference with respect to the control signal UP1 {i} or DN1 {i}. In the ninth embodiment, the control signal UP2 {i} or DN2 {i} is generated so as to have a constant ratio to the control signal UP1 {i} or DN1 {i}. When the control signal UP2 {i} or DN2 {i} is generated in this way, the output impedance when the output signal waveform transitions can be made smaller than the predetermined impedance at a constant ratio.

  FIG. 9B shows an example in which the ratio for multiplication or division can be controlled. That is, UP2 {i} or DN2 {i} is generated by multiplying or dividing the control signal UP1 {i} or DN1 {i} by a predetermined value specified by adjusting the multiplication (division) amount. In this way, the output impedance when the output signal waveform transitions can be controlled by specifying by the adjustment of the multiplication (division) amount by the fuse signal or other control signal depending on the situation where the semiconductor integrated circuit device is mounted. Is possible.

  FIG. 10 is a circuit diagram showing another embodiment of the selection circuit used in the present invention. In this embodiment, a modification of the selection circuit SEL1 corresponding to the pull-up circuit MOSFET1 is shown. In the selection circuit SEL1 of this embodiment, a slew rate control circuit is added to the embodiment circuit of FIG. In this embodiment, the number of gate circuits G10 to G12 enabled by the slew rate control signal is switched to control the rise time of the output signal of the selection circuit so that the output slew rate can be adjusted.

  FIG. 11 shows a circuit diagram of another embodiment of the selection circuit used in the present invention. In this embodiment, a modification of the selection circuit SEL2 corresponding to the pull-down circuit MOSFET2 is shown. In the selection circuit SEL2 of this embodiment, a slew rate control circuit is added to the embodiment circuit of FIG. 4B. In this embodiment, the number of gate circuits G14 to G16 enabled by the slew rate control signal is switched to control the fall time of the output signal of the selection circuit so that the output slew rate can be adjusted.

  In the output circuit, the transition time (rising / falling) at the time of output of the transmitted data also suppresses signal reflection in the package and generation of simultaneous output switching noise due to the package inductor (waveform disturbance due to ringing, etc.). In addition, it is desirable to extend the transmission frequency to the limit. For this reason, it is also important to adjust the output transition time (slew rate) so that the data window width at the time of data transfer becomes the largest. For example, in a high-speed synchronous SRAM product, slew rate adjustment is not performed by an output driver, but is adjusted by load adjustment on an LSI mounting board. 10 and 11, the slew rate can be adjusted by the output circuit, and load adjustment on the LSI mounting board can be omitted.

  FIG. 12 shows a circuit diagram of an embodiment of the selection circuit SEL1 including the slew rate control circuit of FIG. In the figure, IIZP is a data input terminal, UP0 {i} is an output terminal, and is connected to the gate of one MOSFET of the pull-up circuit MOSFET1. UP1 {i} and UP2 {i} are the impedance adjustment code input terminals, and SR <0>, SR <1>, SR <2> are slew rate adjustment code terminals.

  N-channel MOSFETs 40 to 42 are arranged in parallel, and the commonly connected drains are connected to the output terminal UP0 {i}. The ground potential VSS of the circuit is supplied to the commonly connected sources of the N-channel MOSFETs 40 to 42 by the N-channel MOSFET Q43 that receives data to be output supplied from the data input terminal IIZP. A P-channel MOSFET Q53 is provided between the output terminal UP0 {i} and the power supply voltage VDD, and is switch-controlled by data to be output supplied from the data input terminal IIZP.

  P-channel MOSFETs 50 to 52 are provided in series between the output terminal UP0 {i} and the power supply voltage VDD. The gates of the N-channel MOSFETs 40 to 42 and the P-channel MOSFETs 50 to 52 are shared, and output signals of AND gate circuits 60, 61, 62 are transmitted. An impedance adjustment code UP1 {i} or UP2 {i} through the CMOS switch is supplied to one input of the AND gate circuits 60-62. A slew rate adjustment code is supplied to the other inputs of the AND gate circuits 60 to 62 from the input terminals SR <0>, SR <1>, SR <2>.

  In the slew rate control circuit of this embodiment, selection or non-selection of one MOSFET of the pull-up circuit MOSFET1 is set by the impedance adjustment code input terminal UP1 {i} or UP2 {i}, and the slew rate adjustment code SR <0. >, SR <1>, or SR <2> is selected from among the N-channel MOSFETs 40 to 42, and the load driving force (ON resistance) is changed. That is, the fall time of the drive signal transmitted to the gate of one MOSFET of the pull-up circuit MOSFET 1 is adjusted.

  FIG. 13 shows a circuit diagram of an embodiment of the selection circuit SEL2 including the slew rate control circuit of FIG. In the figure, IIZN is a data input terminal, DN0 {i} is an output terminal, and is connected to the gate of one MOSFET of the pull-down circuit MOSFET2. DN1 {i} and DN2 {i} are the impedance adjustment code input terminals, and SR <0>, SR <1>, SR <2> are slew rate adjustment code terminals.

  The selection circuit of this embodiment has a configuration in which the connection relationship between the N-channel MOSFET and the P-channel MOSFET in FIG. 12 is switched. That is, a drive signal for turning on the N-channel type output MOSFET is formed by the P-channel MOSFETs 70 to 72 arranged in parallel, and the data input signal IIZN is used as a switch for supplying the power supply voltage VDD thereto. A receiving P-channel MOSFET 73 is used. A MOSFET that resets the output terminal DN0 {i} to a low level in response to the data input signal IIZN is an N-channel MOSFET 83. N-channel MOSFETs 80 to 82 are arranged in series and are provided between the output terminal and the ground potential VSS of the circuit. Gate circuits 90 to 92 that receive impedance adjustment code DN1 {i} or DN2 {i} and slew rate adjustment codes SR <0>, SR <1>, SR <2> are NAND gates instead of AND gates. The

  FIG. 14 shows a circuit diagram of another embodiment of the selection circuit SEL1 including the slew rate control circuit of FIG. 12, IIZP is a data input terminal, UP0 {i} is an output terminal, and is connected to the gate of one MOSFET of the pull-up circuit MOSFET1. UP1 {i} and UP2 {i} are the impedance adjustment code input terminals, and SR <0>, SR <1>, SR <2> are slew rate adjustment code terminals.

  In the slew rate control circuit of this embodiment, selection or non-selection is designated by the impedance adjustment code IIZP. A PMOS / NMOS combination which is turned on in the CMOS switch by the P-channel MOSFETs 100 to 102 and the N-channel MOSFETs 110 to 112 is selected by the slew rate adjustment codes SR <0>, SR <1> and SR <2>, and the P-channel MOSFET 103 is selected. A combination of capacitors connected to the drain node (output terminal UP0 {i}) via the resistor RS is selected from C10 to C12. In this way, the time constant of the output terminal UP0 {i} is changed. That is, when the capacitance value is increased, the output terminal UP0 {i} falls late, and the slew rate in the P-channel output MOSFET driven thereby is reduced.

  FIG. 15 shows a circuit diagram of another embodiment of the selection circuit SEL2 including the slew rate control circuit of FIG. In the same figure, IIZN is a data input terminal, DN0 {i} is an output terminal, and is connected to the gate of one MOSFET of the pull-down circuit MOSFET2, as in FIG. DN1 {i} and DN2 {i} are the impedance adjustment code input terminals, and SR <0>, SR <1>, SR <2> are slew rate adjustment code terminals.

  In the slew rate control circuit of this embodiment, selection or non-selection is designated by the impedance adjustment code IIZP. A PMOS / NMOS combination which is turned on in the CMOS switch by the P-channel MOSFETs 120 to 122 and the N-channel MOSFETs 130 to 132 is selected by the slew rate adjustment codes SR <0>, SR <1>, SR <2>, and the N-channel MOSFET 133 A combination of capacitors connected to the drain node (output terminal DN0 {i}) via the resistor RS is selected from C20 to C22. In this way, the time constant of the output terminal DN0 {i} is changed. That is, when the capacitance value is increased, the rise of the output terminal DN0 {i} is delayed, and the slew rate in the N-channel output MOSFET driven thereby is reduced.

  FIG. 16 is a block diagram showing another embodiment of the output circuit according to the present invention. In this embodiment, the control signal UP2 {i} or DN2 {i} is fixed to the high level (VDD) or the low level (VSS), and the output signal waveform is changed so that all of the parallel MOSFETs are turned on. The output impedance when doing so is the minimum impedance. This eliminates the need for a circuit for generating the impedance control signal UP2 {i} or DN2 {i}, so that the layout area can be greatly reduced, and the chip size can be reduced accordingly. For example, the fuse means for forming UP2 {i}, and the addition (subtraction) circuit and multiplication (division) circuit as in the embodiments of FIGS. 8 and 9 are not required.

  Furthermore, when the selection circuit SEL1 or SEL2 switches the control signal from UP2 {i} or DN2 {i} to UP1 {i} or DN1 {i}, the output MOS that switches from the off state to the on state can be eliminated. Therefore, the generation of abnormal impedance due to the control signal timing skew can be prevented. Also, by combining the output slew rate control circuit (FIGS. 10 to 15) with this embodiment, pre-emphasis with a low layout area can be achieved without causing overshoot (waveform disturbance due to excessive injection of high frequency components) more than necessary. An output circuit can be configured.

  FIG. 17 is a block diagram showing still another embodiment of the output circuit according to the present invention. This embodiment is a modification of the embodiment of FIG. 16, and diodes D1 and D2 and a resistor RO are added to the output terminal. In this way, electrostatic breakdown can be prevented, and the non-linearity of the resistance characteristics of the output MOSFET can be improved. Further, the power supply voltage VDDQ is used. This power supply voltage VDDQ is an independent power supply terminal directed to the output circuit, and is effective in making it difficult for noise generated at the power supply terminal to be transmitted to the internal circuit in the internal circuit of the semiconductor integrated circuit device. Such a power supply terminal VDDQ can be similarly applied to the other embodiments. Similarly, the ground terminal VSS of the circuit is also a ground terminal VSSQ independent of the ground terminal of the internal circuit.

  FIG. 18 is a block diagram showing an embodiment of a pull-up circuit and a pull-down circuit constituting the output circuit according to the present invention. FIG. 2A shows a layout structure, and FIG. 2B shows an equivalent circuit corresponding thereto. In this embodiment, the output pin (PAD) is arranged in the order of an ESD (electrostatic breakdown) protection diode (p + diode, n + diode), a resistance element, NMOS (N-channel MOSFET), and PMOS (P-channel MOSFET). The basic configuration is a layout connected by a single wiring. A single output circuit is configured by arranging the output buffers of this basic configuration in stripes in parallel to the direction perpendicular to the linear wiring, as many as necessary for impedance adjustment and slew rate adjustment. can do.

  FIG. 19 shows a layout diagram of an embodiment of an output circuit according to the present invention. In this embodiment, the impedance is controlled by selecting the output buffer cells (R / 2, R, 2R, 4R) that are divided into equal ratios with binary (binary) impedance codes. Further, the stripe unit (R / 2, R) having a small impedance increases the size (W) of the MOSFET and decreases the resistance size. On the other hand, the stripe unit (2R, 4R) having a large impedance is configured to have a small MOS size and a large resistance size.

  That is, since the on-resistance value of the MOSFET is inversely proportional to the gate size (W) and the resistance value of the resistance element is proportional to the layout size, the ratio of the on-resistance value of the output buffer and the resistance element is the same, By adjusting the shape of the layout, the impedance is changed without changing the cell height (the length in the wiring direction). Therefore, even if the height of the stripe unit cell is the same in each impedance division cell, there is an effect that it is possible to achieve high integration because it is not necessary to create a useless space.

  FIG. 20 is a block diagram showing one embodiment of a semiconductor memory to which the present invention is applied. In the figure, XADR is a row address signal, YADR is a column address signal, DIN is a data input signal, CTRL is a memory control signal, and DOUT is a data output signal. XDEC is a row address decoder, XDR is a word line driver that applies a selection pulse voltage to a word line corresponding to the row address, and MCA is a memory cell array in which a plurality of memory cells are arranged in a matrix. YDEC is a column address decoder, YSW is a column selection circuit for selecting a bit line pair corresponding to the column address, and DIO writes a data input signal DIN to the selected cell based on the memory control signal CTRL, or information on the selected cell Is a data input / output circuit that outputs a data output signal DOUT. The output buffer described above is included in the data input / output circuit DIO.

  FIG. 21 is a block diagram showing an embodiment of the circuit configuration of the portion related to the present invention in the data input / output circuit DIO of FIG. In the figure, DIN is a data input signal, and DOUT is a data output signal. DIB is a data input circuit, and DQB is a data output circuit. RTE is a resistor for adjusting the input impedance of the terminal that receives the data input signal. In this embodiment, the impedance control circuit IMCNTT adjusts the resistance value of the RTE based on the resistance value of the resistor RT connected to the terminal ZT. Like to do. RQE is a resistor for adjusting the output impedance of the terminal that transmits the data output signal, and corresponds to, for example, the output impedance of the output circuit in the above embodiment. In this embodiment, the impedance control circuit IMCNTQ controls the RQE to a predetermined impedance based on the resistance value of the resistor RQ connected to the terminal ZQ. Further, when the output signal waveform transitions, the RQE is changed from the predetermined impedance. The output impedance is returned to the predetermined impedance after a certain time.

  In this embodiment, a fuse circuit FUSECT is added so that the stop signal of the pre-emphasis function, the amount of decrease in the output impedance at the time of the output transition, or the time for returning the impedance (the delay time) can be controlled by the fuse signal. I have to. That is, the control signals ISEL1 and ISEL2 in FIG. 5, the control signals φi and / φi in FIG. 6 or the control signals DLCTRL0 to DLCTRL2 in FIG. 7 are set by the fuse circuit FUSECT, and the addition in the embodiments of FIGS. The (subtraction) amount adjustment and the multiplication (division) amount adjustment are set by the fuse circuit FUSECT.

  FIG. 22 is a block diagram showing another embodiment of the circuit configuration of the portion related to the present invention in the data input / output circuit DIO of FIG. In the figure, DIN is a data input signal, and DOUT is a data output signal. DIB is a data input circuit, and DQB is a data output circuit. RTE is a resistor for adjusting the input impedance of the terminal that receives the data input signal. In this embodiment, the impedance control circuit IMCNTT adjusts the resistance value of the RTE based on the resistance value of the resistor RT connected to the terminal ZT. Like to do.

  RQE is a resistor for adjusting the output impedance of the terminal that transmits the data output signal, and corresponds to, for example, the output impedance of the output circuit in the above embodiment. In this embodiment, the impedance control circuit IMCNTQ controls the RQE to a predetermined impedance based on the resistance value of the resistor RQ connected to the terminal ZQ. Further, when the output signal waveform transitions, the RQE is changed from the predetermined impedance. The output impedance is returned to the predetermined impedance after a certain time.

  In this embodiment, the control circuit JTRCNT using JTAG (IEEE standard 1149.1 proposed by Joint Test Action Group) is based on the JTAG input signals (TCK, TMS, TDI), and the pre-emphasis function stop signal and the output The amount of decrease in impedance or the time for restoring the impedance can be controlled. That is, the control circuit JTRCNT performs the same control instead of the fuse circuit FUSECT shown in FIG.

  FIG. 23 is a block diagram showing still another embodiment of the circuit configuration of the portion related to the present invention in the data input / output circuit DIO of FIG. In the figure, DIN is a data input signal and DOUT is a data output signal. DIB is a data input circuit, and DQB is a data output circuit. RTE is a resistor for adjusting the input impedance of the terminal that receives the data input signal. In this embodiment, the impedance control circuit IMCNTT adjusts the resistance value of the RTE based on the resistance value of the resistor RT connected to the terminal ZT. Like to do. RQE is a resistor for adjusting the output impedance of the terminal that transmits the data output signal, and corresponds to, for example, the output impedance of the output circuit in the above example.

  In this embodiment, the impedance control circuit IMCNTQ controls the RQE to a predetermined impedance based on the resistance value of the resistor RQ connected to the terminal ZQ, and the RQE is lower than the predetermined impedance when the output signal waveform changes. Then, the output impedance is returned to the predetermined impedance after a predetermined time. In this embodiment, a control circuit IMCNTP is added so that the amount of decrease in the output impedance can be controlled based on the resistance value of the resistor RP in which IMCNTP is connected to the terminal ZP. In this case, in addition to those using the signal generation circuit as shown in FIGS. 8 and 9, the output impedance lowered when the output signal waveform transitions may be directly set by the resistor RP.

  FIG. 24 is a block diagram showing another embodiment of the semiconductor memory to which the present invention is applied. In this embodiment, as in the embodiment of FIG. 20, XADR is a row address signal, YADR is a column address signal, CTRL is a memory control signal, and DQ is a data input / output signal. This embodiment is different from the embodiment of FIG. 20 in that the data input terminal DIN and the data output terminal DOUT are separated in the embodiment of FIG. This is common to the input / output terminal DQ.

  In this embodiment, XDEC is a row address decoder, XDR is a word line driver that applies a selection pulse voltage to a word line corresponding to a row address, and MCA is a memory cell array in which a plurality of memory cells are arranged in a matrix. YDEC is a column address decoder, YSW is a column selection circuit that selects a bit line pair corresponding to the column address, DIO writes a data input / output signal DQ to a selected cell based on a memory control signal CTRL, or A data input / output circuit that amplifies information and outputs a data input / output signal DQ. The aforementioned output circuit is included in the data input / output circuit DIO.

  FIG. 25 is a block diagram showing an embodiment of a circuit configuration of a portion related to the present invention in the data input / output circuit DIO of FIG. In the figure, DQ is a data input / output signal. DIB is a data input circuit, and DQB is a data output circuit. RTE is a resistor for adjusting the input impedance of the terminal for transmitting and receiving data input / output signals. In this embodiment, the impedance control circuit IMCNTT determines the resistance value of RTE based on the resistance value of the resistor RT connected to the terminal ZT. I try to adjust it. RQE is a resistor for adjusting the output impedance of a terminal that transmits and receives data input / output signals, and corresponds to, for example, the output impedance of the output circuit in the embodiment.

  In this embodiment, the impedance control circuit IMCNTQ controls the RQE to a predetermined impedance based on the resistance value of the resistor RQ connected to the terminal ZQ. Further, when the output signal waveform transitions, the RQE is changed from the predetermined impedance. The output impedance is returned to the predetermined impedance after a certain time. Further, in this embodiment, a fuse circuit FUSECT is added so that the amount of decrease in the output impedance or the time for returning the impedance can be controlled by the fuse signal.

  FIG. 26 is a block diagram showing another embodiment of the circuit configuration of the portion related to the present invention in the data input / output circuit DIO of FIG. In the figure, DQ is a data input / output signal. DIB is a data input circuit, and DQB is a data output circuit. RTE is a resistor for adjusting the input impedance of a terminal that transmits and receives data input / output signals. In this embodiment, the impedance control circuit IMCNTT determines the resistance value of the RTE based on the resistance value of the resistor RT connected to the terminal ZT. I try to adjust it. RQE is a resistor for adjusting the output impedance of a terminal that transmits and receives data input / output signals, and corresponds to, for example, the output impedance of the output circuit in the embodiment. In this embodiment, a resistor RC is further added. Since this resistor RC operates both when data is input and when data is output, it can be used in common for adjusting the input impedance and the output impedance. Sharing in this way has the effect of reducing the layout area of the input / output circuit accordingly.

  In this embodiment, the impedance control circuit IMCNTQ controls RQE and RC to a predetermined impedance based on the resistance value of the resistor RQ connected to the terminal ZQ, and further, at least of RQE or RC when the output signal waveform transitions. One is controlled so as to be lower than the predetermined impedance, and then the impedance is returned to the predetermined impedance after a certain time. In this embodiment, a fuse circuit FUSECT is added so that the amount of decrease in the impedance or the time for restoring the impedance can be controlled by a fuse signal as in FIG.

  FIG. 27 is a block diagram showing an embodiment of the impedance control circuit used in the present invention. In the impedance control circuit IMCNT of this embodiment, the resistance value of the resistance element RP connected between the LSI external terminal ZP and the ground (the ground potential VSS of the circuit) is equal to the on-resistance value of the replica MOSFET 1 in the LSI. In other words, the comparator VC1 and the counter CNT1 (UP / DOWN: up / down) that control the reference voltage to VDD / 2 so that the external terminal ZP voltage becomes equal to 1/2 of the power supply voltage VDD, and the control is thereby performed. The pull-up replica MOSFET 1 is used to form a feedback loop, and the counter CNT1 is transmitted to the register REG1 to generate the impedance adjustment code UP2 <0: n> for the pull-up circuit. That is, the count value of the counter circuit CNT1 is set by the feedback loop so that the voltage of the impedance control terminal ZP is closest to 1/2 of VDD.

  The impedance adjustment code DN2 <0: n> for the pull-down circuit is generated in the same manner. In other words, a voltage dividing circuit for the power supply voltage VDD is configured by the pull-up replica circuit MOSFET 1 ′ and the pull-down replica circuit MOSFET 2 having the same configuration as the pull-up replica circuit MOSFET 1 so that the divided voltage becomes 1/2 of the power supply voltage VDD. A feedback loop is configured by a comparator VC2 having a reference voltage of VDD / 2, a counter circuit CNT2 (UP / DOWN: up / down), and a pull-down replica circuit MOSFET 2 controlled thereby, and the pull-down circuit of the pull-down circuit is controlled from the register REG2. Impedance adjustment code DN2 <0: n> is generated.

  As described above, the reference voltage of the comparator VC1 is ½ of the power supply voltage VDD. This is advantageous in that the replica circuit MOSFET 1 'serving as a copy of the pull-up replica circuit MOSFET 1 can be used instead of the external resistor RP when generating the impedance code on the pull-down side, and the circuit configuration can be simplified. The generated impedance code is shifted by an arbitrary number of bits in a code shift circuit if necessary. The shift amount is set by a control signal. If there is a problem that the termination resistance value shifts higher as the input potential shifts from VDD / 2 due to the nonlinearity of the on-resistance of the MOSFET, for example, correction by code shift by 2-bit shift You may make it solve by putting.

  The impedance control circuit IMCNT shown in the figure can be used for the impedance control circuits IMCNTQ, IMCNTT, and IMCNTP shown in FIGS. When the output impedance at the time of signal transition is set directly by the impedance control circuit IMCNTP, in other words, when the control signal DN2 <0: N> is generated, the resistance value of the resistor RP connected to the external terminal ZP is set to Set to the above output impedance. In this case, the MOS size of the replica portion is M times the MOS size of the output buffer (M is a positive real number), and the output impedance is configured to be 1 / M of the resistance value of the external resistor. .

  In the impedance control circuit of this embodiment, the control signal is updated every Q cycles (Q is a positive real number), and automatically (when the system is operating) even when there are process variations or changes in temperature or power supply voltage. The impedance is adjusted to be within the specified value. This makes it possible to control the output impedance, the input impedance, the output impedance when the output signal waveform transitions, and the like by the resistance value of the resistor RP depending on the system situation in which the semiconductor integrated circuit device LSI is mounted. . Furthermore, even when there are process variations or changes in temperature or power supply voltage, these impedances can be kept within specified values.

  FIG. 28 is a block diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention. In this embodiment, a plurality of output circuits are provided, and impedance control signals UP1 <0: n> and UP2 <0: formed by control signal generation circuits provided in common to the plurality of output circuits. n>, DN1 <0: n>, and DN2 <0: n> are transmitted to a plurality of output circuits through the distribution system circuit. The output circuit outputs the output data signal IN formed by the output control system circuit in accordance with the impedance control signals UP1 <0: n>, UP2 <0: n>, DN1 <0: n>, DN2 <0: n>. An output operation is performed in response to the enable signal CTRL. In this embodiment, the impedance control signal generation circuit and the control signal selection circuit are configured to be shared by all output circuits or a part of output circuits (for example, output circuits for each byte). In this way, the layout area of the impedance control signal generation circuit and the control signal selection circuit can be greatly reduced, and the chip size can be reduced accordingly.

  FIG. 29 is a block diagram showing another embodiment of the semiconductor integrated circuit device according to the present invention. In this embodiment, the control signals UP2 <0: n> and DN2 <0: n> can be generated for each output byte or for each specific output pin. In this way, depending on the situation where the semiconductor integrated device is mounted, even if it is connected to a transmission line having different transmission characteristics for each output byte or for each specific output pin, the impedance is controlled independently according to each characteristic. can do. For example, it is possible to correspond to one that outputs a high frequency signal to a relatively long transmission line, one that outputs to a short transmission line, or one that outputs a relatively low frequency signal.

  FIG. 30 shows a chip layout of an embodiment of a semiconductor memory to which the present invention is applied. In the figure, MUL0 to MUL7, MUR0 to MUR7, MLL0 to MLL7, and MLR0 to MLR7 are cell arrays in which memory cells are arranged in an array, and MWD is a main word driver. CK / ADR / CNTL is an input circuit for clock signals, address signals, memory control signals, etc. DI / DQ is a data input / output circuit, I / O is an input / output circuit for mode switching signals, test signals, DC signals, etc. is there.

  The semiconductor memory of this embodiment shows an example of the center pad type, and therefore the CK / ADR / CNTL circuit, DI / DQ circuit, and I / O circuit are also located in the center of the chip. REG / PDEC is a predecoder, DLLL is a clock synchronization circuit, JTAG / TAP is a test circuit, and VG is an internal power supply voltage generation circuit. Fuse is a fuse circuit, and is used for memory array defect relief or the like. VREF generates a reference voltage for capturing an input signal. Here, the output circuit according to the present invention is arranged at or near the data input / output circuit DI / DQ.

  FIG. 31 is a block diagram showing one embodiment of a semiconductor integrated circuit device to which the present invention is applied. In the figure, MPU is an arithmetic unit, MEM is a memory unit, and I / O is an input / output unit. The output circuit described above is applied to the I / O unit. When the arithmetic unit MPU, the memory unit MEM, and the input / output circuit I / O to which the present invention is applied are formed on the same semiconductor substrate, the arithmetic unit MPU performs the memory unit MEM and the input / output circuit I / O for a certain process. Since operations can be performed while exchanging data at high speed, there is an effect that the total processing performance can be improved.

  FIG. 32 shows a block diagram of an embodiment of a system including a semiconductor integrated circuit device to which the present invention is applied. In a semiconductor integrated circuit device, a master and a slave configured by the semiconductor integrated circuit device are connected by using a printed wiring formed on a mother board (mounting substrate) as a transmission line. For this reason, the output impedance of the output circuit is set so as to match the characteristic impedance of the printed wiring or the like, and is temporarily controlled to be smaller than the characteristic impedance at the time of signal transition, thereby enabling high-speed signal transmission with high quality. Can be done.

  FIG. 33 is a block diagram showing another embodiment of a system including a semiconductor integrated circuit device to which the present invention is applied. A semiconductor integrated circuit device is mounted with a master (or slave) composed of a semiconductor integrated circuit device using a printed wiring formed on a mother board (mounting substrate) as a part of a transmission line. The printed wiring of the motherboard is connected to one or more connectors, and one or more DIMM integrated semiconductor integrated circuit device slaves are connected via the one or more connectors. Also in this embodiment, the output impedance is controlled in accordance with the output operation of the output circuit so as to be adapted to the transmission line.

  FIG. 34 shows a waveform diagram of a received signal on the input circuit side corresponding to the output circuit to which the present invention is applied. As described above, by taking into account the dielectric loss tangent (dielectric loss) and skin effect (resistance loss) on the transmission line, pre-emphasis of injecting high frequency components is performed to compensate for the reduction of the high frequency components on the receiving side. The data window can be enlarged. FIG. 35 shows a waveform diagram for comparison when the pre-emphasis is not performed under the same conditions. From the comparison between FIG. 34 and FIG. 35, it can be seen that the data window can be significantly enlarged by applying the present invention.

  The invention made by the inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, a circuit that generates the control signals UP1 <0: n>, DN1 <0: n>, UP2 <0: n>, DN2 <0: n> can take various embodiments. The present invention can be widely applied to not only those that perform high-speed operations such as SRAM as a general-purpose memory, but also those that include a circuit such as an SRAM embedded in a semiconductor integrated circuit device such as a system LSI. .

1 is a block diagram showing an embodiment of an output circuit mounted on a semiconductor integrated circuit device according to the present invention. FIG. 2 is a timing waveform diagram for conceptually explaining an example of the operation of the output circuit of FIG. 1. FIG. 2 is a configuration diagram illustrating a specific example of a selection circuit, a pull-up circuit, and a pull-down circuit in FIG. 1. It is a circuit diagram which shows one Example of the selection circuit used for this invention. It is a circuit diagram which shows another Example of the selection circuit used for this invention. FIG. 2 is a configuration diagram illustrating an example of the delay circuit of FIG. 1. FIG. 3 is a circuit diagram showing another embodiment of the delay circuit of FIG. 1. 3 is a block diagram showing an embodiment of a control signal generation circuit used in the output circuit according to the present invention. It is a block diagram which shows another Example of the production | generation circuit of the control signal used for the output circuit which concerns on this invention. It is a circuit diagram which shows another Example of the selection circuit used for this invention. It is a circuit diagram which shows another Example of the selection circuit used for this invention. FIG. 11 is a circuit diagram showing an embodiment of a selection circuit including the slew rate control circuit of FIG. 10. FIG. 12 is a circuit diagram showing an embodiment of a selection circuit including the slew rate control circuit of FIG. 11. FIG. 11 is a circuit diagram showing another embodiment of a selection circuit including the slew rate control circuit of FIG. 10. FIG. 12 is a circuit diagram illustrating another embodiment of a selection circuit including the slew rate control circuit of FIG. 11. It is a block diagram which shows another Example of the output circuit based on this invention. It is a block diagram which shows another one Example of the output circuit based on this invention. It is a block diagram which shows one Example of the pull-up circuit and pull-down circuit which comprise the output circuit based on this invention. 1 is a layout diagram showing an embodiment of an output circuit according to the present invention. It is a block diagram which shows one Example of the semiconductor memory to which this invention is applied. FIG. 21 is a block diagram showing an embodiment of a circuit configuration of a portion related to the present invention in the data input / output circuit DIO of FIG. 20. FIG. 21 is a block diagram showing another embodiment of the circuit configuration of the portion related to the present invention in the data input / output circuit DIO of FIG. 20. FIG. 21 is a block diagram showing still another embodiment of a circuit configuration of a portion related to the present invention in the data input / output circuit DIO of FIG. 20. It is a block diagram which shows the other Example of the semiconductor memory to which this invention is applied. FIG. 25 is a block diagram showing an embodiment of a circuit configuration of a portion related to the present invention in the data input / output circuit DIO of FIG. 24. FIG. 25 is a block diagram showing another embodiment of the circuit configuration of the portion related to the present invention in the data input / output circuit DIO of FIG. 24. It is a block diagram which shows one Example of the impedance control circuit used for this invention. 1 is a block diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention. It is a block diagram which shows another Example of the semiconductor integrated circuit device based on this invention. 1 is a chip layout diagram showing an embodiment of a semiconductor memory to which the present invention is applied; 1 is a block diagram showing an embodiment of a semiconductor integrated circuit device to which the present invention is applied. 1 is a configuration diagram showing an embodiment of a system including a semiconductor integrated circuit device to which the present invention is applied. It is a block diagram which shows another Example of the system provided with the semiconductor integrated circuit device with which this invention is applied. It is a wave form diagram of the received signal by the side of the input circuit corresponding to the output circuit to which this invention was applied. It is a wave form diagram of the received signal by the side of the input circuit corresponding to the output circuit to which this invention is not applied.

Explanation of symbols

MOSFET1 ... pull-up circuit, MOSFET2 ... pull-down circuit, SEL1, SEL2 ... selection circuit, DLP, DLN ... delay circuit, G1-G17 ... gate circuit, C0-C2 ... capacitance, RS, RO ... resistor, Q1-Q8, QP, QN ... MOSFET, INV1 to INV13 ... Inverter circuit, IMCNT, IMCTQ, IMCNTT, IMCNTP ... impedance control circuit, DIB ... input circuit, DOQ ... output circuit, FUSECT ... fuse circuit, INCKT ... internal circuit, CNT1, CNT2 ... counter circuit, VC1, VC2 ... voltage comparison circuit, REG1, REG2 ... register, LSI ... semiconductor integrated circuit device,
XADR ... row address signal, YADR ... column address signal, XDEC ... row address decoder, XDR ... word line driver, MCA ... memory cell array, YDEC ... column address decoder, YSW ... column selection circuit, DIO ... data input / output circuit, INCKT ... Internal circuit, DIB ... Data input buffer, DQPB ... Output prebuffer, DQO ... Output buffer, IMCNTT ... Impedance control circuit, IMCNTQ ... Impedance control circuit, JTRCNT ... Slew rate control circuit,
MUL0 to MUL7, MUR0 to MUR7, MLL0 to MLL7, MLR0 to MLR7 ... Cell array, MWD ... Main word driver, CK / ADR / CNTL ... Input circuit, DI / DQ ... Data input / output circuit, I / O ... Input / output circuit, REG / PDEC: Predecoder, etc. DLLC: Synchronization circuit, JTAG / TAP: Test circuit, VG: Internal power supply voltage generation circuit, Fuse: Fuse circuit, VREF: Reference voltage generation circuit

Claims (14)

Provided with an output circuit in which a plurality of output impedances are set by a combination of a plurality of output MOSFETs,
A first control signal for specifying a combination of the plurality of output MOSFETs having an output impedance of the output circuit as a first output impedance; and the plurality of outputs having a second output impedance different from the first output impedance. Forming a second control signal designating a combination of MOSFETs;
The output signal is formed by the first output impedance set based on the first control signal corresponding to the signal change timing of the input signal input to the output circuit, and delayed by the signal change timing of the input signal A semiconductor integrated circuit device characterized in that an output signal is formed by a second output impedance set based on the second control signal after the first time has elapsed. In claim 1,
The second output impedance is set to match the characteristic impedance of the transmission line through which the output signal is transmitted,
The semiconductor integrated circuit device, wherein the first output impedance is set to be smaller than the second output impedance. In claim 2,
The semiconductor integrated circuit device according to claim 1, wherein the first time is set to be smaller than twice the delay time of the transmission line. In claim 3,
The semiconductor integrated circuit device, wherein the first time can be set by a control signal input from the outside of the semiconductor integrated circuit device. In claim 3,
2. The semiconductor integrated circuit device according to claim 1, wherein the first time is settable by a control signal formed by a storage element which can be written. In claim 3,
The semiconductor integrated circuit device, wherein the first control signal is formed by an arithmetic circuit having a constant difference with respect to the second control signal. In claim 3,
The semiconductor integrated circuit device, wherein the first control signal is formed by an arithmetic circuit having a constant ratio with respect to the second control signal. In claim 3,
The semiconductor integrated device, wherein the constant difference or the constant ratio can be set by a control signal input from the outside of the semiconductor integrated circuit device or a control signal formed in a writable memory element. In claim 3,
The semiconductor integrated circuit device according to claim 1, wherein the first control signal corresponds to a minimum value among a plurality of output impedances. In claim 3,
And a slew rate control circuit for adjusting a slew rate of the output signal by adjusting a change amount of the drive signal transmitted to the gate of the output MOSFET which is turned on in response to the first control signal. A semiconductor integrated circuit device. In claim 3,
2. The semiconductor integrated circuit device according to claim 1, wherein the second output impedance is set by a second control signal formed by an internal circuit based on a resistance value of a resistance element connected to an external terminal. In claim 3,
The semiconductor integrated circuit device according to claim 1, wherein the first output impedance is set by a first control signal formed in an internal circuit based on a resistance value of a resistance element connected to an external terminal. In claim 3,
The output circuit is composed of a plurality of
The semiconductor integrated circuit device, wherein the first control signal and the second control signal are commonly used for all output circuits. In claim 3,
The output circuit is divided into a plurality of blocks.
A semiconductor integrated circuit device, wherein the first control signal and the second control signal are formed for each block.

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