KR100897295B1 - Bulk bias voltage generator of semiconductor memory apparatus - Google Patents

Abstract

Disclosed is a bulk bias voltage generation circuit of a semiconductor memory device, comprising: a detector configured to generate an enable signal by comparing an input voltage and a reference voltage, and an internal voltage enable signal by comparing an internal voltage and an internal reference voltage A voltage detector, an internal voltage oscillator configured to receive the enable signal and the internal voltage enable signal and generate an internal voltage oscillation signal having a variable period, and an internal to generate the internal voltage in response to the internal voltage oscillation signal And a voltage pump unit, wherein the internal voltage oscillator includes a plurality of oscillation signal generators to selectively provide a path of the internal voltage oscillation signal having a quantitative periodic difference according to the level of the input voltage.

Bulk Bias Voltage (Vbb), Step-Up Voltage (Vpp), External Voltage (Vdd), Latch-Up, Pump

Description

Bulk Bias Voltage Generator Circuit of Semiconductor Memory Device {Bulk Bias Voltage Generator of Semiconductor Memory Apparatus}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a bulk bias voltage generation circuit for reducing the size of a bulk bias voltage pump and stabilizing the bulk bias voltage.

In a semiconductor memory device, a stable voltage is internally used to reduce power consumption without being affected by a change in the external voltage VDD. These internal voltages are of various types such as bulk bias voltage (Vbb), boosted voltage (Vpp), core voltage (Vcore). The bulk bias voltage Vbb is used as the bulk bias of the cell with a negative voltage lower than the ground voltage. The bulk bias voltage Vbb may increase the threshold voltage Vth of the cell transistor to reduce the leakage current. However, when the bulk bias voltage Vbb is used, there is a risk that the bulk bias voltage Vbb is unstable and latch-up occurs.

Here, the core voltage Vcore is generated by transforming the external voltage Vdd, and generally has a value slightly lower than the external voltage Vdd in normal operation. The core voltage Vcore is mainly used for a bit line sense amplifier amplification circuit. The boosted voltage Vpp is generated by boosting the external voltage Vdd and has a voltage level higher than the external voltage Vdd. The boost voltage Vpp is used to compensate for the loss of the threshold voltage Vt of a cell transistor or to control a gate of a bit line isolation transistor or a word line driving circuit for controlling a gate of the cell transistor. Used.

1 is a circuit diagram of a general latch-up structure, and FIG. 2 is a circuit diagram showing an operation principle of a general CMOS.

Referring to FIG. 1, when the voltage boosting voltage Vpp becomes lower than the external voltage Vdd due to insufficient supply capability of the voltage boosting voltage Vpp, which is an initial voltage boosting voltage, the first bipolar transistor BJT1 is turned on and bulk. The bias voltage Vbb is increased. Thereafter, the second bipolar transistor BJT2 is turned on by the elevated bulk bias voltage Vbb. Due to the operation as described above, the voltage drop of the boosted voltage Vpp is accelerated to the ground VSS terminal, and the bulk bias voltage Vbb rapidly rises to generate a latchup. In this case, current flows through the first and second bipolar transistors BJT1 and BJT2 itself, and the first and second bipolar transistors BJT1 and BJT2 may be destroyed. Such a latch-up occurs frequently when the external voltage Vdd is low when the external memory is applied to the semiconductor memory device, and thus the driving force of the bulk bias voltage pump and the boost voltage pump is weak.

Referring to FIG. 2, a low external voltage Vdd is initially applied to the semiconductor memory device so that the driving force of the bulk bias voltage pump Vbb pump is insufficient. At this time, if the outside of the N-Well of the cell region is the boosted voltage Vpp and the outside of the P-Well is the bulk bias voltage Vbb, between the bulk bias voltage Vbb and the boosted voltage Vpp. Since the existing coupling capacitance is very large, the potential of the bulk bias voltage Vbb having a weak driving force rises corresponding to the potential of the boosted voltage Vpp. At this time, as the second bipolar transistor BJT2 is turned on, latch-up occurs.

3 is a block diagram of a bulk bias voltage generation circuit according to the prior art.

Referring to FIG. 3, the bulk bias voltage generation circuit according to the related art is a differential amplifier type that outputs a bulk bias detection signal Vbb_VA by comparing the levels of the bulk bias reference voltage Vbbref and the bulk bias voltage Vbb. A detector 10, an oscillator 20 which oscillates in response to the bulk bias detection signal Vbb_VA and outputs a bulk bias oscillation signal Vbbosc in the form of a pulse, and receives the bulk bias oscillation signal Vbbosc to perform a boost operation. A pump 30 for performing.

The oscillator 20 includes an odd number of inverters forming a loop to output a bulk bias oscillation signal Vbbosc in the form of a pulse.

The pump 30 may generally use a well-known mode pump circuit, and performs a boost operation according to the bulk bias oscillation signal Vbbosc to generate the stable bulk bias voltage Vbb.

According to the prior art, the bulk bias voltage generation circuit may have the bulk bias detection signal Vbb_VA low when the bulk bias voltage Vbb is higher than the bulk bias reference voltage Vbbref (that is, when latchup occurs). Level enabled, outputs a bulk bias oscillation signal Vbbosc having a constant pulse width. The bulk bias oscillation signal Vbbosc stabilizes the bulk bias voltage Vbb by performing a boost operation once every oscillation.

The current consumption of the bulk bias voltage Vbb generated during the normal operation of the bulk bias voltage generation circuit according to the prior art is very small. That is, the size of the pump 30 for generating the bulk bias voltage vbb is very small. The size of the pump 30 is designed based on the amount of current so that latch-up does not occur when an initial external voltage Vdd is applied, rather than the amount of current required for operation of the semiconductor memory device. When the size of the pump 30 is reduced, a latch-up occurs in an initial situation in which an external voltage Vdd is applied, so that a pump having a larger area than that of the pump 30 in operation of the semiconductor memory device is used. The problem which should be provided arises. In addition, the bulk bias voltage generation circuit has a problem that the bulk bias voltage Vbb value is not stable because the current is boosted too much each time a boost operation is performed.

The bulk bias voltage generation circuit of the semiconductor memory device according to the present invention has an object to prevent latch-up at the initial stage of power-up and to stabilize an internal voltage (bulk bias voltage Vbb).

A bulk bias voltage generation circuit of a semiconductor memory device according to the present invention includes a detector for generating an enable signal by comparing an input voltage and a reference voltage, and generating a bulk bias enable signal by comparing the bulk bias voltage and the bulk bias reference voltage. A bulk bias voltage detector, a bulk bias oscillator configured to receive the enable signal and the bulk bias enable signal and generate a bulk bias oscillation signal having a variable period, and generate the bulk bias voltage in response to the bulk bias oscillation signal And a bulk bias pump unit, wherein the internal voltage oscillator includes a plurality of oscillation signal generators to selectively provide a path of the internal voltage oscillation signal having a quantitative periodic difference according to the level of the input voltage.

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The bulk bias voltage generation circuit of the semiconductor memory device according to the present invention uses a small pump to shorten the pumping period at the beginning of power-up and to prevent the latch-up by lengthening the pumping period in normal operation, thereby providing stable internal voltage [bulk]. Bias voltage Vbb].

4 is a bulk bias voltage generation circuit of a semiconductor memory device according to the present invention.

In the conventional bulk bias voltage generation circuit, since the current consumption of the bulk bias voltage is small, the boosting operation is performed using a small pump. When the size of the pump is small, when the external voltage Vdd or the boosted voltage Vpp is applied at the initial stage of power-up, latch-up may occur. Since the size of the pump is designed based on the amount of current so that latch-up does not occur at the initial stage of power-up rather than the amount of current required for operation, a pump larger than the size of the pump required for operation should be provided. In addition, since the voltage is increased too much each time the voltage boosting operation is performed, the problem of the value of the internal voltage (bulk bias voltage Vbb) is unstable. In the present invention, when the level of the boosted voltage Vpp or the external voltage Vdd is low (that is, when latchup may occur), the pumping period is shortened to increase the number of boosting times, thereby generating a larger amount of current. In the case of performing the normal operation by increasing the level of the boosted voltage or the external voltage, the circuit is implemented such that a small amount of current is generated by reducing the number of boosting times by lengthening the pumping period.

Referring to FIG. 4, the internal bulk bias voltage generation circuit according to the present invention includes a boosted voltage sensing unit 100 configured to generate a boosted enable signal Vppen by comparing the boosted voltage Vpp and the boosted reference voltage Vppref. By comparing the external voltage detector 200 generating the external enable signal Vdden by comparing the external voltage Vdd and the external reference voltage Vddref, the bulk bias voltage Vbb and the bulk bias reference voltage Vbbref. Receiving a bulk bias voltage detector 300 for generating a bulk bias enable signal Vbben, the boost enable signal Vppen, the external enable signal Vdden, and the bulk bias signal Vbben. A bulk bias oscillator 400 for generating a bulk bias oscillation signal Vbbosc, and a bulk bias for generating the bulk bias voltage Vbb in response to the bulk bias oscillation signal Vbbosc. It includes a pump unit 500.

Here, the boosted reference voltage Vppref, the external reference voltage Vddref, and the bulk bias reference voltage Vbb refer to the boosted voltage Vpp, the external voltage Vdd, and the bulk bias voltage Vbb. It refers to the voltage that is the reference of potential that can occur. That is, if the boosted voltage Vpp, the external voltage Vdd, and the bulk bias voltage Vbb are voltages lower than the boosted reference voltage Vppref, the external reference voltage Vddref, and the bulk bias reference voltage Vbb, a latch-up occurs. do. On the contrary, if the boosted voltage Vpp, the external voltage Vdd, and the bulk bias voltage Vbb are higher than the boosted reference voltage Vppref, the external reference voltage Vddref, and the bulk bias reference voltage Vbb, normal operation is performed. .

The boosted voltage detector 100, the external voltage detector 200, and the bulk bias voltage detector 300 are detectors having the same configuration as that of the differential amplification type, and are boosted voltage (Vpp) and bulk bias. The voltage Vbb and the external voltage Vdd are respectively input and compared with the respective reference voltages Vppref, Vbbref and Vddref to output the output signals Vppen, Vbben and Vdden.

When the bulk bias oscillator 400 has a low boost voltage Vpp and a low external voltage Vdd in response to the output signals Vppen, Vbben, and Vdden, the bulk bias oscillation signal Vbbosc has a short pumping period. In the normal operation, the bulk bias oscillation signal Vbbosc outputs a long pumping period.

The bulk bias pump unit 500 may generally use all known pump circuits, and generates a larger amount of current when the pumping cycle is fast and generates a smaller amount of current when the pumping cycle is slow. do.

FIG. 5 is a circuit diagram of the boosted voltage detector 100, the external voltage detector 200, and the bulk bias voltage detector 300 shown in FIG. 4.

The boosted voltage detector 100, the external voltage detector 200, and the bulk bias voltage detector 300 correspond to input voltages Vpp, Vbb and Vdd and the input voltages Vpp, Vbb and Vdd, respectively. Only the reference voltages Vppref, Vbbref, and Vddref are different and have the same configuration.

For example, the boosted voltage detector 100 will be described.

Referring to FIG. 5, the boosted voltage detector 100 outputs a boosted voltage division unit Vpp_Level in response to a change in the boosted voltage Vpp, and the boosted voltage divider Vpp_Level. ) And a boosted voltage comparison unit 120 for comparing the potential level of the reference boosted voltage Vppref and outputting a boosted enable signal Vppen.

The boosted voltage divider 110 includes a plurality of resistors R1 to R4 connected in series between a boosted voltage Vpp terminal and a ground VSS terminal. The plurality of resistive elements may include a plurality of resistive elements for distributing voltage, but the present invention will be described using, for example, four resistive elements R1 to R4.

The boosted divided voltage Vpp_level is output from a node Vppnode that is divided into the plurality of resistors R1 to R4, and is a signal whose voltage level is changed in response to a change in the boosted voltage Vpp.

The boosted voltage comparator 120 is a general differential amplification type comparator, and includes a first NMOS transistor NM1, the boosted divided voltage Vpp_level and the boosted reference that are activated in response to the boosted divided voltage Vpp_level. Second and third NMOS transistors NM2 and NM3 that receive a voltage Vppref, respectively, and first and second PMOS transistors PM1 and PM2 in the form of current mirrors.

The first NMOS transistor NM1 includes a gate configured to receive the boosted distribution voltage Vpp_level, a drain connected to the first node N1, and a source connected to the ground VSS terminal. The second NMOS transistor NM2 includes a gate configured to receive the boosted distribution voltage Vpp_level, a drain connected to the second node N2, and a source connected to the first node N1. The third NMOS transistor NM3 includes a gate receiving the boosted reference voltage Vppref, a drain connected to the third node N3, and a source connected to the first node N1. The first PMOS transistor PM1 includes a gate connected to the third node N3, a source connected to an external voltage VDD terminal, and a drain connected to the second node N2. The second PMOS transistor PM2 includes a gate and a drain commonly connected to the third node N3, and a source connected to an external voltage VDD terminal. The second node N2 outputs the boost enable signal Vppen.

More specifically, for example, assuming a boost voltage Vpp at which latchup may occur is 2.8V, the boost reference voltage Vppref is designed to be 1.4V. When the boosted voltage is 2.8 V or less, the boost enable signal Vppen becomes a high level because the potential level of the boosted reference voltage Vppref is high. When the boosted voltage is 2.8V or more, the boosted divided voltage ( The boost enable signal Vppen goes low because the potential level of Vpp_level is higher.

When the potential level of the external divided voltage Vdd_level is lower than the external reference voltage Vddref, the external enable signal Vdden becomes a high level and the external divided voltage Vdd_level. When the potential level of is higher than the external reference voltage Vddref, the external enable signal Vdden becomes a low level.

When the potential level of the bulk bias distribution voltage Vbb_level is lower than the bulk bias reference voltage Vbbref, the bulk bias voltage detection unit 300 becomes the high level and the bulk bias When the potential level of the division voltage Vbb_level is higher than the bulk bias reference voltage Vbbref, the bulk bias enable signal Vbben becomes a low level.

6 is a block diagram of a bulk bias oscillator shown in FIG. 4.

Referring to FIG. 6, the bulk bias oscillator 400 outputs a bulk bias oscillation signal Vbbosc in response to a bulk bias enable signal Vbben and a pulse oscillation signal Pulse_osc. In response to an external voltage enable signal Vdden, a boost enable signal Vppen, and the bulk bias oscillation signal Vbbosc, the pulse oscillation signal is controlled by controlling whether the bulk bias oscillation signal Vbbosc is delayed for a predetermined time. A second pulse generator 420 output as (Pulse_osc) is included.

When the bulk bias oscillator 400 is enabled, the bulk bias enable signal Vbben is enabled and any one of the external enable signal Vdden and the boost enable signal Vppen is enabled. A loop is formed between the pulse generator 410 and the second pulse generator 420 to generate the bulk bias oscillation signal Vbbosc having a short period. When the bulk bias enable signal Vbben is enabled and the external enable signal Vdden and the boost enable signal Vppen are disabled, the first pulse generator 410 and the second pulse are disabled. Loops are formed between the generators 420 to generate the bulk bias oscillation signal Vbbosc having a period of the predetermined time delay.

FIG. 7 is a circuit diagram of the bulk bias oscillator shown in FIG. 6.

Referring to FIG. 7, the first pulse generator 410 may include a first NOR gate NR1 and the first NOR gate that receive the bulk bias enable signal Vbben and the pulse oscillation signal Pulse_osc. Second to fourth inverters IV2 to IV4 that receive an output signal of NR1 and a first inverter IV1 and an output of the first inverter IV1, and form an inverter chain in which an output terminal and an input terminal are connected in series. ) And thirteenth to seventeenth resistors R13 to R17 connected to output terminals of the first to fourth inverters IV1 to IV4, respectively.

When the bulk bias enable signal Vbben is disabled at a high level, the first pulse generator 410 always sends a low level signal to the oscillation output node oscout regardless of the pulse oscillation signal Pulse_osc. Output When the bulk bias enable signal Vbben is enabled at a low level, the output level is controlled by the pulse oscillation signal Pulse_osc, and the level of the oscillation output node oscout is also changed. When the pulse oscillation signal Pulse_osc is high level, the level of the oscillation output node oscout becomes a low level, and when the pulse oscillation signal Pulse_osc is low level, the level of the oscillation output node oscput Becomes the high level.

The second pulse generator 420 outputs a pulse control signal PulseCTRL for controlling whether the bulk bias oscillation signal Vbbosc is delayed in response to an external enable signal Vdden and a boost enable signal Vppen. The pulse controller 421 outputs a pulse signal Pulse in response to the inverted signal of the pulse control signal PulseCTRL and the bulk bias oscillation signal Vbbosc, and the pulse control signal PulseCTRL. And a pulse delay unit 423 for outputting a pulse delay signal DLY_Pulse by controlling whether the bulk bias oscillation signal Vbbosc has a predetermined time delay in response to the bulk bias oscillation signal Vbbosc, and the pulse delay. And a signal combiner 424 for outputting the pulse oscillation signal Pulse_osc by logically combining the signal DLY_Pulse and the pulse signal Pulse.

The pulse controller 421 inverts the output signals of the second NOR gate NR2 and the second NOR gate NR2 that receive the external enable signal Vdden and the boost enable signal Vppen to control pulses. And a fifth inverter IV5 for outputting the signal PulseCTRL.

The pulse controller 421 outputs the high level pulse control signal PulseCTRL when any one of the external enable signal Vdden and the boost enable signal Vppen has a high level signal. When both the external enable signal Vdden and the boost enable signal Vppen have a low level signal, the pulse control signal PulseCTRL at a low level is output.

The pulse unit 422 includes a third NOR gate NR3 that receives an inverted signal of the pulse control signal PulseCTRL and the bulk bias oscillation signal Vbbosc. When the pulse control signal PulseCTRL is at a high level, the pulse unit 422 determines the level of the pulse signal Pulse by the bulk bias oscillation signal Vbbosc, and the pulse control signal PulseCTRL is low. If the level is low, the pulse signal Pulse having a low level is output regardless of the bulk bias oscillation signal Vbbosc. When the pulse control signal PulseCTRL is at a high level, the third NOR gate NR3 serves as an inverter, and when the high level bulk bias oscillation signal Vbbosc is applied, the pulse signal of a low level is pulsed. When the low-level bulk bias oscillation signal Vbbosc is applied, the high-level pulse signal Pulse is output.

The pulse delay unit 423 receives a fourth NOR gate N4 that receives the pulse control signal PulseCTRL and the bulk bias oscillation signal Vbbosc and an output signal of the fourth NOR gate NR4. A seventh inverter IV7, an eighth inverter IV8 connected in series with the seventh inverter IV7, and resistors R18 to R19 respectively connected to output terminals of the seventh and eighth inverters IV7 and IV8. .

The pulse delay unit 423 outputs a low level pulse delay signal DLY_Pulse when both the pulse control signal PulseCTRL and the bulk bias oscillation signal Vbbosc are at a low level, and outputs the pulse control signal PulseCTRL. ) And the bulk bias oscillation signal Vbbosc output a high level pulse delay signal DLY_Pulse.

The signal combination unit 424 includes a fifth NOR gate NR5 for receiving the pulse delay signal DLY_Pulse and the pulse signal Pulse.

The signal combination unit 424 outputs the low level pulse oscillation signal Pulse_osc when any one of the pulse delay signal DLY_Pulse and the pulse signal Pulse has a high level, and outputs the pulse delay signal ( When both the DLY_Pulse and the pulse signal Pulse have a low level, the pulse oscillation signal Pulse_osc of the high level is output.

The bulk bias enable signal Vbben is a low level enable signal, and the external enable signal Vdden and the boost enable signal Vppen are high level enable signals.

The pulse width of the bulk bias oscillation signal Vbbosc is determined by the amount of delay between the first pulse generator 410 and the second pulse generator 420. The first pulse generator 410 determines a period when a latchup occurs (when the pump voltage Vpp and the external voltage Vdd are low), and the second pulse generator 420 operates normally. At a time (when the boosted voltage Vpp and the external voltage Vdd become high), the cycle of the first pulse generator 410 is delayed for a predetermined time is determined.

More specifically, when the bulk bias enable signal Vbben is at a high level and any one of the external enable signal Vdden and the boost enable signal Vppen is at a high level, the oscillation output node. The signal at (oscout) goes low. The pulse control signal PulseCTRL becomes high level. The pulse unit 422 receives the high level control signal PulseCTRL and the signal of the low level oscillation output node oscout, and outputs a high level pulse signal Pulse. The signal combination unit 424 receiving the high level pulse signal Pulse outputs a low level pulse oscillation signal Pulse_osc regardless of the pulse delay signal DLY_Pulse. In this case, the first NOR gate NR always has the same output regardless of the pulse oscillation signal Pulse-osc.

As described above, when the bulk bias enable signal Vbben is enabled at a low level while any one of an external voltage enable signal Vdden and a boosted voltage enable signal Vppen is at a high level, the first NOR is enabled. The gate NR1 outputs a high level signal, and the oscillation output node oscout is at a high level. The pulse unit 422 receiving the signal of the oscillation output node oscout of the high level outputs the pulse signal Pulse of a low level, and the pulse delay signal DLY_Pulse fixed to a low level and the The signal combination unit 424 receiving the low level pulse signal Pulse outputs the high level pulse oscillation signal Pulse_osc. The high level pulse oscillation signal Pulse_osc is fed back to the first NOR gate NR1 to form a loop. The first NOR gate NR1 receiving the high level pulse oscillation signal Pulse_osc outputs a low level signal and passes the first to fourth inverters IV1 to IV4 to generate the first pulse generator. 410 outputs a low level signal to the oscillation output node oscout. The pulse unit 422 receives a signal of a low level oscillation output node oscout and outputs a low level pulse signal Pulse. The signal combination unit 424 receives the low level pulse signal Pulse and the low level pulse delay signal DLY_Pulse and outputs a low level pulse oscillation signal Pulse_osc. The low level pulse oscillation signal Pulse_osc is fed back to the first NOR gate NR1. The bulk bias pulse signal Pulse is output at the oscillation output node oscout. The bulk bias oscillator 400 is looped back to the first pulse generator 410 via the first pulse generator 410, the pulse unit 422, and the signal combination unit 424. And generate a pulse, and output the bulk bias oscillation signal Vbbosc whose period is determined by the delay value of the first pulse generator 410.

When the bulk bias enable signal Vbben is enabled at the low level and the external enable signal Vdden and the boost enable signal Vppen are disabled at the low level, the pulse controller 421 The pulse control signal PulseCTRL at a low level is output. The pulse unit 422 outputs a low level pulse signal Pulse regardless of the signal of the oscillation output node oscout, and the pulse oscillation signal Pulse_osc is leveled by the pulse delay signal DLY_Pulse. Is determined. When the signal of the oscillation output node oscout is at a high level, the fourth NOR gate NR4 plays a role of an inverter and outputs a low level signal, and the seventh and eighth inverters IV7 and IV8. And a low level pulse delay signal DLY_Pulse through the 17th and 18th resistors R17 and R18. The pulse oscillation signal Pulse_osc becomes a high level. The high level pulse oscillation signal Pulse_osc is fed back to the first NOR gate NR1. The first NOR gate NR1 outputs a low level signal, and the first pulse generator 410 is configured to control the pulse output node oscout via the first to fourth inverters IV1 to IV4. Output the signal at a low level. The fourth NOR gate NR4, which receives the signal of the low level pulse output node oscout, outputs a high level signal, and the seventh and eighth inverters IV7 and IV8 and the seventeenth and eighteenth resistors. The high-level pulse delay signal DLY_Pulse is output via (R17, R18). Therefore, the pulse oscillation signal Pulse_osc is at a low level. The low level pulse oscillation signal Pulse_osc is fed back to the first NOR gate NR1. The bulk bias oscillator 400 receives a loop input to the first pulse generator 410 via the first pulse generator 410, the pulse delay unit 422, and the signal combination unit 424. To generate a pulse. The bulk bias oscillator 400 outputs the bulk bias oscillation signal Vbbosc whose period is determined by the delay value of the pulse delay unit 422 in addition to the delay value of the first pulse generator 410. .

8 is a timing diagram of a bulk bias voltage generation circuit of a semiconductor memory device according to the present invention.

Referring to FIG. 8, in the bulk bias voltage generation circuit, the bulk bias voltage Vbb is increased to be higher than the bulk bias reference voltage Vbbref, and the boost voltage Vpp and the external voltage Vdd are latched up. If there is a risk of occurrence, the bulk bias enable signal Vbben is enabled at a low level, and the external enable signal Vdden and the boost enable signal Vppen are enabled at a high level. The bulk bias oscillation signal Vbbosc has a short period. Subsequently, when the boosted voltage Vpp and the external voltage Vdd are higher than the boosted reference voltage Vppref and the external reference voltage Vdd to perform a normal operation, the boosted enable signal Vppen and When the external enable signal Vdden is disabled at a low level, the bulk bias oscillation signal Vbbosc has a long period.

In the above description, the voltage Vbb, Vpp, and Vdd are changed using the boosted voltage detector 100, the external voltage detector 200, and the bulk bias voltage detector 300, and the cycle is detected using the detected signal. Was changed to generate the bulk bias voltage (Vbb). However, the bulk bias voltage generation circuit may include the bulk bias voltage detector 300 and may independently use the boosted voltage detector 100 and the external voltage detector 200. In this case, the pulse controller 421 shown in FIG. 7 should be removed, and the control signal for determining the period becomes the boosted voltage enable signal Vppen and the external voltage enable signal Vdden, respectively.

The bulk bias voltage generation circuit of the semiconductor memory device according to the present invention uses a short period of time using only the first pulse generator 410 when the latch up occurs because the external voltage Vdd or the boost voltage Vpp is low. When the bulk bias oscillation signal Vbbosc is output, the pumping is quick, and when the external voltage Vdd or the boost voltage Vpp is increased and no latchup occurs, the first pulse generator 410 is additionally provided. The second pulse generator 420 is used to output the bulk bias oscillation signal Vbbosc of a long period, thereby slowing pumping. That is, at low level external voltage (Vdd) and low level boost voltage (Vpp) where the driving force of the bulk bias pump needs to be large, pumping is performed quickly to generate a sufficient amount of current, and requires little current consumption. In the region of normal operation, there is an effect that can generate a stable bulk bias voltage (Vbb) by slowing the pimping.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents are included in the scope of the present invention. Should be.

1 is a circuit diagram of a general latch up structure;

2 is a circuit diagram of a general CMOS operating principle;

3 is a block diagram of a bulk bias voltage generation circuit according to the prior art,

4 is a block diagram of a bulk bias voltage generation circuit of a semiconductor memory device according to the present invention;

5 is a circuit diagram of a boosted voltage detector, an external voltage detector, and a bulk bias detector shown in FIG. 4;

6 is a block diagram of a bulk bias oscillator shown in FIG. 4;

7 is a circuit diagram of the bulk bias oscillator shown in FIG. 6, and

8 is a voltage waveform diagram illustrating an operation of a bulk bias voltage generation circuit of a semiconductor memory device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

100: boosted voltage detection unit 110: boosted voltage divider 120: boosted voltage comparison unit

200: external voltage detector 210: external voltage divider 220: external voltage comparator

300: bulk bias voltage detector 310: bulk bias voltage divider

320: bulk bias voltage comparison unit 400: bulk bias oscillation unit

410: first pulse generator 420: second pulse generator

Claims (14)

A detector for generating an enable signal by comparing an input voltage and a reference voltage, An internal voltage detector configured to compare an internal voltage and an internal reference voltage to generate an internal voltage enable signal; An internal voltage oscillator configured to receive the enable signal and the internal voltage enable signal and generate an internal voltage oscillation signal having a variable period; An internal voltage pump unit configured to generate the internal voltage in response to the internal voltage oscillation signal, The internal voltage oscillator includes a plurality of oscillation signal generators, thereby selectively providing a path of the internal voltage oscillation signal having a quantitative period difference according to the level of the input voltage. Generating circuit. The method of claim 1, The detection unit, An input voltage divider for dividing the input voltage to output a divided voltage; And an input voltage comparator configured to compare the divided voltage and the potential level of the reference voltage to output the enable signal. The method of claim 1, The internal voltage detector, An internal voltage divider for dividing the internal voltage to output an internal divided voltage; and And an internal voltage comparator configured to compare the internal division voltage and the potential level of the internal reference voltage to output the internal voltage enable signal. The method of claim 1, The internal voltage oscillator, A first oscillation signal generator for outputting the internal voltage oscillation signal in response to the internal voltage enable signal and the pulse oscillation signal; And a second oscillation signal generation unit configured to control whether or not a predetermined time delay is delayed with respect to the internal oscillation signal in response to the enable signal and the internal voltage oscillation signal, and output the pulse oscillation signal. Bulk bias voltage generation circuit. The method of claim 4, wherein The second oscillation signal generator, A pulse unit outputting a pulse signal in response to the enable signal and the internal voltage oscillation signal; A pulse delay unit configured to control whether or not the predetermined time delay with respect to the internal voltage oscillation signal in response to the enable signal and the internal voltage oscillation signal, and output the pulse delay signal; And a signal combiner for logically combining the pulse signal and the pulse delay signal to output the pulse oscillation signal. The method of claim 5, wherein The pulse unit, When the enable signal is enabled, the level of the pulse signal is controlled in response to the internal voltage oscillation signal, And disabling the pulse signal regardless of the internal voltage oscillation signal when the enable signal is disabled. The method of claim 5, wherein The pulse delay unit, When the enable signal is enabled, the pulse delay signal is disabled regardless of the internal voltage oscillation signal. And if the enable signal is disabled, controlling the level of the pulse delay signal in response to the internal voltage oscillation signal. The method of claim 5, wherein The signal combination unit, When the pulse delay signal is disabled, the level of the pulse oscillation signal is controlled in response to the pulse signal, And if the pulse signal is disabled, controlling the level of the pulse oscillation signal in response to the pulse delay signal. The method according to any one of claims 1 to 8, The input voltage is, A bulk bias voltage generation circuit of a semiconductor memory device, characterized in that the boost voltage. The method according to any one of claims 1 to 8, The input voltage is, A bulk bias voltage generation circuit of a semiconductor memory device, characterized in that the external voltage. The method according to claim 1, wherein The internal voltage is, A bulk bias voltage generation circuit of a semiconductor memory device, characterized in that it is a bulk bias voltage. The method of claim 1, The detection unit, And a boost sensing unit configured to generate a boost enable signal by comparing the boosted voltage to the boosted reference voltage. The method of claim 1, The detection unit, A bulk bias voltage generation circuit of a semiconductor memory device, characterized in that the external voltage sensing unit for generating an external enable signal by comparing an external voltage and an external reference voltage. The method of claim 1, The detection unit, A boost detector configured to compare the boost voltage and the boost reference voltage to generate a boost enable signal; and And an external voltage detector configured to compare an external voltage with an external reference voltage to generate an external enable signal.

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