KR970055367A - Precharge Signal Generators in Semiconductor Devices - Google Patents

Precharge Signal Generators in Semiconductor Devices Download PDF

Info

Publication number
KR970055367A
KR970055367A KR1019950059502A KR19950059502A KR970055367A KR 970055367 A KR970055367 A KR 970055367A KR 1019950059502 A KR1019950059502 A KR 1019950059502A KR 19950059502 A KR19950059502 A KR 19950059502A KR 970055367 A KR970055367 A KR 970055367A
Authority
KR
South Korea
Prior art keywords
precharge signal
stage
signal generator
delay
buffer
Prior art date
Application number
KR1019950059502A
Other languages
Korean (ko)
Other versions
KR0155937B1 (en
Inventor
김응만
민병언
박민철
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950059502A priority Critical patent/KR0155937B1/en
Publication of KR970055367A publication Critical patent/KR970055367A/en
Application granted granted Critical
Publication of KR0155937B1 publication Critical patent/KR0155937B1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)

Abstract

반도체장치의 프리차지 신호 발생기가 포함되어 있다. 본 발명은 제1버퍼단이 비트라인 프리차지 신호의 라이징(Rising)을 워드라인 프리차지 신호의 라이징보다 더 빨리 해줌으로써 스큐를 방지하고, 또한 제2버퍼단이 비트라인 프리차지 신호의 폴링(Falling)을 워드라인 프리차지 신호의 폴링보다 더 늦게 해줌으로써 스큐를 방지할 수 있는 장점이 있다.A precharge signal generator of the semiconductor device is included. The present invention prevents skew by allowing the first buffer stage to raise the bit line precharge signal faster than the rising of the word line precharge signal, and the second buffer stage to fall the bit line precharge signal. By delaying the delay of the word line precharge signal, the skew can be prevented.

따라서 메모리셀 부분에서의 DC 전류 패쓰를 방지함으로써 불필요한 전류소모를 없앨 수 있다.Therefore, unnecessary current consumption can be eliminated by preventing the DC current path in the memory cell portion.

Description

반도체장치의 프리차지 신호 발생기Precharge Signal Generators in Semiconductor Devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 프리차지 신호 발생기의 회로도이다.3 is a circuit diagram of a precharge signal generator according to the present invention.

제4도는 제3도에 대한 타이밍도이다.4 is a timing diagram with respect to FIG.

Claims (7)

반도체장치의 프리차지 신호 발생기에 있어서, 클락을 입력으로 받아 딜레이시키는 제1딜레이단과, 상기 제1딜레이단의 출력을 받아 딜레이시키는 제1버퍼단과, 상기 제1딜레이단의 최종 인버터의 입력단에 접속되는 또다른 인버터의 출력과 상기 클락을 입력으로 하는 제2딜레이단과, 상기 제2딜레이단의 출력을 받아 딜레이시키는 제2버퍼단으로 이루어지는 딜레이 신호 생성수단; 상기 클락에 게이트가 접속되고 소오스가 공급전원에 접속되는 제1피모스 트랜지스터와, 상기 제1버퍼단의 출력단에 게이트가 접속되고 소오스가 공급전원에 접속되는 제2피모스 트랜지스터와, 상기 제2딜레이단의 출력단에 게이트가 접속되고 소오스가 접지에 접속되며 드레인이 상기 제1 및 제2피모스 트랜지스터의 드레인들에 접속되는 제1엔모스 트랜지스터로 이루어지는 워드라인 프리차지 신호 생성수단; 상기 클락에 게이트가 접속되고 소오스가 공급전원에 접속되는 제3피모스 트랜지스터와, 상기 제1딜레이단의 출력단에 게이트가 접속되고 소오스가 공급전원에 접속되는 제4피모스 트랜지스터와, 상기 제2버퍼단의 출력단에 게이트가 접속되고 소오스가 접지에 접속되며 드레인이 상기 제3 및 제4피모스 트랜지스터의 드레인들에 접속되는 제2엔모스 트랜지스터로 이루어 지는 비트라인 프리차지 신호 생성수단을 구비하는 것을 특징으로 하는 반도체장치의 프리차지 신호 발생기.A precharge signal generator of a semiconductor device, comprising: a first delay stage for receiving a clock as an input, a first buffer stage for receiving and delaying an output of the first delay stage, and an input terminal of a final inverter of the first delay stage; Delay signal generation means comprising an output of another inverter, a second delay stage for inputting the clock, and a second buffer stage for receiving and outputting the output of the second delay stage; A first PMOS transistor having a gate connected to the clock and a source connected to a supply power supply, a second PMOS transistor having a gate connected to an output terminal of the first buffer terminal and a source connected to a supply power supply, and the second delay Word line precharge signal generation means comprising a first NMOS transistor having a gate connected to an output terminal of the stage, a source connected to ground, and a drain connected to drains of the first and second PMOS transistors; A third PMOS transistor having a gate connected to the clock and a source connected to a supply power supply, a fourth PMOS transistor having a gate connected to an output terminal of the first delay stage and a source connected to a supply power supply, and the second And a bit line precharge signal generating means comprising a second NMOS transistor having a gate connected to an output terminal of the buffer stage, a source connected to ground, and a drain connected to the drains of the third and fourth PMOS transistors. A precharge signal generator for a semiconductor device. 제1항에 있어서, 상기 제1딜레이단이 다수의 홀수개 인버터로 구성되는 것을 특징으로 하는 반도체장치의 프리차지 신호 발생기.The precharge signal generator of claim 1, wherein the first delay stage comprises a plurality of odd-numbered inverters. 제1항에 있어서, 상기 제1버퍼단이 2개의 인버터로 구성되는 것을 특징으로 하는 반도체장치의 프리차지 신호 발생기.The precharge signal generator of claim 1, wherein the first buffer stage comprises two inverters. 제1항에 있어서, 상기 제1버퍼단에 의해 비트라인 프리차지 신호의 라이징이 워드라인 프리차지 신호의 라이징보다 더 빨리 이루어지는 것을 특징으로 하는 반도체장치의 프리차지 신호 발생기.2. The precharge signal generator of claim 1, wherein the rising of the bit line precharge signal is faster than the rising of the word line precharge signal by the first buffer stage. 제1항에 있어서, 상기 제2딜레이단이 낸드게이트와 상기 낸드게이트의 출력을 인버팅시키는 인버터로 구성되는 것을 특징으로 하는 반도체장치의 프리차지 신호 발생기.The precharge signal generator of claim 1, wherein the second delay stage comprises a NAND gate and an inverter for inverting an output of the NAND gate. 제1항에 있어서, 상기 제2버퍼단이 2개의 인버터로 구성되는 것을 특징으로 하는 반도체장치의 프리차지 신호 발생기.The precharge signal generator of claim 1, wherein the second buffer stage comprises two inverters. 제1항에 있어서, 상기 제2버퍼단에 의해 비트라인 프리차지 신호의 폴링이 워드라인 프리차지 신호의 폴링보다 더 늦게 이루어지는 것을 특징으로 하는 반도체장치의 프리차지 신호 발생기.2. The precharge signal generator of claim 1, wherein the second buffer stage polls the bitline precharge signal later than the polling of the wordline precharge signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950059502A 1995-12-27 1995-12-27 Free-charge signal generator for semiconductor equipment KR0155937B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950059502A KR0155937B1 (en) 1995-12-27 1995-12-27 Free-charge signal generator for semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950059502A KR0155937B1 (en) 1995-12-27 1995-12-27 Free-charge signal generator for semiconductor equipment

Publications (2)

Publication Number Publication Date
KR970055367A true KR970055367A (en) 1997-07-31
KR0155937B1 KR0155937B1 (en) 1998-12-15

Family

ID=19445214

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950059502A KR0155937B1 (en) 1995-12-27 1995-12-27 Free-charge signal generator for semiconductor equipment

Country Status (1)

Country Link
KR (1) KR0155937B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100527593B1 (en) * 1998-07-21 2006-02-13 주식회사 하이닉스반도체 Bit Line Precharge Voltage (VBLP) and Cell Plate Voltage (VCP) Control Devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100527593B1 (en) * 1998-07-21 2006-02-13 주식회사 하이닉스반도체 Bit Line Precharge Voltage (VBLP) and Cell Plate Voltage (VCP) Control Devices

Also Published As

Publication number Publication date
KR0155937B1 (en) 1998-12-15

Similar Documents

Publication Publication Date Title
KR880003333A (en) Dynamic Random Access Memory with Improved Refresh Timing
KR970017680A (en) Semiconductor memory device
KR870002653A (en) Complementary semiconductor device reduces latch spill
KR0167295B1 (en) Sense amplifier circuit for low power
KR100304195B1 (en) Synchronous Semiconductor Memory Device with External Clock Signal
KR970078020A (en) Memory devices including latch circuits
KR890012319A (en) Semiconductor integrated circuit device
Foss et al. Application of a high-voltage pumped supply for low-power DRAM
KR970051107A (en) Internal power supply
KR930003150A (en) Semiconductor memory device with refresh short circuit in data retention mode
KR970055367A (en) Precharge Signal Generators in Semiconductor Devices
KR970051444A (en) Redundancy Circuit of Semiconductor Memory Device
KR920018754A (en) Semiconductor memory circuit
KR960025787A (en) Flash memory device
KR970063262A (en) Short Chip Memory System with Decoder for Pulse Word Line
KR880008527A (en) Pulse Generator of Semiconductor Memory Device
KR980004998A (en) An initial pre-charge generator of the synchronous DRAM
KR880014570A (en) Pulse Generator of Semiconductor Memory Device
KR970017637A (en) Sense Amplifier Control Circuit of Semiconductor Memory Device
KR970051338A (en) Flash memory device
KR100596771B1 (en) Address transition detector circuit
KR940002860B1 (en) Read-write circuit of ram
KR960042747A (en) Word Line Control Circuit of Semiconductor Memory
KR960038986A (en) Bit Line Pull-Up Circuit in Semiconductor Memory Devices
KR920010643A (en) Bit Line Operation Circuit of Semiconductor Memory Device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20050607

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee