JPS6142797A - Dynamic semiconductor memory device - Google Patents

Abstract

PURPOSE:To eliminate an erroneous action due to noises during amplifying data of a memory cell by providing an interrupting circuit for inhibiting a chip activating clock in a sense period. CONSTITUTION:When a chip activation/CE' clock is inputted, a timing generator circuit 3 is activated through an interrupting circuit 8, and an address inputted to a buffer 1 is latched. At this time, the buffer 1 activates the interrupting circuit 8 with the aid of a latch completion signal after the completion of the latch, and outputs the latched address to a decoder 2. A word line 9 selected by a decoder output is made at ''H'' level, and the data of a cell 4' is transmitted to a digit line 10 and amplified by a sense amplifier 6. Afterward the interrupting circuit 8 releases the activated state of the generator circuit 3 by an amplifying completion signal, which allows a CE' clock to be inputted to the circuit 3.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a dynamic semiconductor memory device.

(Prior Art) Conventionally, in a dynamic semiconductor memory device, when a chip activation clock (hereinafter referred to as CE clock) is activated, the inside of the chip is immediately activated and read/write If or refresh by an external address is performed. An operating cycle was executed, and it was impossible to reset the CE clock in the middle of this operating cycle. That is, if the CE clock is reset in the middle of an operation cycle, the following disadvantages arise. Data from a memory cell is extremely small, and resetting the CE clock without sufficient sensing will cause data destruction during read/write operations or freshening. For this reason, it was necessary to prohibit any input of electrical noise, whiskers, etc. that would otherwise reset the CE clock during the operation cycle after activation of the CE clock.

(Problems to be Solved by the Invention) An object of the present invention is to prevent the system from malfunctioning in a dynamic semiconductor memory device by preventing input of a signal that would reset the CE clock during an operation cycle after inputting the CE clock. It's all about writing.

[Means for solving problems]

According to the present invention, after the CE clock is activated, the chip activation input prohibits the input of the CE clock during the so-called sense period from before the sense amplifier amplifies the data in the memory cell until the amplification is completed. By having a cutoff circuit, a dynamic semiconductor memory element capable of eliminating malfunctions due to noise during data amplification of a memory cell is obtained.

(Example) Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention.

1 is an address input buffer, 2 is a decoder, 3 is a typing generation circuit, 4 is a memory cell array, 4' is a single memory cell, 5 is an input/output buffer, 6 is a sense amplifier, 7
8 is a read/write operation control circuit, 8 is a chip activation input cutoff circuit, 9 is a word line, and 10 is a digit line.

The operation of this embodiment is performed as follows. When the CB clock is input, the timing generation circuit 3 is activated throughout the chip activation input cutoff circuit 8, and the address input input to the address input buffer 1 is latched. At this time, after the address input latching is completed, a latch completion signal is outputted to the chip activation input cutoff circuit 8iC, and the latched address input is outputted to the decoder 2. In response to this latch completion signal, chip activation input cutoff circuit lj is activated and keeps timing generation circuit 3 in an activated state. Next, the word line 9 selected by the decoder is set to high level, the data stored in the memory cell 4 is sent to the digit line 10, and the sense amplifier 6 is all activated by the output of the decoder 2. Increase @4I data. Depending on the output state of the read/write control circuit 7, the input/output buffer 5 is controlled to perform a read operation or a write operation.In other words, even if the output of the read/write control circuit 7 is at a high level, If it is low level, it performs a read operation, and if it is low level, it performs a write operation.

After amplifying the data in the memory cell 4', the sense amplifier 6 outputs an amplification completion signal to the chip activation input cutoff circuit 8. Upon receiving this signal, the chip activation input cutoff circuit 8 releases the activation state of the timing generation circuit 3 and enables input of the CE clock to the timing generation circuit 3.

(Effects of the Invention) As described above, according to the present invention, it is possible to improve the amplification operation of memory cell data of a dynamic semiconductor memory device by more than 40E.
It is possible to realize a dynamic semiconductor memory device that is not affected by re-noise and can cut off the CE clock during periods susceptible to clock noise.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. l...Address input buffer, 2...
Decoder, 3... Timing generation circuit, 4...
...Memory cell array, 4'...Single memory cell, 5...I/O buffer, 6...
... sense amplifier, 7 ... read/write control circuit, 8 ... chip activation input cutoff circuit, 9 ...
...word line, 10...digit line. Agent Patent Attorney Isamu Uchihara ',':'
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Claims (1)

[Claims] A timing generation circuit that is activated by an input from a chip activation terminal, an address input buffer that generates an address latch end signal after latching address inputs that are sequentially controlled by the timing generation circuit, and an address input buffer that generates an address latch end signal. A decoder that selects the word line, a dynamic memory cell connected to the word line and the digit line, a sense amplifier that outputs an amplification completion signal after amplifying the data of the memory cell, an input/output buffer, and the address latch end signal. The function is to cut off the input from the chip activation terminal and maintain the timing generation circuit in the activated state, and release the cutoff of the input from the chip activation terminal by the amplification completion signal from the sense amplifier, and to What is claimed is: 1. A dynamic semiconductor memory device comprising: a chip activation input cutoff circuit having a function of making chip control possible again;