JPS6066393A - Memory driving circuit - Google Patents

Abstract

PURPOSE:To prevent storage information from damage due to the lack of the pulse width of an access clock by driving a dynamic RAM by using an OR signal between a pulse signal with prescribed width and a delay clock signal as an access clock. CONSTITUTION:A pulse B with the prescribed width is outputted from a pulse generating circuit 1 in accordance with a clock signal CS. The pulse B and the signal CS through a delay circuit 2 are applied to a NOR circuit NOR, a signal CS with wide clock width is formed by OR processing and the dynamic RAM3 is accessed by using the CS' as an access clock. Even if the pulse width of the clock CS is narrow, the storage information can be prevented from damage due to the lack of the pulse width of the access clock by the access clock CS'.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Summary of the Invention The present invention provides a dynamic random access memory (DRA)
O Concerning Improvement of Memory Drive Circuit in M) Technical Background In recent years, with the development of semiconductor technology, especially integration technology, large-capacity IC memories using LSIs have become available at low cost.

(c) Prior Art and Problems Normally, in a DRAM, accesses necessary for internal storage area selection control are performed when writing and reading are performed periodically in response to the chip select (C8) signal associated with the system address.
If 1 is a pulse with a width shorter than the specified value, not only the stored information in the memory cell array of the accessed area but also the stored information in other adjacent areas may be destroyed.

Traditionally, DRAM configurations have been obtained by arranging a large number of memory cells on the same substrate at high density, and each memory cell consists of one transistor 4 (Tr) as shown in Figure 1.
and one capacitor (consisting of 0), its input/output operation is to set the word line to high or low level, turn on the Tr, transfer the bit line level to C, write, turn on the Tr, and charge to C. 'lj+: The charge is transferred to the tip and hemp and read out.0 The charge accumulated in this C gradually changes from its original value as the leakage current that exists in the surrounding area and Haruma's II pass. The data at C will change.

1) Since RAM uses various memory cells, there is a reflexology that rewrites the level of the bit line in the read operation before C loses the memory and the stored information disappears. Flowing the movement 1-7 is performed 0 Refrenotsuyu movement is a constant lvl standard is 2 W 84
This is executed by a read operation that does not involve sending information to the outside. For example, DiI with 64 Kbit capacity
M is the beginning of 1280 - x 512 columns x 1 bit or i
:t consists of 2560-×256 columns×1 bit, and its read operation is performed by the downlink of C8 [1-via decoder:l'! Cell information is transmitted on all 512 or 256 bit lines connected to the three selected word lines, and the same number of sense amplifiers are also convex at four o'clock, and the zero sense amplifiers that perform the playback operation are usually increased by one. From the point of view of sensitivity, a flip-flop type amplifier is used that compares the outflow level of the 1 (+ low level intermediate signal pitch V41) set separately in a dummy cell, etc., and the cell information that exceeds the intermediate signal is immediately detected on the bit line. The high and low levels amplified by the sense amplifier are directly or indirectly sent out from the input/output circuit only for the bit ω selected by the column decoder, and become the readout signal. The level of the memory cell is refreshed by returning the high and low levels in the via line after amplification to the memory cell at the rising edge of the rear convexity. Therefore, if C8 is short and C-8 is disconnected and rises before signal transmission to the outside is completed due to sense amplifier amplification and readout, writing to the memory cell connected by the word line selected by 8 will not be possible. Since rewriting is performed with insufficient high and low levels, the information in the memory cell is destroyed during external read or reflow operations. In addition, in DRAM, a multi-address method is used due to restrictions on the number of input/output pins due to package dimensions, and C8 is decoded and used to select the memory area to be accessed.
In this case as well, if C-8 is narrow, the pulse width will be insufficient due to the secondary selection signal force S skew, etc., and as a result, other areas will be accessed by mistake and the IJ will be applied to the expected area. In order to eliminate the above-mentioned drawbacks, the present invention has the disadvantage that the old information is destroyed in the case of a write operation.・If the puff 11 width set in advance cannot be obtained even if the puff width force 3 is insufficient in the pump select signal (Cs), apply C8 via the drive circuit. This is intended to provide a means for avoiding destruction of information stored in an element.

(e) Structure of the Invention The object of the present invention is to provide a peripheral circuit that is close to a semiconductor dynamic random access memory element and drives the element, by receiving a clock signal in the vi element O) access and using a clock signal having a preset time width of 0. ) comprising pulse generating means for transmitting a clock signal, means for delaying the clock signal, and means for obtaining a logical sum of the output signals transmitted from both means, and inputting the clock signal to the pulse generating means and the delay means. A memory drive circuit characterized in that a logical sum signal obtained from a logical sum means is applied to a clock input terminal of the element to drive the element, thereby preventing destruction of stored information due to insufficient clock signal width when accessing the memory element. This can be achieved by providing the following.

(f) Embodiment of the Invention An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram of a memory drive circuit according to an embodiment of the present invention, and FIG. 3 (b) is a time chart thereof.

In the figure, 1 is a pulse generation circuit, 2 is a delay circuit, and 3 is a dynamic random access memory l (D
RAM) and NOR are NOR circuits.

The pulse generating circuit 1 is composed of, for example, a monostable multicircuit (MM), and is triggered by an input signal to generate and send out a pulse having a preset time length. The delay circuit 2 uses circuit elements such as a delay element or an inverter formed by a combination of an inductance (1) and a capacitor (C1) to give a preset delay time to the purchased and input signal and output A-60 in this embodiment. When a signal is inputted, the output B of the pulse generation circuit 1 becomes A as shown in Fig. 3(a).
, and the normal pulse width irxs is sent to the NOR output. A normal C8 is input to the DRAM 3. On the other hand, when the clock signal A2 having a narrow pulse width is input, the pulse generating circuit 1 sends out an output B having a wider width than A2, and the NOR output is input to the DRAM 3. NOR can be achieved by setting the pulse width of pulse generation circuit B to a width sufficient to prevent DRAM3 from malfunctioning.
The output D2 becomes C8 with sufficient pulse width, and the DRAM3
performs a normal read or refresh operation and
AM30) A memory drive circuit capable of preventing destruction of stored information is obtained.

In the above, the clock signal of the DI AM is shown as CS/CS, but especially when used in an address multi-system, etc., it is called as row address strobe (RAS), column address strobe (CAS), etc. Although the above has been described as an external circuit of the DRAD, it goes without saying that it operates in the same way even if it is provided in a common package.

(g) Detailed Description of the Invention As described in detail, the present invention provides a DRAM that prevents destruction of memory information during read operations, fresco operations, etc. caused by insufficient pulse width of the clock signal applied to the conventional DRAM. A memory driving circuit is obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a memory cell in a conventional example and an embodiment of the present invention, FIG. 2 is a block diagram of a memory drive circuit in an embodiment of the present invention, and FIG.
is the time chart. In the figure, the pulse generation circuit shown, 2 is the delay circuit, 3 is the dynamic random access memory and the beam 11'\
] Key 2 Mouth harp 3 Mouth (a) 10θ 13 Delay circuit output C2

Claims (1)

[Claims] In a peripheral circuit that is close to a semiconductor dynamic random access memory element and drives the element, a pulse generating means that receives a clock signal for accessing the element and sends out a pulse signal with a preset time width, and delays the clock. and means for obtaining the logical sum of the output signals sent from both means, inputting the clock signal to the pulse generating means and the delay means, and applying the logical sum signal obtained from the logical sum means to the clock input terminal of the element. What is claimed is: 1. A memory drive circuit that is driven by applying a clock signal to prevent the destruction of stored information due to insufficient clock signal width when accessing the memory cell.