KR940002859A - Light Enable (WE) Buffer Protection Circuit - Google Patents

Light Enable (WE) Buffer Protection Circuit Download PDF

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Publication number
KR940002859A
KR940002859A KR1019920011933A KR920011933A KR940002859A KR 940002859 A KR940002859 A KR 940002859A KR 1019920011933 A KR1019920011933 A KR 1019920011933A KR 920011933 A KR920011933 A KR 920011933A KR 940002859 A KR940002859 A KR 940002859A
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KR
South Korea
Prior art keywords
buffer
clock generator
data
write
protection circuit
Prior art date
Application number
KR1019920011933A
Other languages
Korean (ko)
Other versions
KR950010142B1 (en
Inventor
김정필
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019920011933A priority Critical patent/KR950010142B1/en
Priority to DE4322359A priority patent/DE4322359C2/en
Priority to JP5165485A priority patent/JPH06103772A/en
Publication of KR940002859A publication Critical patent/KR940002859A/en
Application granted granted Critical
Publication of KR950010142B1 publication Critical patent/KR950010142B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

다수의 I/O 패드를 갖는 메모리 디바이스에서, 데이타 리드 동작시 데이타 출력 버퍼에서 발생되는 VSS 노이즈로부터버퍼를 보호하기 위하여,버퍼(10)와 내부 라이트 클럭 발생기(30)사이에 스위치 역할을 하는버퍼 보호회로(40)를 설치하여, 데이타 라이트 동작시에는버퍼와 내부 라이트 클럭 발생기(37)를 연결시키고 데이타 리드 동작시에는 데이타 출력 버퍼(50)가 동작하기 전에버퍼 (10)와 내부 라이트 클럭 발생기(30)를 분리시키면 다음번 라이트 사이클에 대비하여 TOFF시간경과 이전에버퍼를 다시 내부 라이트 발생기(30)와 연결시켜줌으로써, 데이타 리드시 데이타 출력버퍼에서 발생되는 노이즈로 인해 라이트 사이클이 진행되는 것을 방지할 수 있다.In memory devices with multiple I / O pads, the VSS noise generated by the data output buffer during the data read operation To protect the buffer, Acting as a switch between the buffer 10 and the internal write clock generator 30 The buffer protection circuit 40 is provided so that the data write operation Connect the buffer and the internal write clock generator 37, and during the data read operation, before the data output buffer 50 operates. By separating the buffer 10 and the internal write clock generator 30, the T OFF time elapses before the next write cycle. By connecting the buffer to the internal write generator 30 again, it is possible to prevent the write cycle from proceeding due to noise generated in the data output buffer when reading the data.

Description

라이트 인에이블()버퍼 보호회로Light Enable () Buffer Protection Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 다이나믹 RAM의 리드 모디파이 라이트 사이클 타이밍 차트,2 is a read modifier write cycle timing chart of a dynamic RAM,

제3도는버퍼 보호 회로를 가진 본 발명에 따른버퍼의 블럭 다이어그램3 is According to the invention with a buffer protection circuit Buffer block diagram

제4도는 본 발명에 따른버퍼 보호 회로를 설치한 실시예를 도시한 블럭 다이어그램.4 is according to the invention Block diagram showing an embodiment in which a buffer protection circuit is provided.

Claims (2)

다수의 I/O (입/출력)패드를 갖는 메모리 디바이스에서, 데이타 리드 동작시 데이타 출력 버퍼 (50)에서 발생되는 (VSS) 노이즈로부터 라이트 인에이블() 버퍼(10)를 보호하기 위한 회로(40)로서,버퍼(10)와 내부 라이트 클럭 발생기(30) 사이에 설치되어, 데이타 라이트 동작시에는버퍼(10)와 내부 라이트 클럭 발생기(30)를 연결시키며, 데이타 리드 동작시에는 데이타 출력 버퍼 (50)가 동작하기 전에버퍼(10)와 내부 라이트 클럭 발생기(30)를 분리시키고 다음번 라이트 사이클에 대비하여 TOFF시간 경과 이전에버퍼(10)를 다시 내부 라이트 클럭 발생기 (37)와 연결시키도록 스위칭 되는 것을 특징으로 하는 라이트 인에이블() 버퍼 보호회로.In a memory device with multiple I / O (input / output) pads, write enable (VSS) noise from (VSS) noise generated in the data output buffer 50 during a data read operation. ) Circuit 40 for protecting buffer 10, Installed between the buffer 10 and the internal write clock generator 30, the data write operation The buffer 10 is connected to the internal write clock generator 30, and during the data read operation, before the data output buffer 50 is operated. Separate buffer 10 and internal write clock generator 30 and before the T OFF time elapses in preparation for the next write cycle. Light enable, characterized in that the switch to switch the buffer 10 back to the internal light clock generator 37 ( Buffer protection circuit. 제1항에 있어서, 상기 스위칭 동작을 위한 신호(SWITCH)가 CAS 신호와 OE신호의 결합에 의해 형성되는 것을 특징으로 하는 라이트 인에이블()버퍼 보호회로.The write enable of claim 1, wherein the signal SWITCH for the switching operation is formed by combining a CAS signal and an OE signal. Buffer protection circuit. ※ 참고사항：최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920011933A 1992-07-04 1992-07-04 Protecting circuit for write enable(we) buffer KR950010142B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019920011933A KR950010142B1 (en) 1992-07-04 1992-07-04 Protecting circuit for write enable(we) buffer
DE4322359A DE4322359C2 (en) 1992-07-04 1993-07-05 Semiconductor memory device
JP5165485A JPH06103772A (en) 1992-07-04 1993-07-05 Writable buffer protecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920011933A KR950010142B1 (en) 1992-07-04 1992-07-04 Protecting circuit for write enable(we) buffer

Publications (2)

Publication Number Publication Date
KR940002859A true KR940002859A (en) 1994-02-19
KR950010142B1 KR950010142B1 (en) 1995-09-07

Family

ID=19335882

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920011933A KR950010142B1 (en) 1992-07-04 1992-07-04 Protecting circuit for write enable(we) buffer

Country Status (3)

Country Link
JP (1) JPH06103772A (en)
KR (1) KR950010142B1 (en)
DE (1) DE4322359C2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100480900B1 (en) * 1998-01-13 2005-07-07 주식회사 하이닉스반도체 Semiconductor memory
KR100481827B1 (en) * 1997-05-12 2005-07-11 삼성전자주식회사 Semiconductor memory device with circuits for controlling data input/output buffer circuit
US7079443B2 (en) 1998-06-29 2006-07-18 Fujitsu Limited Semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62103898A (en) * 1985-10-31 1987-05-14 Mitsubishi Electric Corp Dynamic random access memory device
JPH0713863B2 (en) * 1989-07-20 1995-02-15 株式会社東芝 Dynamic random access memory
JPH05182466A (en) * 1991-12-27 1993-07-23 Mitsubishi Electric Corp Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100481827B1 (en) * 1997-05-12 2005-07-11 삼성전자주식회사 Semiconductor memory device with circuits for controlling data input/output buffer circuit
KR100480900B1 (en) * 1998-01-13 2005-07-07 주식회사 하이닉스반도체 Semiconductor memory
US7079443B2 (en) 1998-06-29 2006-07-18 Fujitsu Limited Semiconductor device

Also Published As

Publication number Publication date
DE4322359A1 (en) 1994-01-27
KR950010142B1 (en) 1995-09-07
DE4322359C2 (en) 1998-05-28
JPH06103772A (en) 1994-04-15

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