KR970012785A - Parallel test circuit - Google Patents

Parallel test circuit Download PDF

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Publication number
KR970012785A
KR970012785A KR1019950028368A KR19950028368A KR970012785A KR 970012785 A KR970012785 A KR 970012785A KR 1019950028368 A KR1019950028368 A KR 1019950028368A KR 19950028368 A KR19950028368 A KR 19950028368A KR 970012785 A KR970012785 A KR 970012785A
Authority
KR
South Korea
Prior art keywords
memory cells
parallel test
test circuit
data
comparison circuit
Prior art date
Application number
KR1019950028368A
Other languages
Korean (ko)
Other versions
KR100360149B1 (en
Inventor
최재명
이재진
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950028368A priority Critical patent/KR100360149B1/en
Publication of KR970012785A publication Critical patent/KR970012785A/en
Application granted granted Critical
Publication of KR100360149B1 publication Critical patent/KR100360149B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Dram (AREA)

Abstract

병렬 테스트 회로는 반도체 메모리장치의 메모리 셀들 및 데이타 전송라인들이 이상 유무를 정확하게 검출한다. 이를 위하여 상기 병렬 테스트 회로는 두개의 메모리 셀들에 서로 상반된 논리값의 데이타 동시에 기록되도록 하는 기록통로와, 상기 두개의 메모리 셀들로부터 판독되는 데이타들의 논리값을 비교하는 비교회로부와, 상기 비교회로의 출력을 출력시키는 데이타 출력통로를 갖는다.The parallel test circuit accurately detects whether memory cells and data transmission lines of the semiconductor memory device are abnormal. To this end, the parallel test circuit includes a write path for simultaneously writing data of opposite logic values to two memory cells, a comparison circuit unit for comparing the logic values of data read from the two memory cells, and an output of the comparison circuit. It has a data output path that outputs.

Description

병렬 테스트 회로Parallel test circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 제1실시예에 따른 병렬 테스트 회로를 도시하는 도면,3 is a diagram showing a parallel test circuit according to a first embodiment of the present invention;

제4도는 본 발명의 제2실시예에 따른 병렬 테스트 회로를 도시하는 도면.4 illustrates a parallel test circuit according to a second embodiment of the present invention.

Claims (1)

다수의 메모리 셀들은 구비한 반도체 메모리장치에 있어서, 두개의 메모리 셀들에 서로 상반된 논리값의 데이타 동시에 기록되도록 하는 기록통로와, 상기 두개의 메모리 셀들로부터 판독되는 데이타들의 논리값을 비교하는 비교회로와, 상기 비교회로의 출력을 출력시키는 데이타 출력통로를 구비한 것을 특징으로 하는 병렬 테스트 회로.A semiconductor memory device having a plurality of memory cells, comprising: a write path for simultaneously writing data of opposite logic values to two memory cells, a comparison circuit for comparing a logic value of data read from the two memory cells; And a data output passage for outputting the output of the comparison circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950028368A 1995-08-31 1995-08-31 Parallel test circuit KR100360149B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950028368A KR100360149B1 (en) 1995-08-31 1995-08-31 Parallel test circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950028368A KR100360149B1 (en) 1995-08-31 1995-08-31 Parallel test circuit

Publications (2)

Publication Number Publication Date
KR970012785A true KR970012785A (en) 1997-03-29
KR100360149B1 KR100360149B1 (en) 2003-01-24

Family

ID=37490491

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950028368A KR100360149B1 (en) 1995-08-31 1995-08-31 Parallel test circuit

Country Status (1)

Country Link
KR (1) KR100360149B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117686889A (en) * 2024-01-25 2024-03-12 杭州广立微电子股份有限公司 Addressable parallel test circuit, method, chip and system

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100809070B1 (en) 2006-06-08 2008-03-03 삼성전자주식회사 Parallel test circuit of semiconductor memory device and method there-of

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117686889A (en) * 2024-01-25 2024-03-12 杭州广立微电子股份有限公司 Addressable parallel test circuit, method, chip and system
CN117686889B (en) * 2024-01-25 2024-05-14 杭州广立微电子股份有限公司 Addressable parallel test circuit, method, chip and system

Also Published As

Publication number Publication date
KR100360149B1 (en) 2003-01-24

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