KR970049576A - Data write control circuit of the memory element - Google Patents

Data write control circuit of the memory element Download PDF

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Publication number
KR970049576A
KR970049576A KR1019950065843A KR19950065843A KR970049576A KR 970049576 A KR970049576 A KR 970049576A KR 1019950065843 A KR1019950065843 A KR 1019950065843A KR 19950065843 A KR19950065843 A KR 19950065843A KR 970049576 A KR970049576 A KR 970049576A
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KR
South Korea
Prior art keywords
controller
memory element
control circuit
data write
write control
Prior art date
Application number
KR1019950065843A
Other languages
Korean (ko)
Inventor
백인권
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950065843A priority Critical patent/KR970049576A/en
Publication of KR970049576A publication Critical patent/KR970049576A/en

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Abstract

본 발명은 어드레스와 복수개의 바이트 인네이블 신호를 출력하는 콘트롤러와, 상기 콘트로러에서 출력되는 복수개의 바이트 인네이블 신호에 의해 소정의 데이터를 기입 및 독출하는 제1,2메모리 소자로 구성하되, 상기 콘트롤러의 하위 32비트 데이터 라인을 칩의 32비트 출력 데이터 라인과 워드 교환되도록 하여, 서로 다른 RAM 포트와 SAM 포트를 가진 메모리 소자의 각 포트의 데이터 폭을 같게 하는 메모리 소자의 데이터 기입제어 회로에 관한 것이다.The present invention comprises a controller for outputting an address and a plurality of byte enable signals, and first and second memory devices for writing and reading predetermined data by a plurality of byte enable signals output from the controller. The lower 32-bit data line of the controller is word-exchanged with the 32-bit output data line of the chip, so as to equalize the data width of each port of the memory element having different RAM and SAM ports. It is about.

Description

메모리 소자의 데이터 기입 제어 회로Data write control circuit of the memory element

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 따른 메모리 소자의 데이터 기입 제어 회로를 나타낸 도면.1 is a diagram showing a data write control circuit of a memory device according to the present invention.

Claims (1)

어드레스와 복수개의 바이트 인네이블 신호를 출력하는 콘트롤러와, 상기 콘트롤러에서 출력되는 복수개의 바이트 인네이블 신호에 의해 소정의 데이터를 기입 및 독출하는 제1,2메모리 소자로 구성하되, 상기 콘트로러의 하위 32비트 데이터 라인을 칩의 32비트 출력 데이터 라인과 워드 교환되도록 한 것을 특징으로 메모리 소자의 데이터 기입 제어 회로.A controller for outputting an address and a plurality of byte enable signals, and first and second memory devices for writing and reading predetermined data by a plurality of byte enable signals output from the controller, And a lower 32-bit data line for word exchange with the 32-bit output data line of the chip. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950065843A 1995-12-29 1995-12-29 Data write control circuit of the memory element KR970049576A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950065843A KR970049576A (en) 1995-12-29 1995-12-29 Data write control circuit of the memory element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950065843A KR970049576A (en) 1995-12-29 1995-12-29 Data write control circuit of the memory element

Publications (1)

Publication Number Publication Date
KR970049576A true KR970049576A (en) 1997-07-29

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950065843A KR970049576A (en) 1995-12-29 1995-12-29 Data write control circuit of the memory element

Country Status (1)

Country Link
KR (1) KR970049576A (en)

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