KR970017600A - Semiconductor memory device with memory array banks with different speeds - Google Patents
Semiconductor memory device with memory array banks with different speeds Download PDFInfo
- Publication number
- KR970017600A KR970017600A KR1019950031525A KR19950031525A KR970017600A KR 970017600 A KR970017600 A KR 970017600A KR 1019950031525 A KR1019950031525 A KR 1019950031525A KR 19950031525 A KR19950031525 A KR 19950031525A KR 970017600 A KR970017600 A KR 970017600A
- Authority
- KR
- South Korea
- Prior art keywords
- array
- memory
- blocks
- memory array
- memory device
- Prior art date
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Static Random-Access Memory (AREA)
- Dram (AREA)
Abstract
1. 청구범위에 기재된 발명이 속하는 기술 분야1. TECHNICAL FIELD OF THE INVENTION
반도체 메모리 장치의 메모리 쎌 어레이 뱅크에 관한 것이다.A memory bank array bank of a semiconductor memory device.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
본 발명은 메모리를 뱅크별로 나누어 각 뱅크가 서로 다른 속도를 갖도록 하여 고속을 요하는 응용분야에는 고속의 메모리 뱅크로 저속을 요하는 응용분야에는 저속의 메모리 뱅크가 억세스되도록 하여 메모리의 효율적인 관리와 물리적 사이즈의 감축을 가져오는 메모리 어레이 뱅크를 제공한다.The present invention divides memory into banks so that each bank has a different speed so that high speed memory banks are accessed for high speed applications and low speed memory banks are accessed for low speed applications. A memory array bank is provided that results in a reduction in size.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
본 발명은 두개 이상의 메모리 쎌 어레이 블럭과, 상기 메모리 쎌 어레이 블럭들과 서브워드라인드라이버로 구성되어 서로 다른 어드레스에 의해 선택되는 메모리 쎌 어레이 뱅크들을 구비한 반도체 메모리 장치에 있어서, 상기 어드레스중 열을 지정하는 어드레스에 응답하여 상기 메모지 쎌 어레이 블럭들에 어드레스를 공급하는 컫럼디코더와, 상기 어드레스중 행을 지정하는 어드레스에 응답하여 상기 메모리 쎌 어레이 블럭들에 어드레스를 공급하는 로우디코더와, 입력된 상기 어드레스에 응답하여 메모리 쎌 어레이 블럭에 해당하는 갯수로 2의 블럭갯수제곱한만큼의 메모리 쎌 어레이 블럭중 하나의 상기 메모리 쎌 어레이 블럭을 지정한 블럭디코더와, 두개의 상기 서브워드라인드라이버사이에 위치하는 적어도 하나 이상의 상기 메모리 쎌 어레이 블럭을 제공함에 있다.The present invention relates to a semiconductor memory device including two or more memory array array blocks, and a memory array array bank including the memory array array blocks and a subword line driver selected by different addresses. A row decoder for supplying an address to the memo array array blocks in response to a specified address; a row decoder for supplying an address to the memory array array blocks in response to an address specifying a row among the addresses; At least between a block decoder designating the memory array array of one of the memory array arrays and the number of blocks corresponding to a memory array array block corresponding to the memory array array block and at least two subword line drivers. One or more of the above memory To provide a ray block.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 메모리 장치에 적합하게 사용된다.It is suitably used for semiconductor memory devices.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명에 따른 메모리 어레이 뱅크 구조의 블럭도,2 is a block diagram of a memory array bank structure according to the present invention;
제3도는 본 발명에 따른 뱅크사이즈가 다른 메모리 어레이 뱅크 구조의 블럭도,3 is a block diagram of a memory array bank structure having different bank sizes according to the present invention;
제4도는 본 발명에 따른 입출력속도가 다른 메모리 어레이 뱅크의 구조의 블럭도.4 is a block diagram of a structure of a memory array bank having different input / output speeds according to the present invention.
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950031525A KR0167685B1 (en) | 1995-09-23 | 1995-09-23 | Semiconductor memory apparatus having memory array band and with different velocity |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950031525A KR0167685B1 (en) | 1995-09-23 | 1995-09-23 | Semiconductor memory apparatus having memory array band and with different velocity |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970017600A true KR970017600A (en) | 1997-04-30 |
KR0167685B1 KR0167685B1 (en) | 1999-02-01 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950031525A KR0167685B1 (en) | 1995-09-23 | 1995-09-23 | Semiconductor memory apparatus having memory array band and with different velocity |
Country Status (1)
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KR (1) | KR0167685B1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100332469B1 (en) * | 1998-05-29 | 2002-07-18 | 박종섭 | Low power memory device by controlling the bank operation |
KR100361862B1 (en) * | 1998-12-30 | 2003-02-20 | 주식회사 하이닉스반도체 | Semiconductor memory device and sensing current reduction method |
KR100480558B1 (en) * | 1997-07-24 | 2005-06-13 | 삼성전자주식회사 | Internal voltage generating circuit and semiconductor memory device |
-
1995
- 1995-09-23 KR KR1019950031525A patent/KR0167685B1/en not_active IP Right Cessation
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100480558B1 (en) * | 1997-07-24 | 2005-06-13 | 삼성전자주식회사 | Internal voltage generating circuit and semiconductor memory device |
KR100332469B1 (en) * | 1998-05-29 | 2002-07-18 | 박종섭 | Low power memory device by controlling the bank operation |
KR100361862B1 (en) * | 1998-12-30 | 2003-02-20 | 주식회사 하이닉스반도체 | Semiconductor memory device and sensing current reduction method |
Also Published As
Publication number | Publication date |
---|---|
KR0167685B1 (en) | 1999-02-01 |
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