KR970051149A - Semiconductor memory device with double word line structure - Google Patents

Semiconductor memory device with double word line structure Download PDF

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Publication number
KR970051149A
KR970051149A KR1019950056959A KR19950056959A KR970051149A KR 970051149 A KR970051149 A KR 970051149A KR 1019950056959 A KR1019950056959 A KR 1019950056959A KR 19950056959 A KR19950056959 A KR 19950056959A KR 970051149 A KR970051149 A KR 970051149A
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KR
South Korea
Prior art keywords
swd
output
line driver
memory device
word line
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KR1019950056959A
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Korean (ko)
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차기원
전준영
이상재
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김광호
삼성전자 주식회사
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Priority to KR1019950056959A priority Critical patent/KR970051149A/en
Publication of KR970051149A publication Critical patent/KR970051149A/en

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  • Static Random-Access Memory (AREA)

Abstract

이중 워드라인 구조를 갖는 반도체 메모리장치에 대한 것이 포함되어 있다. 본 발명은 하나 또는 다수개의 어드레스를 입력으로 하여 다수개의 출력을 발생시키는 로우데코더와, 하나 또는 다수개의 어드레스를 입력으로 하여 다수개의 출력을 발생시키는 프리데코더와, 다수개의 메모리 어레이 블락과, 상기 메모리 어레이 블락에서 워드라인을 드라이브하기 위한 다수개의 서브워드라인 드라이버(SWD)영역을 구비하고, 또한 상기 각각의 서브워드라인 드라이버(SWD)영역에서 상기 로우데코더와 출력의 조합에 의해 각각의 메모리 어레이 내에서 하나의 서브워드라인(SWL)을 인에이블시키는 반도체 메모리장치에 있어서, 상기 각각의 서브워드라인 드라이버(SWD)영역에, 상기 로우데코더의 출력을 입력으로 하는 버퍼 회로와, 상기 버퍼 회로의 출력과 상기 프리데코더의 출력을 입력으로 하여 서브워드라인(SWL)을 출력하는 서브워드라인 드라이버(SWD)회로를 구비하고, 상기 하나의 버퍼 회로의 출력이 다수개의 서브워드라인 드라이버(SWD)에 입력됨을 특징으로 한다. 따라서 본 발명은 하나의 SWD 영역에서 하나의 NWEiB가 하나의 버퍼에 입력되므로 NWEiB의 부하 캐피시턴스가 감소되어, 결과적으로 SWL의 딜레이를 감소시킬 수 있고 데이터의 리드 및 리이트시의 신호의 속도지연을 방지할 수 있다.A semiconductor memory device having a double word line structure is included. The present invention provides a low decoder for generating a plurality of outputs by inputting one or a plurality of addresses, a predecoder for generating a plurality of outputs by inputting one or a plurality of addresses, a plurality of memory array blocks, and the memory. And a plurality of subword line driver (SWD) regions for driving word lines in an array block, and in each memory array by a combination of the low decoder and output in each sub word line driver (SWD) region. A semiconductor memory device for enabling one subword line (SWL) in the memory device, comprising: a buffer circuit having an output of the low decoder as an input to each of the subword line driver SWDs, and an output of the buffer circuit. And a sub-war for outputting a subword line SWL using the output of the predecoder as an input. Comprising a line driver (SWD) circuit, and characterized in that the output of the one of the input buffer circuit to a plurality of sub-word line driver (SWD). Therefore, in the present invention, since one NWEiB is input to one buffer in one SWD region, the load capacitance of the NWEiB is reduced, and as a result, the delay of the SWL can be reduced and the speed of the signal at the time of reading and writing data is reduced. Delay can be prevented.

Description

이중 워드라인 구조를 갖는 반도체 메모리장치Semiconductor memory device with double word line structure

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 실시예에 의한 이중 워드라인 구조를 갖는 반도체 메모리장치의 블럭도.2 is a block diagram of a semiconductor memory device having a double word line structure in accordance with an embodiment of the present invention.

Claims (2)

하나 또는 다수개의 어드레스를 입력으로 하여 다수개의 출력을 발생시키는 로우데코더와, 하나 또는 다수개의 어드레스를 입력으로 하여 다수개의 출력을 발생시키는 프리데코더와, 다수개의 메모리 어레이 블락과, 상기 메모리 어레이 블락에서 워드라인을 드라이브하기 위한 다수개의 서브워드라인 드라이버(SWD)영역을 구비하고, 또한 상기 각각의 서브워드라인 드라이버(SWD)영역에서 상기 로우데코더와 프리데코더의 출력의 조합에 의해 각각의 메모리 어레이 내에서 하나의 서브워드라인(SWL)을 인에이블시키는 반도체 메모리장치에 있어서, 상기 각각의 서브워드라인 드리이버(SWD)영역에, 상기 로우데코더의 출력을 입력으로 하는 버퍼 회로와, 상기 버퍼 회로의 출력과 상기 프리데코더의 출력을 입력으로 하여 서브워드라인(SWL)을 출력하는 서브워드라인 드라이버(SWD)회로를 구비하고, 상기 하나의 버퍼 회로의 출력이 다수개의 서브워드라인 드라이버(SWD)에 입력됨을 특징으로 하는 이중 워드라인 구조를 갖는 반도체 메모리장치.A low decoder generating a plurality of outputs by inputting one or a plurality of addresses, a predecoder generating a plurality of outputs by inputting one or a plurality of addresses, a plurality of memory array blocks, and a memory array block And a plurality of subword line driver (SWD) regions for driving word lines, and in each memory array by a combination of the outputs of the low decoder and predecoder in the respective subword line driver (SWD) regions. A semiconductor memory device for enabling one subword line (SWL) in the semiconductor memory device, comprising: a buffer circuit having an output of the low decoder as an input to each subword line driver (SWD) region, and an output of the buffer circuit. And a sub word line (SWL) for outputting the predecoder output as an input. A word line driver (SWD) and circuit with a semiconductor memory device having a dual word line structure, characterized in that the output of the one of the input buffer circuit to a plurality of sub-word line driver (SWD) a. 제1항에 있어서, 상기 버퍼 회로가 인버터퍼로 구성됨을 특징으로 하는 이중 워드라인 구조를 갖는 반도체 메모리장치.2. The semiconductor memory device of claim 1, wherein the buffer circuit comprises an inverter drive. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950056959A 1995-12-26 1995-12-26 Semiconductor memory device with double word line structure KR970051149A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100330527B1 (en) * 1999-01-05 2002-03-28 포만 제프리 엘 Wordline activation delay monitor using sample wordline located in data-storing array
KR100330539B1 (en) * 1999-01-05 2002-04-01 포만 제프리 엘 A robust wordline activation delay monitor using a pluarality of sample wordlines
KR100361863B1 (en) * 1999-06-29 2002-11-22 주식회사 하이닉스반도체 Semiconductor memory device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100330527B1 (en) * 1999-01-05 2002-03-28 포만 제프리 엘 Wordline activation delay monitor using sample wordline located in data-storing array
KR100330539B1 (en) * 1999-01-05 2002-04-01 포만 제프리 엘 A robust wordline activation delay monitor using a pluarality of sample wordlines
KR100361863B1 (en) * 1999-06-29 2002-11-22 주식회사 하이닉스반도체 Semiconductor memory device

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