SU1707746A1 - Turnable delay line - Google Patents

Abstract

The invention relates to the field of microelectronics and can be used to slow down the data transfer rate and provide synchronization during the exchange between memory subsystems and processor logic elements. The aim of the invention is to simplify the device and improve the accuracy of the delay by reducing the device’s own delay. Tunable delay line contains elements 1 and 2 of the front-edge delay, inverters 3 and 4. two-input element OR 5, element 6, digital-analog converter 7 with input 8. input 9 of the adjustable delay line. 2 yl

Description

FIG. I

The invention relates to microelectronics and computer technology and can be used to slow down the data transfer rate and provide synchronization during the exchange between memory subsystems and processor logic elements.

The aim of the invention is to simplify the device and improve the accuracy of the delay by reducing the device’s own delay.

Figure 1 presents the scheme of a tunable delay line; figure 2 - diagram of the scheme.

The tunable delay line contains the first 1 and second 2 elements of the leading edge delay, the first 3 and second 4 inverters, the two-input element OR 5, the element 1/1 6 and the digital-to-analog converter (DAC) 7. Input 8 of the DAC 7 is connected to the delay control bus, and the output is connected to the control inputs of the first 1 and second 2 elements of the leading edge delay.

The input 9 of the circuit is connected to the input of the first inverter 3, the output of which is connected to the input of the second element 2 of the leading edge delay, the input of the second inverter 4 and the direct input of the AND 6 element, the inverse input of which is connected to the output of the second element 2 of the leading edge, output - with the first input of the element OR 5.

The second input element OR 5 is connected to the output of the first element 1 of the leading edge delay, the input of which is connected to the output of the second inverter 4. The output of the element OR 5 is connected to the output 10 of the circuit.

The scheme works as follows.

The delay control bus at input 8 of the DAC 7 provides for the formation of output voltage at the output of the DAC 7, which has 2N discrete levels (where N is the number of input pins at input 8 of the DAC 7). This output voltage is the source of the reference voltage for elements 1 and 2 of the leading edge delay, the magnitude of the delay of which is proportional to the reference voltage and is fed to the control inputs of these delay elements. Elements 1 and 2 of the leading edge delay provide the delay of the leading edge of the pulse arriving at their inputs.

When the signal at input 9 of the circuit from logical O to logical G changes, a logical O appears at the output of the first inverter 3, and a logical 1 appears at the output of the second inverter 4, which, after a time determined by the delay value of the first

the leading edge delay element 1, appears at the output of the OR element 5, which is connected to the output 10 of the circuit. The output element And b is preserved logical O,

When the signal at input 9 of the circuit changes from logical 1 to logical O, logical 1 appears at the output of the first inverter 3, arriving at the input of the second element of the front-front delay 2, and output logical at the output of the second inverter 4. the output of the first inverter 3 a logical G appears at the output of the element AND 6, which is connected to the input of the element OR 5, and the output of the element OR 5 remains logical 1, despite the fact that at the output of the first element 1 of the leading edge there is a logical O coming in the other input of OR 5.

After a time determined by the delay value of the second element 2 of the leading edge delay, a logical G appears at the inverse input of the element AND 6 and transfers its output to the logical state O, which arrives at the input of the element OR 5. At the output of the element OR 5, which is connected to the output 10 of the circuit, a logical O is established.

Thus, the input signal of the circuit. The input to input 9 appears at the output 10 of the circuit with a delay determined by the voltage value at the output of the DAC 7. In this case, the number of discrete delay values is determined by the resolution (or number of input pins) of the digital-to-voltage converter.

Consequently, to build a tunable delay line having the same delay of both edges, it is sufficient to have two elements of the leading edge delay, the delay of which is proportional to the reference voltage specified by the digital-analog converter controlled by the digital encoding signal.

Claims (1)

Invention Formula A tunable delay line containing the first and second delay elements, characterized in that. that, in order to simplify and improve accuracy by reducing its own initial delay, the first and second inverters, the OR element, are introduced into it. And element, digital-to-analog converter, the input of which is connected to the delay control bus, and the output - to the control inputs of the first and second delay elements, the input of the first inverter is connected to the input of the device, and the output - to the input of the second ele delay element, the input of which is connected to the second inverter output of the first and the input element And, the inverse input of the delay element, the input of which is connected to the output of the secondary output with the output of the second inverter, the output delay point, and the output - from the pen-element OR is connected to the output of the device With the input of the element OR, the second. FIG. 2