JPS5552580A - Memory system control system - Google Patents

Memory system control system

Info

Publication number
JPS5552580A
JPS5552580A JP12336978A JP12336978A JPS5552580A JP S5552580 A JPS5552580 A JP S5552580A JP 12336978 A JP12336978 A JP 12336978A JP 12336978 A JP12336978 A JP 12336978A JP S5552580 A JPS5552580 A JP S5552580A
Authority
JP
Japan
Prior art keywords
address
access
registers
addresses
row
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12336978A
Other languages
Japanese (ja)
Inventor
Takeshi Murata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12336978A priority Critical patent/JPS5552580A/en
Publication of JPS5552580A publication Critical patent/JPS5552580A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)

Abstract

PURPOSE:To increase an access speed by omitting address comparison of each access by switching access control according to the indication of the pointer of an address supply part. CONSTITUTION:When addresses are supplied to address registers 9-0..., chip selection, row address and column address signals from registers 9-0... are applied to memory unit 1 by low-level outputs of pointers 11-0... corresponding to registers 9-0...; the row address is latched by data latch 5 and the column address is supplied to column selection part 6 to attain access to memory chips 2-0.... Next, + or -alpha counter 10 updates next addresses of registers 9-0 to generate a carry signal and unless the system is put in a cross mode, outputs of pointers 11-0 are held at high levels to make a decision that row data of next addresses are latched by latch 5; and access by column address is attained without comparison of row addresses to shorten access time, thereby increasing the access speed.
JP12336978A 1978-10-06 1978-10-06 Memory system control system Pending JPS5552580A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12336978A JPS5552580A (en) 1978-10-06 1978-10-06 Memory system control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12336978A JPS5552580A (en) 1978-10-06 1978-10-06 Memory system control system

Publications (1)

Publication Number Publication Date
JPS5552580A true JPS5552580A (en) 1980-04-17

Family

ID=14858870

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12336978A Pending JPS5552580A (en) 1978-10-06 1978-10-06 Memory system control system

Country Status (1)

Country Link
JP (1) JPS5552580A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60160457A (en) * 1984-01-24 1985-08-22 インターナシヨナル　コンピユーターズ　リミテツド Data memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60160457A (en) * 1984-01-24 1985-08-22 インターナシヨナル　コンピユーターズ　リミテツド Data memory

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