JPH0454543A - Memory device - Google Patents

Abstract

PURPOSE:To carry out the access of a CPU having the highest priority with no delay by holding the output of an access control signal group corresponding to production of the grant signals to the access requests of the lower rank CPUs until the end of the access of the highest rank CPU. CONSTITUTION:A conflict circuit inputs a memory access request signal 6 received from a CPU having the highest priority, a clock signal 8, and a memory access signal 7 received from a CPU having the lower priority and produces the grant signals 9 in the start/end timing of the signal 6 and in the grant signal timing in a period except the access operations of the CPU of the lower priority. Furthermore the grant signal of the CPU of the highest priority is produced in the request signal timing with a memory 5 which outputs the output 11 of the corresponding access control signal group. Then the output 11 is outputted. Thus the CPU can perform an access operation at a high speed and with no delay.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to memory devices for workstations, desktop publishing, personal computers, and the like.

Conventional technology In recent years, as ablation software has become more sophisticated,
2. Description of the Related Art Processing speeds and memory capacities of workstations, desktop publishing, personal computers, etc. are becoming faster and larger, and correspondingly, semiconductor memories with faster speeds and lower costs are being used more frequently. Generally multiple C
Memory accessed by the PUs is accessed via a contention circuit that arbitrates with memory access requests from each CPU,
The contention circuit samples the request signals of the plurality of CPUs using an asynchronous clock to generate a permission signal, and
It outputs a group of access control signals corresponding to it.

Problems to be Solved by the Invention In such a conventional memory device, there is a delay M in the access operation in response to a memory access request from the highest CPU. FIG. 3 is a timing chart showing the operation of a competition circuit that processes access requests of a conventional memory device. In the figure, a memory access request signal input indicated by @) is sampled with a clock signal indicated by (1) to generate an access permission signal as indicated by (3). This operation is performed regardless of the priority of the CPU, and causes a maximum delay of one clock, which is not desirable for the CPU with the highest priority, which desires high-speed access.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a memory device that does not cause a delay with respect to a CPU with the highest priority.

Means for Solving the Problems In order to achieve the above object, the present invention provides a memory device comprising a memory and a competition circuit that inputs a group of memory access signals from a plurality of CPUs and controls access to the memory. Then, the contention circuit has the highest priority C
It inputs the memory access request signal and clock signal from the PU and the memory access request signal from other lower CPUs, and controls the start and end of the access request signal of the highest CPU except during the access operation of the lower CPU. A permission signal synchronized with the timing and a corresponding access control signal group are output to the highest CPU.
In this memory device, generation of a permission signal in response to an access request from another low-level CPU and output of a corresponding group of access permission signals are reserved until an access request is made.

Operation According to the present invention, the contention circuit generates a permission signal for the CPU with the highest priority at the timing of the access request signal, and outputs a group of corresponding access signals.

Embodiments Hereinafter, memory devices according to embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a case where the configuration of a memory device according to an embodiment of the present invention is applied to two CPUs. As shown in the figure, the contention circuit 12 receives an access request signal R from a CPU with a higher priority.
EQz and clock signal 8, low priority CPU access request signal REQ2, and the two CPUs
A memory access signal group input 13 such as data and addresses from U is input to a competition circuit 12, which outputs an access control signal to the memory 6 to be accessed. The contention circuit 12 outputs the permission signal EN1 in synchronization with the access request signal of the higher CPU except during the access operation of the lower CPU.
and latches 2 and 3, which suspend the request signal of the lower CPU while the higher CPU is accessing and generate the permission signal EN2 after the access of the higher CPU is completed, and access control corresponding to the permission signal. It is composed of a memory controller 4 that outputs a group of signals.

The operation in the above configuration will be explained. FIG. 2 is a timing chart showing the operation of the above configuration in the case where request signals from the higher and lower CPUs are input simultaneously. High level CP
ENl rises at the timing of the request signal EQ1 of the U clock, and then the request signal of the lower CPU is inhibited by the latch 2 at that timing. It ends at timing B of the clock, ENl falls at the timing when the request signal from the high-level CPU ends, and the request signal R from the low-level CPU starts at timing D of the next clock.
EQ2 is accepted and the enable signal EN2 of the lower CPU rises. That is, the request signal REQ2 of the lower CPU
is reserved for a period indicated by E in the figure, and a permission signal is generated at the timing of the higher CPU.

As described above, according to the memory device of the embodiment of the present invention, the contention circuit divides the memory access request signal and clock signal from the highest priority CPU and the other low priority CPUs.
A memory access request signal from U is input, and except during an access operation of the lower CPU, a permission signal is generated at the start and end timing of the access request signal of the highest CPU, and a permission signal is generated at the timing of the permission signal. Since the corresponding access signal group is output, the high-level CPU access is executed without delay, and the high-level CPU
High-speed access to PU is possible.

Note that the above explanation is for two CPUs, but it also applies to request signal input from a large number of CPUs.
A competition circuit can be constructed that outputs a permission signal synchronized with U and a corresponding access control signal group with priority over other low-level CPUs, and a competition circuit that performs the same operation for dynamic RAM as well as static RAM can be configured. Needless to say, it is necessary to configure the

Effects of the Invention As is clear from the above embodiments, the present invention has a memory;
In a memory device including a competition circuit that inputs a group of memory access signals from a plurality of CPUs to control access to the memory, the competition circuit receives a memory access request signal and a clock signal from a CPU with the highest priority. and a memory access request signal from another low-level CPU, and generates a permission signal synchronized with the start and end timing of the access request signal of the highest-level CPU except when the low-level CPU is performing an access operation. and a corresponding access control signal group, and suspends the generation of a permission signal and the output of the corresponding access control signal group in response to an access request from other lower-level CPUs until the access by the highest-level CPU is completed. By doing so, access by the CPU with the highest priority can be executed without delay, and a memory device capable of high-speed memory access can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a memory device according to an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the memory device according to the same embodiment, and FIG. 3 is a timing chart showing the operation of a conventional memory device. It is a chart. 6...Memory, 6...Highest priority CP, memory access request signal input from U, 7...Other low priority CPUs
8... Clock input from the highest CPU, 9... Permit signal synchronized with the request signal from the highest CPU, 1o...
・Permit signal corresponding to other low-level CPUs, 11...
・Access control signal output, 12... competitive circuit,
13... Memory access signal group input from multiple CPUs.

Claims (1)

[Claims] In a memory device comprising a memory and a competition circuit that inputs a group of memory access signals from a plurality of CPUs to control access to the memory, the competition circuit receives a memory access request signal from a CPU with the highest priority. and a clock signal and a memory access request signal from another low-level CPU, and except during an access operation of the low-level CPU, a permission signal synchronized with the start and end timing of the access request signal of the highest CPU. output a group of access control signals corresponding to the generated access control signals,
Until the access of the highest CPU is completed, other lower CPUs
A memory device configured to reserve the generation of a permission signal in response to a PU access request and the output of a corresponding access control signal group.