KR0149687B1 - Common memory access control circuit in multi-processor system - Google Patents

Abstract

The present invention relates to a multiprocessor system, and more particularly, to a common memory access control circuit of a multiprocessor system which makes it possible to smoothly use a bus for each processor by controlling the priority of the common memory access by the multiprocessor.

A multiprocessor system having a common memory of the present invention includes an upper bit processor, a lower bit processor, a common memory shared by the upper and lower bit processors, and installed between the upper and lower bit processors and the common memory, respectively. And first and second beepers receiving data signals, address signals, and control signals from lower bit processors, and common memory access signals from the upper and lower bit processors. It is composed of a common memory access control circuit that prioritizes the access request of the processor and controls to wait for the access request for the upper bit processor until the access to the lower bit processor is terminated.

Description

Common Memory Access Control Circuit in Multiprocessor System

The present invention relates to a multiprocessor system, and more particularly, to a common memory access control circuit of a multiprocessor system that makes it possible to smoothly use a bus for each processor by controlling access priorities among processors when accessing a common memory by the multiprocessor. .

In the conventional method of accessing a common memory in a multi-microprocessor system, a dual bus structure includes a local bus and a plurality of local buses connected with one or more processors, each of which is connected via a bus controller of the multiprocessor system. Access the memory by connecting the bus to common memory.

Meanwhile, a common bus multiprocessor system is a system in which a plurality of processors are connected to a memory device through a common passage, and only one processor can access memory for a given time through a time division common bus.

In FIG. 1, the upper bit processor 1 having, for example, MC68020 having 16 or 32 bit processors (CPU), and the lower bit processor 3 having, for example, Z-80, having 8 bit processors, have their own. A multiprocessor system is shown which accesses the common RAM 7 via a bus processing circuit 5 which is connected via a local bus and is an interface circuit. In FIG. 1, 9 indicates a time control unit.

In the prior art, for example, the MC68020 processor and the Z-80 processor assign priority to the MC68020 processor, which is the upper processor, for the common RAM access. Therefore, when the two processors access simultaneously, the Z-80 processor is an 8-bit processor. Because of the complexity of the circuit that constitutes the access cycle wait signal, the efficiency of the 8-bit subprocessor is inferior in the high-speed access of the common RAM for processing a large amount of information.

Accordingly, an object of the present invention is to provide an accurate priority signal to an upper bit processor when the processor requires simultaneous access in a multiprocessor system, to make the lower bit processor stand by, and to provide stable memory access time to each processor even at high speed access. It is to provide a common memory access control circuit of a multiprocessor system that can provide.

1 is a block diagram showing a configuration of a common memory access control circuit of a conventional multiprocessor system.

2 is a block diagram showing a configuration of a multiprocessor system according to an embodiment of the present invention.

3 is a detailed circuit diagram showing a configuration of a common memory access control circuit according to the present invention.

4 and 5 are signal timing diagrams of the common memory access control circuit shown in FIG.

* Explanation of symbols for main parts of the drawings

11: upper bit processor (CPU1) 12: first buffer

14: second buffer 13: low-bit processor (CPU2)

15: common memory 16: common memory access control circuit

21 to 25: 1st to 5th inverter 26 ~ 31: 1st to 6D flip-flop

39: AND gate 32 to 38: first to seventh OR gate

40: NAND gate

In order to achieve the above object, the present invention provides an upper bit processor, a lower bit processor, a common memory shared by the upper and lower bit processors, and installed between the upper and lower bit processors and the common memory, respectively. Priority is given to the access request of the upper bit processor when the first and second buffers receiving the data signal, the address signal and the control signal from the lower bit processor and the common memory access signal from the upper and lower bit processors are simultaneously received. Generates an access wait signal for the lower bit processor, outputs a buffer enable signal for the first buffer, and continues to access the upper bit processor until the access to the lower bit processor is terminated To control queued access requests Provides a multiprocessor system having a common memory, characterized in that a memory access control circuit.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

2 is a block diagram showing the configuration of a multiprocessor system according to a preferred embodiment of the present invention.

Referring to FIG. 2, the present invention is a 32-bit microprocessor (CPU), for example, the upper bit processor 11 consisting of the MC68020, the upper bit processor 11 and the data bus, address bus and data through the control signal line A first buffer (BUF1) 12 for receiving a signal DATA, an address signal ADD and a read / write signal R / W and determining the direction of each bus signal, and an 8-bit microprocessor CPU2, For example, the lower bit processor 13 made of Z-80 and the data bit DATA, the address signal ADD, and the read / write signal through the data bus, the address bus, and the control signal line. A second buffer (BUF2) 14 for receiving (R / W) and determining the direction of each bus signal, and from the upper processor 11 to the common memory access signal / CSMCPU and the lower bit processor 13; The common memory access signal (/ CSZCUP) Applying to the processor 13, applying an access termination signal (/ IACK) to the upper bit processor 11, and determining each processor (CPU) access time with the first and second buffers 12 and 14; And a common memory access control circuit (CMAC) 16 for outputting a buffer enable signal / CSMBUF.

A detailed circuit for the common memory access control circuit 16 is shown in FIG.

Referring to FIG. 3, the common memory access control circuit generates first to third 3D flip-flops 26 to generate various control signals / pr, / prdt, and / tip that determine access priority of the upper bit processor 11. , 27, 28, first and second inverters 21 and 22, first to third OR gates 32, 33 and 34, and an access termination signal (IACK) to the upper bit processor 11 And the 4D flip-flop 29 which generates the wait bit signal / WAITZCPU, the third and fourth inverters 23 and 24, the fourth OR gate 35, and the AND gate ( 39), fifth and sixth flip-flops 30 and 31 for generating buffer enable signals (/ CSMBUF and / CSZBUF) for determining respective CPU access times, fifth inverter 25, and fifth to fifth. The seventh OR gate 36, 37, 38 and the NAND gate 40 are comprised.

The operation of the common memory access control circuit of the present invention constructed as described above will be described in detail with reference to FIGS. 3 to 5 as follows.

First, the timing diagram of FIG. 4 shows the timing when only the upper bit processor 11, which is a 32-bit CPU, accesses the common memory 15. FIG. 4B which is one input of the first OR gate 32 is shown in FIG. The memory access signal (/ CSMCPU) of the low level (L) is applied to the input (D) of the first D flip-flop 26, at this time, the CPU clock (ZCLK) of the low-bit processor 13, which is an 8-bit CPU (Latched by FIG. 4A), the output of the first D flip-flop 26 outputs the first priority signal / pr in the L state (FIG. 4C).

The first priority signal / pr becomes one input of the second OR gate 23, and the output of the high level H state of the third OR gate 34 is the input of the 3D flip-flop 28. The output / tip of the 3D flip-flop 28 is brought to the H state by the latch by the ZCLK clock signal.

After that, the output of the 3D flip-flop 28 is inverted through the second inverter 22, and then an input signal in an active L state is applied to the other input of the second OR gate 33 so that the second OR gate 33 L output of) becomes an input signal of the second D flip-flop 27.

At this time, the second priority signal (/ prdt) signal having the output of the second D flip-flop 27 in the L state by the latch by the ZCLK clock passes through the fourth inverter 24, and latches the fourth D flip-flop 29. When used as a clock, the output Q of the fourth D flip-flop 29 generates the access termination signal / IACK in the active L state because the access signal / CSMCPU is in the active L state from the upper bit processor. .

This signal is a signal for notifying the upper bit processor 11 of the completion of data transmission. When the upper bit processor 11 recognizes the / IACK signal, it completes the access to the common memory 15 after its next clock cycle ( That is, the / CSMCPU) signal is brought to the H state.

When the upper bit processor 11 accesses the common memory 15 as described above, the / CSZCPU signal is in the active L state and the signal passing through the first inverter 21 becomes the input of the first OR gate 32. The signal goes into the H state.

At this time, the first priority signal / pr, which is the output Q signal of the first D flip-flop 26, becomes an active H state because the input signal is H state as shown in FIG.

Therefore, since the first priority signal / pr has not been generated, the second priority signal / prdt, which is an output signal of the second flip-flop 27, becomes H state, and L passes through the fourth inverter 24. Since the signal does not make the rising latch click of the fourth D flip-flop 29, the fourth D flip-flop 29 is kept in the preset state, and thus the / IACK signal is kept in the active H state so that the upper bit processor 11 Keeps the second access cycle idle.

Next, when each processor 11, 13 enables the first and second buffers 12, 14 to which data DATA, an address ADD, and a control signal R / W are applied, will be described. .

The operating clock ZCLK (FIG. 5A) of the high-bit processor 13 is inverted through the fifth inverter 25 and then input to the input latch clocks of the fifth and sixth Flimflops 30 and 31. When the upper bit processor 11 accesses the common memory 15, that is, the lower bit processor access wait signal / WAITZCPU (FIG. 5G) is input as the input of the 5D flip-flop 30. After the half cycle of ZCLK, the input of the 5D flip-flop 30 is made, and the output (/ trgm) (figure 5) of the 5D flip-flop 30 (figure (H)) is output to the active L after the half cycle of ZCLK. The first buffer 12 connected to the upper bit processor 11 is enabled by setting the state in which the signal becomes active L as the output signal / CSMBUF of the fifth OR gate 36. (Fig. 5 (J)).

Meanwhile, we will look at the case where each processor simultaneously accesses the buffer enable signal. When each processor 11 and 13 requests access at the same time, the / pr signal (FIG. 5D) is in the H state, and when the upper bit processor 11 does not actually access the common memory 15, that is, When the / WAITZCPU signal is in the H 'state, the output of the NAND gate 40 is applied to the input terminal of the 6D flip-flop 31 when the output of the sixth OR gate 937 is in the L state.

At this time, an input generates an output (/ trgz) signal fifth (1) on the 6D flip-flop 31 after the ZCLK half cycle, and then inputs the input and output signals of the 6D flip-flop 31 as inputs. By the 7 OR gate 38, the / CSZBUF signal for enabling the second buffer 14 goes into the L state during the time that the two inputs maintain the L state in common, and the second buffer 14 is enabled.

As described above, according to the present invention, when the upper and lower processors access simultaneously using the operation clock of the lower bit processor as the latch clock of the D flip-flop, a priority signal (/ pr) giving priority to the upper bit processor is provided. To ensure accuracy, the access of the lower bit processor is easily controlled by the signals generated by its operation clock.

In addition, when enabling the buffers connected to each processor, the spare time is allowed during the half-cycle operation clock of the low-bit processor, thereby providing stable memory access time for each processor by eliminating the instability of each bus state through the buffer even in high-speed access. .

Claims (3)

An upper bit processor, a lower bit processor, a common memory shared by the upper and lower bit processors, and between the upper and lower bit processors and the common memory, respectively, to provide a data signal and an address signal from the upper and lower bit processors. And the first and second buffers receiving the control signal and the common memory access signal from the upper and lower bit processors simultaneously give priority to the access request of the upper bit processor and generate an access wait signal for the lower bit processor. And outputting a buffer enable signal for the first buffer, and controlling to wait for an access request for the higher bit processor until the access to the lower bit processor is terminated when the access request from the higher bit processor continues. Composed of common memory access control circuit That a common multi-processor system as claimed in memory access control circuit. 2. The common memory access control circuit of claim 1, wherein the common memory access control circuit is configured to prioritize first and second priority in order to prioritize access of the upper bit processor in response to an operation clock of the lower bit processor and an access signal of the upper and lower bit processors. Priority signal generating means for generating a signal, standby signal generating means for generating a standby signal for a lower bit processor according to said first priority signal, and said second priority signal and an access signal of an upper bit processor An access end signal generating means for generating an access end signal according to the first access signal, first enable signal generating means for enabling the first buffer in response to a wait signal for the operation clock and the lower bit processor, and the operation; A clock, a first priority signal, the wait signal, and an access signal for the lower bit processor A second buffer for the memory access common control of the multiprocessor system, characterized in that consisting of the second enable signal generating means to enable circuit in accordance with. 2. The common memory access control circuit according to claim 1, wherein a spare time of a predetermined time is set between the enable of each buffer.