JPS60157657A - Electronic computer - Google Patents

Abstract

PURPOSE:To execute an operation at a high speed as the whole system by constituting so that a bus line can be rearranged, and making the bus line have several fundamental arithmetic functions. CONSTITUTION:A connection between each bus line of an address bus A, a data bus D, a control bus C, etc., or between each memory bank is constituted so that it can be rearranged dynamically, and several fundamental arithmetic parts 8 are provided in the bus line. A local bus controller LBC changes a connection between general buses B1-B3 and local buses A, D and C, performs one of several fundamental arithmetic to a data on the bus line, and loads it on the local bases A, D and C, or the general buses B1-B3. When a signal on the control bus C is controlled by an output data from the memory bank, read and write can be executed, processing simultaneously the contents of plural memory banks without executing a request to a CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a wiring structure between bus lines in an electronic computer, and in particular, to realize high-speed calculation, the bus line is made into a controller pull, and a calculation function is provided therein. It concerns computer architecture.

Generally, a common bus system is adopted in electronic and slave computers, and bus lines such as an address bus, take bus, and control bus are fixed. This is one of the causes of the so-called Neumann bottle neck. In order to realize all high-speed calculations, high-speed C
You can use a PU (Central Processing Unit) and high-speed memory, but in general, considering heat generation, space, and 7 actors,
It becomes complicated and expensive. Moreover, no matter how fast the CPU is,
Even if -1 is used, high-speed calculations exceeding the CPU's inherent cycle time are impossible.

Does the present invention address these points? It is an attempt to solve
Even when using a cheap and slow memo IJ ffi,
The aim is to make the calculation speed of the entire system extremely high. The computer architecture for ultra-fast calculations of the present invention enables direct calculations between memories without CPU intervention. It features some basic functions. Such a bus-line is called a controller-pull bus. C, in fields such as computer graphics and computer vision, the same calculations are often repeated for each point on both sides, so by using the above constituent sounds, the performance speed can be reduced. It is expected that it will become dramatically faster. The following (9) side? I will explain while referring to it.

The role of each block kNf2 will be explained with reference to Figure 1.

CPUI, memory bank 2~ quadrupled in the top square
The 4th grade parts are called local blocks: tl, A, D,
C are the addresses on the local bus: bus, data, bus, control, bus, respectively.

represent. Among the control signals, there are also signals generated from addresses, such as 0 inch and chip select, but they are described separately here for convenience. There is generally a plurality of memory banks), and the CPU-1 can be connected to the local bus to handle all local operations. local·
There is no contention on bus vH1, and operations can be serialized roughly in proportion to the number of local blocks. Moreover, one of the major features is that side-stage indirect modification addressing can be executed in one instruction and can be easily pipelined. Although the control/arithmetic unit and the input/output/counter unit are depicted separately here, there is no need to strictly distinguish them, and they may be included in one local block.

The control/arithmetic unit has relatively complex operations such as floating-point operations, parallel FFT operations using FUT, and i* operations that give priority to take from each memory bank. Make it functional. Is the internal part required a peripheral device? It is used as an interface with 1. This system%-
V RAM (Video Random Access Memory)
When used as a multiplying D/A (digital/analog) converter, the transparency of the object can be easily increased, and concealment can be erased at high speed.
It is especially effective in fields such as computer graphics. The counter section is necessary to make it possible to automatically omit calculations without the intervention of the CPU, and puts its output data on the general-purpose bus line. A detailed example of its use will be fully explained later using figures.

Local bus controller (LBCI・~LBC4
) is a characteristic part of the present invention, and includes general-purpose buses B1 to Bn and local buses A, D,
You can change the connection between 0 and 0, or perform some basic operations on data on the bus input, and put it on the local bus or general-purpose bus. Here, g(Nk) is performed, which is relatively simpler and faster than the calculation in the control/calculation section.

The method of wiring within the local bus block and the type of calculation performed therein are determined by signals from the LBC unit controller. Since the LBC unit controller 5 can be further controlled by other controllers, the controllers can be controlled one after another by other controllers, but in FIG. 1, only one stage of LBC is shown for simplicity.
This is written by the controller. The LBC unit control signal is transmitted on line 6, and the system clock is transmitted on line 7.

Furthermore, the next major feature is the drawing buses labeled B1 to Bn. In the commonly used common bus system, the Has line is used for the address bus, data bus,
Although the control bus line is divided into two parts, the role of each bus line is fixed from the beginning. B1~ in Figure 1
In Bn (generally n≧3), each role is not fixed; sometimes it is connected to the address bus of the local bus, and sometimes it is connected to the data bus.
The address bus of one memory bank is connected to the data bus of another memory bank. Its control is performed by the local bus controller mentioned above.

In Figure 1, B1 to Bn are shown separately for convenience, but as just mentioned, the dedicated bus connects to various local buses, and the connections change dynamically, so B1 to Bn are not necessarily written as B1 to Bn.
There is no need to divide the wires into wires such as 1 to Bn, but it may simply be considered as a collection of several dozen wires.

FIG. 2 is a conceptual diagram for explaining all the functions of the local bus controller. In this figure, fd, B1, B2. B
3 shows an example when each bus is used as an address bus, a data bus, and a control bus. Arithmetic unit 8
Are some basic operations (6)? This is the part to do. In this figure, if the calculation unit 8
If the input signal sound is output as an output signal without performing any calculations, the result will be the same as the common bus method. The effective use of the local bus controller LBC is explained in the application examples of FIGS. 3 and 9.4. The bus line connection method and type of calculation in the local bus controller are determined by control signals from the LBC unit controller. Timing generator 1
1 is for generating all the timings necessary for latching, taking in, sending out data, etc. in response to a clock for synchronously operating the system. data latch 10
The section marked ``is required when using a general-purpose bus for time-sharing, which will be described later, or when using a relatively slow memory IJ-2. The signals on the control bus can be controlled by the output data from the memory bank without depending on the CPU. The contents of several memory banks can all be read and written simultaneously. In addition, calculations are performed in parallel in each local block, making it easy to implement in a pipeline, dramatically improving performance speed. Particularly in fields such as graphic processing, where a certain fixed operation is often repeated on a large number of points, the effect V is large. Bus Bl, B2. B3 is connected to the data latch circuit 10 by bus changeover switches 12-14.

Figures 3 and 4 illustrate an example application using a controller pull bus. Please refer to these figures in order. Figure 3 is the focus/reverse angle of the pigeon coop with a 16-pin address. Take advantage of Bit Reverse! =
If it were to be executed, an upper sand step would be required, but if the address bus is a controller pull, it can be easily executed by simply replacing the connections as shown in this figure. L'B
C5°LBC6 is the local bus controller.

Figure 4 shows memory banks 13-16 without CPU intervention.
An example is shown in which data is transferred from memory bank 15 to memory bank 16 by indirect addressing. The arrows indicate the flow of data, and R and W represent the Read signal and Write signal, respectively. Kara/
The output of jZ17 is connected to the address buses of memory bank 13 and memory bank 14, and stops after outputting the end address from the start address. Are the data buses of memory bank 13 and memory bank 14 each an adder? through memory bank 15 and memory bank 1
6 address bus. Adders in local bus controllers 18-22 are used to offset addresses. memory bank 1
3 and memory bank 14 are represented by A2 and A3, the addresses of memory bank 15 and memory bank 16 are 1 for A2+ and 2 for A3+, respectively. +K 1)
Earth.

3 is added to the contents of memory bank 16 (A3
2) Transferred to location i. In this example, the counter output and the addresses of memory bank 13 and memory bank 14 are
Although the buses are directly connected, arithmetic functions such as calculations and comparison judgments can be added along the way.

As described above, calculations that used to require a lot of calculations using mechanical devices can now be performed easily and quickly, and in addition, using C++
Can be executed without PU intervention. The operational speed of the system as a whole increases as the number of local blocks increases, but if the number of general-purpose bus lines required increases at the same time, the number of changeover switches in the local bus controller also increases. For example, there are IVI x N combinations of M general-purpose bus lines and N local bus lines, so it becomes almost impossible to cover all combinations as M and N increase. . However, when the number of local blocks is small, the effect of parallel processing JJ! , l Jia small. During this time fil k
Another solution is to use the bus lines in a time-divided manner.

FIG. 5 shows a timing chart when the general-purpose bus lines are used in a time-divided manner. One cycle time includes several time-sharing clocks as shown in Figure 5 (1), and each local bus uses the same bus line of the general-purpose bus in a determined phase. Use only for a period of . (If the ff-cul block is a low-speed memory, etc., it will not be possible to access it during the ■ phase, so it is necessary to -H launch the data jZ. I looked at the data at 7A's.

The timing generator generates a trigger pulse for that purpose, and also adjusts the data output timing and
This is for controlling the state. When used as a VRAM, additional signals such as vertical synchronization and horizontal synchronization are required. Although three types of clocks are shown in Figure 5, they can also be placed on one bus line by applying modulation.

When using a general-purpose bus line in a time-division manner, the entire system must operate synchronously using the synchronization signal shown in FIG. 5(3). By using the bus lines in a time-division manner in this way, the number of bus lines can be reduced by the amount of time-division. In the example shown in Fig. 5, it is 17 m. FIG. 5(2) shows the system cycle.

As explained above, in the present invention, the connections between each local bus can be completely reassigned dynamically, and the local bus controller is equipped with an arithmetic function, which previously required several steps in machine language. It has become easier and faster to perform various calculations, and even different types of calculations can be executed in parallel. Also, if you use the entire counter section, the CPU
It is also possible to perform all kinds of operations without having to perform all the necessary functions.

The calculation circuit of the local bus controller is an ordinary C
TT much faster than PU cycle time
L() transistor, transistor, logic) and ECL
(emitter-coupled logic), etc., so basic operations can be performed during data transfer between local buses.

Even in the case of complex operations, the structure is such that they can be easily put into a pipeline to reduce time loss. Therefore, even if you use inexpensive, slow, and large-capacity memos +7 = j, you can still configure an ultra-high-speed system as a whole.
It has high cost performance.

[Brief explanation of drawings]

Figure 1 is a general schematic diagram of an electronic computer using a controller pull bus, Figure 2 is a schematic diagram of a local bus controller, and Figures 3 and 4 are applications of the controller pull bus. For example, Figure 5 uses a general-purpose bus line for full time division. The timing chart is shown below. 1... Central processing unit, 2, 13, 14, 15. 16.
・・Memory bank, LBCI~LBCI O, LBC
... Local bus controller, 17 ... Counter agent Patent attorney Kei Nishi

Claims (1)

[Claims] Making the bus line controller pull, Sunawachi,
It enables dynamic relocation of connections between each bus line such as address bus, take bus, control bus, etc., or between each memory bank, and allows some basic functions to be added to the bus lines. An electronic computer that achieves ultra-high-speed calculations by providing functions such as enabling direct parallel calculations between bus lines even without the intervention of a CPU (Central Processing Unit).