CN105550147B - A kind of spi bus expansion system and its means of communication - Google Patents
A kind of spi bus expansion system and its means of communication Download PDFInfo
- Publication number
- CN105550147B CN105550147B CN201510922961.2A CN201510922961A CN105550147B CN 105550147 B CN105550147 B CN 105550147B CN 201510922961 A CN201510922961 A CN 201510922961A CN 105550147 B CN105550147 B CN 105550147B
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- Prior art keywords
- spi
- multiplexer
- microprocessor
- spi interface
- expansion system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
Abstract
The present invention provides a kind of spi bus expansion system and its means of communication, including a microprocessor and four multiplexer (MUXs；The microprocessor is connected with the SPI interface of CPU；The input terminal of four multiplexer (MUXs is connected with four pins of the SPI interface of CPU respectively, and the SPI interface after an extension is formed by the pin all the way of the output terminal of each multiplexer (MUX；The address choice pin of four multiplexer (MUXs is connected with the address choice pin of microcontroller respectively.The spi bus expansion system and its means of communication of the present invention is easy to a SPI interface expanding to multiple SPI interfaces, so as to save GPIO resources；Each SPI interface after extension has the communication characteristic identical with former SPI interface；Without excessive cost, strong applicability.
Description
Technical field
The present invention relates to a kind of bus circuit and its means of communication, more particularly to a kind of spi bus expansion system and its
The means of communication.
Background technology
Serial Peripheral Interface (SPI) (Serial Peripheral Interface, SPI) is a kind of high speed, full duplex, synchronization
Communication bus, and four lines are only taken up on the pin of chip, have not only saved the pin of chip, moreover it is possible to be the cloth of PCB
Office saves space, there is provided convenient.
SPI can make MCU communicate in a serial fashion with various ancillary equipment to exchange information.Periphery, which is set, to be included
FLASHRAM, network controller, LCD display drivers, A/D converter and MCU etc..Spi bus system can directly with each factory
The multiple standards peripheral components direct interface of family's production, the interface generally use 4 lines：Serial time clock line (CLK), host are defeated
Enter/slave output data line MISO, host output/slave input data line MOSI and the effective piece of low level select data cable CS.
Just it is being in order at this characteristic easy to use, nowadays more and more integrated chips SPI communication agreement.
With the continuous development of Embedded Application, the SPI equipment accessed in embedded device is also more and more.When access
When SPI number of devices exceeds the limitation of CPU, generally realized using extra GPIO pins.
But such processing mode has following deficiency：
(1) the CPU pin resources of preciousness are occupied；
(2) SPI communications are carried out by way of the SPI interface of GPIO extensions is generally simulated using software so that communication
Speed is restricted.
The content of the invention
In view of the foregoing deficiencies of prior art, it is an object of the invention to provide a kind of spi bus expansion system and
Its means of communication, the extension of spi bus is realized using microprocessor and several multiplexer (MUXs, and need not take CPU pins
Resource, strong applicability.
In order to achieve the above objects and other related objects, the present invention provides a kind of spi bus expansion system, including one micro-
Processor and four multiplexer (MUXs；The microprocessor is connected with the SPI interface of CPU；Four multiplexer (MUXs
Input terminal is connected with four pins of the SPI interface of CPU respectively, is made of the pin all the way of the output terminal of each multiplexer (MUX
SPI interface after one extension；Address choice of the address choice pin of four multiplexer (MUXs respectively with microcontroller is drawn
Foot is connected.
According to above-mentioned spi bus expansion system, wherein：The microprocessor uses microcontroller.
According to above-mentioned spi bus expansion system, wherein：The number of SPI interface after extension and the road of multiplexer (MUX
Number is identical.
Meanwhile the present invention also provides a kind of extended method according to any of the above-described spi bus expansion system, including
Following steps：
When CPU is communicated with preparing SPI equipment, CPU sends SPI interface numbering to microcontroller；Microcontroller is according to institute
State SPI interface numbering control multiplexer (MUX and connect corresponding extended SPI interface, so as to connect CPU and the SPI interface connected
Between SPI passages；
When CPU and SPI equipment are communicated, microcontroller persistently monitors chip selection signal；When chip selection signal is become by low level
During into high level, a SPI communication terminates, and microcontroller control multiplexer (MUX restPoses, and monitors SPI next time and lead to
News.
According to the extended method of above-mentioned spi bus expansion system, wherein：The SPI interface compiles a byte.
According to the extended method of above-mentioned spi bus expansion system, wherein：The microcontroller receives the SPI interface
After numbering, multiplexer (MUX is controlled to connect corresponding extended SPI interface by address choice pin.
According to the extended method of above-mentioned spi bus expansion system, wherein：After a SPI is communicated, microcontroller control
Multiplexer (MUX processed cuts off connected extended SPI interface.
As described above, the spi bus expansion system and its means of communication of the present invention, have the advantages that：
(1) it is easy to a SPI interface expanding to multiple SPI interfaces, so as to save GPIO resources；
(2) each SPI interface after extending has the communication characteristic identical with former SPI interface；
(3) without excessive cost, strong applicability.
Brief description of the drawings
Fig. 1 is shown as the electrical block diagram of a preferred embodiment of the spi bus expansion system of the present invention；
Fig. 2 is shown as the implementation procedure schematic diagram of the spi bus extended method of the present invention；
Fig. 3 is shown as the flow chart of the spi bus extended method of the present invention.
Component label instructions
1 microprocessor
21 multiplexer (MUXs
22 multiplexer (MUXs
23 multiplexer (MUXs
24 multiplexer (MUXs
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.It should be noted that in the case where there is no conflict, following embodiments and implementation
Feature in example can be mutually combined.
It should be noted that the diagram provided in following embodiments only illustrates the basic structure of the present invention in a schematic way
Think, then only the display component related with the present invention rather than component count, shape and size during according to actual implementation in schema
Draw, kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its assembly layout kenel
It is likely more complexity.
With reference to Fig. 1, spi bus expansion system of the invention include a microprocessor 1 and four multiplexer (MUXs (21,
22nd, 23 and 24).Microprocessor 1 is connected with the SPI interface of CPU；The input terminal of four multiplexer (MUXs (21,22,23 and 24)
It is connected respectively with four pins of the SPI interface of CPU, an expansion is formed by the pin all the way of the output terminal of each multiplexer (MUX
SPI interface after exhibition；The address choice pin (A1 and A0) of four multiplexer (MUXs (21,22,23 and 24) respectively with microcontroller
Address signal pin (A1 and A0) be connected.
Wherein, four pins of SPI interface are respectively serial time clock line (CLK), host input/slave output data line
MISO, host output/slave input data line MOSI and the effective piece of low level select data cable CS.
Preferably, microprocessor 1 uses microcontroller.
Wherein, the number for the SPI interface that spi bus expansion system of the invention is extended and the way phase of multiplexer (MUX
Together.I.e. how many road multiplexer (MUX includes, you can expands how many a SPI interfaces.
With reference to Fig. 2, when spi bus expansion system using the present invention carries out SPI communications,
When CPU prepares to be communicated with SPI equipment, the SPI interface that CPU first sends a byte to microcontroller is compiled
Number；After microcontroller receives SPI interface numbering, multiplexer (MUX is controlled to connect corresponding extension by address choice pin
SPI interface.So far, the SPI passages between CPU and the extended SPI interface connected connect completely, you can are carried out with SPI equipment
Normal SPI communications.
When CPU and SPI equipment are communicated, microcontroller persistently monitors chip selection signal (CS).When chip selection signal (CS) by
When low level becomes high level, a SPI communication terminates.Microcontroller control multiplexer (MUX restPoses, and under monitoring
SPI communication.
With reference to Fig. 3, the means of communication of spi bus expansion system of the invention comprise the following steps：
Step S1, when CPU is communicated with preparing SPI equipment, CPU sends SPI interface numbering to microcontroller；Microcontroller
Control multiplexer (MUX is numbered according to the SPI interface and connects corresponding extended SPI interface, so as to connect CPU and the expansion connected
Open up the SPI passages between SPI interface.
Specifically, when CPU prepares to be communicated with SPI equipment, CPU first sends the SPI of a byte to microcontroller
Interface index；After microcontroller receives SPI interface numbering, multiplexer (MUX is controlled to connect by chip selection signal pin corresponding
Extended SPI interface.So far, the SPI passages between CPU and the extended SPI interface connected connect completely, you can with SPI equipment
Carry out normal SPI communications.
Step S2, when CPU and SPI equipment are communicated, microcontroller persistently monitors CS signals；When CS signals are by low level
When being changed into high level, after a SPI communication, microcontroller control multiplexer (MUX restPoses, and monitors next time
SPI is communicated.
Specifically, after a SPI is communicated, microcontroller control multiplexer (MUX cuts off connected extended SPI and connects
Mouthful, it is allowed to restPose, and monitor SPI next time and communicate.
In conclusion the spi bus expansion system and method for the present invention are easy to a SPI interface expanding to multiple SPI
Interface, so as to save GPIO resources；Each SPI interface after extension has the communication characteristic identical with former SPI interface；Need not
Excessive cost, strong applicability.So the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization
Value.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (7)
- A kind of 1. spi bus expansion system, it is characterised in that：Including a microprocessor and four multiplexer (MUXs；The microprocessor is connected with the SPI interface of CPU；The input terminal of four multiplexer (MUXs is connected with four pins of the SPI interface of CPU respectively, by each multi-channel control The pin all the way of the output terminal of device forms the SPI interface after an extension；The address choice pin of four multiplexer (MUXs It is connected respectively with the address choice pin of microprocessor.
- 2. spi bus expansion system according to claim 1, it is characterised in that：The microprocessor uses microcontroller.
- 3. spi bus expansion system according to claim 1, it is characterised in that：The number of SPI interface after extension with it is more The way of road controller is identical.
- A kind of 4. means of communication of spi bus expansion system according to one of claim 1-3, it is characterised in that：Including Following steps：When CPU prepares to be communicated with SPI equipment, CPU sends SPI interface numbering to microprocessor；Microprocessor is according to institute State SPI interface numbering control multiplexer (MUX and connect corresponding extended SPI interface, so as to connect CPU and the SPI interface connected Between SPI passages；When CPU and SPI equipment are communicated, microprocessor persistently monitors chip selection signal；When chip selection signal is become by low level During high level, a SPI communication terminates, and microprocessor control multiplexer (MUX restPoses, and monitors SPI next time and lead to News.
- 5. the means of communication of spi bus expansion system according to claim 4, it is characterised in that：The SPI interface numbering For a byte.
- 6. the means of communication of spi bus expansion system according to claim 4, it is characterised in that：The microprocessor connects After receiving the SPI interface numbering, multiplexer (MUX is controlled to connect corresponding extended SPI interface by address choice pin.
- 7. the means of communication of spi bus expansion system according to claim 4, it is characterised in that：When a SPI communication knot Shu Hou, microprocessor control multiplexer (MUX cut off connected extended SPI interface.
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| CN201510922961.2A CN105550147B (en) | 2015-12-11 | 2015-12-11 | A kind of spi bus expansion system and its means of communication |
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| CN201510922961.2A CN105550147B (en) | 2015-12-11 | 2015-12-11 | A kind of spi bus expansion system and its means of communication |
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| CN105550147A CN105550147A (en) | 2016-05-04 |
| CN105550147B true CN105550147B (en) | 2018-04-24 |
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Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108255231B (en) * | 2016-12-28 | 2020-10-02 | 深圳市中兴微电子技术有限公司 | Data sampling method and chip |
| CN106959933B (en) * | 2017-03-16 | 2019-08-23 | 数据通信科学技术研究所 | A kind of method of extended bus system and bus marco |
| CN107145460B (en) * | 2017-04-13 | 2020-07-07 | 上海云统信息科技有限公司 | Expandable serial bus system and communication method thereof |
| CN110781117B (en) * | 2019-09-12 | 2020-11-20 | 广东高云半导体科技股份有限公司 | SPI expansion bus interface and system on chip based on FPGA |
| CN112636569B (en) * | 2019-10-08 | 2022-03-25 | 洪禄有限公司 | Switch type AC/DC power supply system with 10MHz time base |
| CN112069103A (en) * | 2020-09-07 | 2020-12-11 | 歌尔科技有限公司 | Method and system for communication between multiple modules and host |
| CN113032318B (en) * | 2021-03-30 | 2022-08-30 | 纵目科技（上海）股份有限公司 | Communication system based on parallel bus |
| CN114546925B (en) * | 2022-03-08 | 2022-09-02 | 合肥富煌君达高科信息技术有限公司 | Multi-device communication device and method suitable for high-speed camera |
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Effective date of registration: 20180209 Address after: No. 15, building No. 3, No. 1486, Nanjing West Road, Jingan District, Shanghai Applicant after: Shanghai Yi Electric Building Technology Co., Ltd. Address before: 200082 Tangshan Road, Hongkou District, Hongkou District, Hongkou District, Shanghai Applicant before: Shanghai Hygrand Electronic Equipment Co., Ltd. |
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